JP4003454B2 - SRAM cell structure and SRAM inspection method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an SRAM cell structure and an SRAM inspection method.
[0002]
[Prior art]
An example of an SRAM memory cell is shown in FIG. The memory cell includes six transistors 101, 102, 103, 104, 105, and 106. Although SRAM can identify a defective bit by electrical characteristic evaluation, since it has a 1-bit 6-transistor configuration, it is difficult to identify a defective portion in 1 bit and evaluate its characteristics. Although it is possible to evaluate the characteristics of a single transistor by performing wiring processing so that the single transistor can be evaluated after completion of the wafer, in reality, in the miniaturization and multilayer wiring processes, more precise processing technology and high aspect ratio In addition to requiring an embedding technique, it is difficult to obtain good characteristics due to the resistance of the material itself used for processing and the influence of the connection resistance. Further, it is possible to specify a defective portion in one bit by emission analysis or the like, but it is not possible to evaluate the characteristics of the defective transistor.
[0003]
[Problems to be solved by the invention]
The present invention has been made under such a background, and an object of the present invention is to enable detailed inspection of elements constituting one bit in the SRAM.
[0004]
[Means for Solving the Problems]
According to the first aspect of the present invention, the SRAM cell structure has a separate system for each of the high voltage side and low voltage side terminals in the first inverter and the high voltage side and low voltage side terminals in the second inverter in each memory cell. Rutotomoni provided wiring, a second wiring connected to the drain portions of the selection transistors, always is electrically disconnected from the second wiring, the second wiring in the evaluation process of the selection transistor A transistor inspection wiring including a first wiring which is electrically connected is provided . Therefore, each element in the two inverters can be inspected independently by using different lines of wiring. In addition, it is possible to individually inspect each selection transistor using the transistor inspection wiring. As a result, all the elements constituting the SRAM can be inspected.
[0007]
In addition , the transistor inspection wiring connected to the drain portions of both the selection transistors is composed of the first wiring and the second wiring, and the first wiring and the second wiring are always electrically cut off. And are electrically connected in the evaluation process of the selection transistor . For this reason , in a normal time other than the evaluation process, the first wiring and the second wiring are isolated wirings and do not affect the original SRAM operation.
[0008]
According to a second aspect of the present invention , in the memory cell in which a defect is found, the first wiring and the second wiring in both the selection transistors are electrically connected to inspect the quality of the selection transistor, and then the inverter Examine the quality of the elements constituting the.
[0009]
In the inspection method according to the third aspect , in particular, when the memory cell is composed of six transistors, the fourth aspect may be employed.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 shows a circuit configuration of a memory cell in the SRAM according to the present embodiment. FIG. 2 shows a plan and sectional structure of the SRAM.
[0011]
In FIG. 1, each cell of the SRAM is composed of six transistors, and includes four N-channel MOSFETs 2, 3, 5, 6 and two P-channel MOSFETs 1, 4.
[0012]
The first inverter INV1 includes a series circuit of a P-channel MOSFET 1 and an N-channel MOSFET 2. The second inverter INV2 is composed of a series circuit of a P-channel MOSFET 4 and an N-channel MOSFET 3. The gate terminals of the P-channel and N-channel MOSFETs 1 and 2 in the first inverter INV1 are connected to a point α between the MOSFETs 4 and 3 in the second inverter INV2. The α point is connected to the drain terminal of an N-channel MOSFET (select transistor) 5 and the source terminal of the MOSFET 5 is connected to the bit line Di. Further, the gate terminal of the N-channel MOSFET (select transistor) 5 is connected to the word line. Similarly, the gate terminals of the P-channel and N-channel MOSFETs 4 and 3 in the second inverter INV2 are connected to the point β between both MOSFETs 1 and 2 in the first inverter INV1. Further, the β point is connected to the drain terminal of the N-channel MOSFET (select transistor) 6, and the source terminal of the MOSFET 6 is connected to the bit line Di + 1. Further, the gate terminal of the N-channel MOSFET (select transistor) 6 is connected to the word line.
[0013]
In this way, two inverters INV1, INV2 are constituted by four transistors 1, 2, 3, 4 out of six transistors 1-6 in a memory cell corresponding to 1 bit, and the remaining 2 The two transistors 5 and 6 are selection transistors whose sources are connected to the bit lines. The outputs of the two inverters INV1 and INV2 are the inputs of the other inverters.
[0014]
The cell structure is constituted by a multilayer wiring structure (two-layer wiring structure) as shown in FIG. A detailed structure will be described with reference to FIGS.
First, as shown in FIG. 3, an n-well region 21 is formed in the surface layer portion of the p-type silicon substrate 20. An n-type diffusion region 22 is formed (patterned) in the surface layer portion of the p-type silicon substrate 20. A p-type diffusion region 23 is formed (patterned) in the surface layer portion of the n-well region 21. As shown in FIG. 4, a polysilicon gate electrode 25 is formed (patterned) via a gate oxide film 24 on the upper surface of the silicon substrate 20 of FIG. 3, and a word line 26 made of polysilicon is extended. In this way, six transistors 1, 2, 3, 4, 5, 6 constituting each cell are formed on the silicon substrate.
[0015]
As shown in FIG. 5, a first-layer aluminum wiring 28 is formed (patterned) on the polysilicon 25 and 26 in FIG. 4 via an interlayer insulating film 27. The aluminum wiring 28 is formed in via holes 29. The n-type diffusion region 22 is electrically connected through the through hole.
[0016]
Further, as shown in FIG. 6, second-layer aluminum wirings 31, 32, 33, and 34 are formed (patterned) on the first-layer aluminum wiring 28 in FIG. The aluminum wirings 31 to 34 are electrically connected to the first-layer aluminum wiring through the via holes 35, 36, 37, and 38. Here, the aluminum wiring 31 is a first power supply wiring (Vdd1 wiring), the aluminum wiring 32 is a first ground wiring (GND1 wiring), and the aluminum wiring 33 is a second power supply wiring (GND1 wiring). Vdd2 wiring), and the aluminum wiring 34 is a second ground wiring (GND2 wiring).
[0017]
Further, as shown in FIG. 2, third-layer aluminum wirings 40, 41, 42, and 43 are formed on the second-layer aluminum wirings 31 to 34 in FIG. The aluminum wirings 42 and 43 are connected to the second-layer aluminum wiring through the via holes 44 and are electrically connected to the drain portions of the selection transistors 5 and 6 through the aluminum wiring, respectively.
[0018]
Here, it compares with the comparative example shown in FIG. In FIG. 7, second-layer aluminum wirings 110 and 111 are formed on the first-layer aluminum wiring 28 in FIG. 5 via an interlayer insulating film 109. This wiring 110 is for GND, and the wiring 111 is Vdd. And is electrically connected to the first-layer aluminum wiring through the via hole 112. In other words, in the conventional layout, as shown in FIG. 8, two inverters in one bit use common Vdd and GND wirings (110, 111), respectively.
[0019]
Compared to this case, in FIG. 6, in addition to the structure used for the SRAM circuit operation, wirings 31, 32, 33, and 34 are arranged for failure analysis. That is, in FIG. 6, as the Vdd wiring and the GND wiring commonly supplied to the inverters INV1 and INV2, the first Vdd wiring 31 and the second Vdd wiring 33, and the first GND wiring 32 and the second wiring, respectively. The wiring structure is such that an arbitrary bias can be supplied independently to the GND wiring 34.
[0020]
explain in detail. For example, whenever the power supply voltage Vdd is supplied to the P-channel transistor 101 in FIG. 8, the power supply voltage Vdd is also supplied to the P-channel transistor 104 and both transistors 101 and 104 operate. Therefore, it is not possible to characterize each of them individually.
[0021]
On the other hand, in this embodiment, as shown in FIG. 6, the power supply voltages Vdd1 and Vdd2 and the ground voltages GND1 and GND2 are obtained by extending the wirings 31, 32, 33, and 34 obliquely with respect to the cell. Each is a separate source. As a result, the power supply voltages Vdd1 and Vdd2 and the ground potentials GND1 and GND2 can be supplied to the inverters INV1 and INV2 through the power supply wirings 31 and 33 and the ground wirings 32 and 34, respectively.
[0022]
As shown in FIG. 2, a via hole 44 in the second layer and a third aluminum layer 43 in the form of dots are provided in the drain portion of the select transistor 5, and a third layer of aluminum is adjacent to the via hole 44. Wiring 41 is arranged. Similarly, a second-layer via hole 44 and a dot-shaped third-layer aluminum wiring 42 are provided in the drain portion of the selection transistor 6, and a third-layer aluminum wiring 40 is disposed adjacent thereto. .
[0023]
Then, after evaluating the electrical characteristics of the SRAM and specifying the defective bit, wiring processing is performed, and the wirings 42 and 43 arranged in the defective bit are connected to the wirings 40 and 41, respectively, as inspection wiring for the defective bit. Use. By using this wiring, the operation of the selection transistors 5 and 6 can be inspected alone. That is, as shown in FIG. 1, the selection transistors 5 and 6 can be individually characterized by using the word line as the gate, the bit line as the source, and the wirings 41 and 40 as the drain.
[0024]
Conventionally, the characteristics of each element constituting the SRAM have been evaluated by performing wiring processing using FIB (focused ion beam), etc. However, in the miniaturization / multilayer wiring process, more precise processing technology and high aspect ratio are required. It is difficult to obtain good characteristics due to the resistance of the material itself used for processing and the influence of its connection resistance. Further, it is possible to specify a defective portion in one bit by emission analysis or the like, but it is not possible to evaluate the characteristics of the defective transistor.
[0025]
On the other hand, by providing the wirings 31 to 34 and 40 to 43 in advance, it is possible to evaluate the characteristics of each element with very simple processing.
Here, the wirings 40 and 41 in FIG. 2 are used only for identifying the defective portion, and are isolated wirings unless they are processed and connected to the wirings 42 and 43, so that the original SRAM is not affected. In addition, since the SRAM can be configured with two-layer wiring, there is no third-layer wiring. Therefore, the wirings 40, 41, 42, and 43 can be formed without increasing the cell area.
[0026]
Next, the method of characteristic evaluation will be described.
First, the characteristics of the selection transistors 5 and 6 are evaluated.
In FIG. 1, the operation of the selection transistors 5 and 6 can be confirmed individually by using the word line as the gate, the bit line as the source, and the wirings 41 and 40 as the drain. Discrimination is possible.
[0027]
Next, if the selection transistors 5 and 6 are not defective, any of the remaining four transistors 1, 2, 3 and 4 is defective. By supplying arbitrary biases Vdd1, Vdd2, GND1, and GND2 to the power supply wirings 31, 33 and the ground wirings 32, 34, it is possible to further narrow down defective transistors. Specifically, by setting the following bias conditions, only a desired transistor can be operated, and a single characteristic evaluation is possible.
(Part 1)
In order to evaluate the N-channel transistor 3 in FIG. 1, the word line is set to L level, the wiring 40 is set to H level, and the second ground wiring 34 (GND2) is set to H level. Then, the α point potential at that time is monitored by the wiring 41.
(Part 2)
In order to evaluate the N-channel transistor 2, the word line is set to L level, the wiring 41 is set to H level, and the first ground wiring 32 (GND1) is set to H level. The β point potential at that time is monitored by the wiring 40.
(Part 3)
In order to evaluate the P-channel transistor 4, the word line is set to L level, the wiring 40 is set to L level, and the second power supply wiring 33 (Vdd2) is set to H level. Then, the α point potential at that time is monitored by the wiring 41.
(Part 4)
In order to evaluate the P-channel transistor 1, the word line is set to L level, the wiring 41 is set to L level, and the first power supply wiring 31 (Vdd1) is set to H level. The β point potential at that time is monitored by the wiring 40.
[0028]
By the above inspection, it is possible to narrow down defective portions of one transistor out of one bit and six transistors.
Thus, this embodiment has the following features.
(A) As shown in FIG. 6, the high-voltage side and low-voltage side terminals (for Vdd1 and GND1) in the first inverter INV1 and the high-voltage side and low-voltage side terminals in the second inverter INV2 ( Separate lines 31, 32, 33, and 34 are provided for each of Vdd 2 and GND 2. Therefore, it becomes possible to inspect each transistor (N-channel transistor, P-channel transistor) in the two inverters INV1 and INV2 by using wirings 31 to 34 of different systems (elements constituting one bit). Detailed inspection is possible). In other words, separate wirings 31 to 34 are provided at the Vdd (for Vdd1 and Vdd2) terminals and the GND (for GND1 and GND2) terminals of the first inverter and the second inverter (conventionally). Vdd1 and Vdd2, GND1 and GND2 are common wiring), and by preparing a circuit that can arbitrarily control the bias that can be applied to each of these wirings 31 to 34, the N-channel transistor and the P-channel transistor that constitute each inverter are provided. This results in a cell structure that can be characterized independently.
(B) As shown in FIG. 2, transistor inspection wirings 40, 41, 42, 43 connected to the drain portions of the selection transistors 5, 6 in each memory cell of the SRAM are provided. Therefore, it becomes possible to individually inspect (characteristic evaluation) the selection transistors 5 and 6 by using the transistor inspection wirings 40, 41, 42, and 43 (it is possible to finely inspect elements constituting one bit). Possible).
(C) High voltage side and low voltage side terminals (for Vdd1, GND1) at the first inverter INV1 and high voltage side and low voltage side terminals (for Vdd2, GND2) at the second inverter INV2 in each memory cell of the SRAM Are provided with different lines of wiring 31, 32, 33, 34, and transistor testing wirings 40, 41, 42, 43 connected to the drains of the selection transistors 5, 6, respectively. Therefore, it is possible to inspect each transistor (N-channel transistor, P-channel transistor) in the two inverters by using separate lines 31 to 34, and also use transistor inspection lines 40 to 44. Thus, the selection transistors 5 and 6 can be individually inspected (characteristic evaluation). As a result, all transistors constituting the SRAM can be inspected (characteristics of all elements are evaluated). That is, the characteristics of all six transistors in one bit can be evaluated, and a defective transistor can be specified.
(D) In FIG. 2, transistor inspection wirings 40, 41, 42, and 43 connected to the drain portions of the selection transistors 5 and 6 are connected to the first wirings 40 and 41 and the second wirings 42 and 43. Therefore, the first wirings 40 and 41 and the second wirings 42 and 43 are always electrically disconnected, and are electrically connected in the evaluation process of the selection transistor. In the discovered memory cell, after the first wirings 40 and 41 and the second wirings 42 and 43 in both the selection transistors 5 and 6 are electrically connected and the quality of the selection transistors 5 and 6 is checked, The transistors 1, 2, 3, and 4 constituting the inverters INV1 and INV2 are checked for quality. In this manner, the first wirings 40 and 41 and the second wirings 42 and 43 are isolated wirings at normal times other than the evaluation process, and the original SRAM operation is not affected.
(E) As an SRAM inspection method, in a memory cell in which a defect is found, transistor inspection wirings 40 and 41 connected to the drain portions of the selection transistors 5 and 6 with the word line as the gate and the bit line as the source, respectively. , 42 and 43 as drains, the first inspection step for confirming the operation of each of the selection transistors 5 and 6 and the case where both the selection transistors 5 and 6 are not defective in the first inspection step In the memory cell, an arbitrary voltage is independently supplied to the wirings 31 and 32 provided in different systems to the high-voltage side and low-voltage side terminals Vdd1 and GND1 in the first inverter INV1, and the high-voltage side in the second inverter INV2 In addition, any voltage is independently supplied to the wirings 33 and 34 provided in different systems for the low-voltage side terminals Vdd2 and GND2, respectively. And a second inspection step for narrowing down elements.
[0029]
In particular, when a memory cell corresponding to 1 bit is configured by six transistors 1, 2, 3, 4, 5, and 6, the second inspection step turns off the selection transistors 5 and 6 through the word line. (For example, the word line is set to L level in order to evaluate the N-channel transistor 3 in FIG. 1), and two inverters are formed through transistor inspection wirings 40, 41, 42, and 43 in one of the selection transistors. Among the transistors, a transistor to be inspected is turned on (for example, the wiring 40 is set to H level in order to evaluate the N-channel transistor 3 in FIG. 1), and the high-voltage side and low-voltage side terminals Vdd1 and GND1 in the inverter. , Vdd2 and GND2 when a desired voltage is applied to wirings 31, 32, 33 and 34 provided in separate systems. 1 is monitored (for example, the second ground wiring 34 (GND2) is connected to H in order to evaluate the N-channel transistor 3 in FIG. 1). The potential of the α point at the time of the level is monitored by the wiring 41), and the inspection target transistor is inspected.
[0030]
In the above description, the memory cell is composed of six transistors, and four inverters are composed of two inverters, and the remaining two transistors are selected transistors. The present invention may be applied to a case where four transistors and two resistors are used, and two inverters and two resistors are used to form two inverters and the remaining two transistors are selected transistors. That is, the present invention may be applied to the case where the transistor indicated by reference numeral 1 in FIG. 1 is replaced with a resistor and the transistor indicated by reference numeral 4 is replaced with a resistor.
[Brief description of the drawings]
FIG. 1 is a diagram showing a circuit configuration of a memory cell in an SRAM according to an embodiment.
FIG. 2 is a diagram showing a configuration of an SRAM.
FIG. 3 is a diagram showing a substrate configuration of an SRAM.
FIG. 4 is a diagram showing SRAM polysilicon wiring.
FIG. 5 is a diagram showing a first layer wiring;
FIG. 6 is a diagram showing a second layer wiring;
FIG. 7 is a diagram showing a wiring state for comparison.
FIG. 8 is a circuit configuration diagram for explaining the prior art.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... P channel MOSFET, 2 ... N channel MOSFET, 3 ... N channel MOSFET, 4 ... P channel MOSFET, 5 ... N channel MOSFET, 6 ... N channel MOSFET, INV1 ... Inverter, INV2 ... Inverter.

Claims (4)

A memory cell corresponding to one bit is composed of six transistors (1, 2, 3, 4, 5, 6), or four transistors and two resistors, and four of them (1, 2, 2, 3, 4) or two transistors and two resistors constitute two inverters (INV1, INV2), and the remaining two transistors (5, 6) are connected to a selection transistor whose source is connected to the bit line. In the SRAM,
The high voltage side and low voltage side terminals (Vdd1, GND1) at the first inverter (INV1) and the high voltage side and low voltage side terminals (Vdd2, GND2) at the second inverter (INV2) in each memory cell Rutotomoni provided wiring systems (31, 32, 33, 34), a second wiring connected to the drain portions of the selection transistors (5, 6) and (42, 43), always the second wiring The first wiring (40, 41) which is electrically disconnected from the second wiring (42, 43) and is electrically connected to the second wiring (42, 43) in the evaluation process of the selection transistor (5, 6). An SRAM cell structure characterized in that transistor inspection wiring (40, 41, 42, 43) comprising: A memory cell corresponding to one bit is composed of six transistors (1, 2, 3, 4, 5, 6), or four transistors and two resistors, and four of them (1, 2, 2, 3, 4) or two transistors and two resistors constitute two inverters (INV1, INV2), and the remaining two transistors (5, 6) are connected to a selection transistor whose source is connected to the bit line. An inspection method for SRAM,
The high-voltage side and low-voltage side terminals (V dd 1 and GND1) of the first inverter (INV1) and the high-voltage side and low-voltage side terminals (V dd 2 and GND2) of the second inverter (INV2) in each memory cell. A separate line (31, 32, 33, 34) is provided for each, and the second lines (42, 43) connected to the drains of the selection transistors (5, 6) are always connected to the first line. The first wiring (40, 43) that is electrically disconnected from the second wiring (42, 43) and is electrically connected to the second wiring (42, 43) in the evaluation process of the selection transistors (5, 6). , 41) are provided for transistor inspection wiring (40, 41, 42, 43),
In the memory cell in which the defect is found, the first wiring (40, 41) and the second wiring (42, 43) in both selection transistors (5, 6) are electrically connected to select transistor (5 , 6), the SRAM is inspected for each element (1, 2, 3, 4) constituting the inverter (INV1, INV2) . A memory cell corresponding to one bit is composed of six transistors (1, 2, 3, 4, 5, 6), or four transistors and two resistors, and four of them (1, 2, 2, 3, 4) or two transistors and two resistors constitute two inverters (INV1, INV2), and the remaining two transistors (5, 6) are connected to a selection transistor whose source is connected to the bit line. An inspection method for SRAM,
The high voltage side and low voltage side terminals (Vdd1, GND1) at the first inverter (INV1) and the high voltage side and low voltage side terminals (Vdd2, GND2) at the second inverter (INV2) in each memory cell The system wiring (31, 32, 33, 34) is provided, and the second wiring (42, 43) connected to the drains of the selection transistors (5, 6), respectively, and the second wiring (always) 42, 43) and the first wiring (40, 41) electrically connected to the second wiring (42, 43) in the evaluation process of the selection transistor (5, 6). transistor inspection wiring (40, 41, 42, 43) provided consisting,
In a memory cell in which a defect is found, transistor inspection wiring (40, 41, 42, 43) connected to the drain portions of both selection transistors (5, 6) using the word line as a gate and the bit line as a source, respectively. A first inspection step for confirming the operation of each of the select transistors (5, 6) independently by using the drain;
When both the selection transistors (5, 6) are not defective in the first inspection step, the high voltage side and low voltage side terminals (V dd 1, GND1) of the first inverter (INV1) in the memory cell. In addition, an arbitrary voltage is independently supplied to the wirings (31, 32) provided in the separate system, and the high voltage side and low voltage side terminals (V dd 2, GND2) of the second inverter (INV2 ) are separately provided in the separate system. A second inspection step of narrowing down defective elements by supplying an arbitrary voltage to each of the provided wirings (33, 34);
A method for inspecting SRAM, comprising : A memory cell corresponding to 1 bit is composed of 6 transistors (1, 2, 3, 4, 5, 6),
  In the second inspection step, the selection transistors (5, 6) are turned off through the word lines, and two inverters are formed through the transistor inspection wirings (40, 41, 42, 43) in one selection transistor. The transistor to be inspected is turned on, and the high-voltage side and low-voltage side terminals (V dd 1, GND1, V dd 2, GND2) Level of transistor inspection wiring (40, 41, 42, 43) at the other selected transistor when a desired voltage is applied to wiring (31, 32, 33, 34) provided in a separate system 4. The SRAM inspection method according to claim 3, wherein the transistor to be inspected is inspected by monitoring the above.

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