JPH08137737A - Dram control system - Google Patents

Abstract

PURPOSE: To eliminate a circuit change accompanied by means of the change of a DRAM type and to provide system constitution which can flexibly correspond to the speed of DRAM. CONSTITUTION: A circuit 2 receiving a data control signal from a processor and generating a DRAM control signal to DRAM 1 and a timing setting register 3 controlling the operation timing of the DRAM control signal which the DRAM control signal generation circuit 2 generates are provided. Timing is controlled so that a setting data value which DRAM 1 requests to the timing setting register 3 is set.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operation control system for a DRAM (dynamic RAM) used in an image data processing device or the like.

[0002]

2. Description of the Related Art A functional block of a conventional DRAM control system is shown in FIG. It is almost impossible for a system controller such as a microprocessor or a data processor to directly connect control signals such as data input / output, which it has, directly to the DRAM 1. Therefore, a control signal generation circuit 2 for generating a DRAM control signal from a control signal generated by a system controller or a data processor (hereinafter abbreviated as a processor) is required between the processor and the DRAM.

The control signal generating circuit 2 inputs an R / W signal and an address signal ADDR which are identification signals of data read / write from the processor, and a clock signal for synchronizing with the operation of the processor, and outputs them. A DRAM control signal for DRAM 1 is generated from the signal.

[0004]

In the prior art as described above, the DRA that influences the data processing speed of the system.
When the type of M is changed, it is necessary to change the control signal itself.

The object of the present invention is the problem of this prior art. It is to eliminate the circuit change associated with the DRAM type change and to improve the system development ability.

[0006]

DISCLOSURE OF THE INVENTION The above-mentioned object is to generate a DRA of a DRAM control signal generating circuit for controlling the operation of a DRAM.
A timing setting register for controlling the operation timing of the M control signal according to the setting data value is provided, and the setting data value of the timing setting register is set to a value corresponding to the DRAM to control the operation timing of the DRAM control signal. It is achieved by

[0007]

According to the above means, by setting the timing information required by the DRAM in the timing setting register, the timing of the DRAM control signal generated from the DRAM control signal generating circuit is controlled by the timing value set in the timing setting register. can do. As a result, the control timing required by the DRAM can be flexibly dealt with by setting the data in the timing setting register.

[0008]

EXAMPLES The present invention will be described below with reference to examples. FIG.
Shows a configuration example of the present invention. The difference from FIG. 3 is that a timing setting register is provided to control the operation timing of the DRAM control signal. That is, it receives a data control signal from a processor (not shown)
It comprises a circuit 2 for generating a control signal and a timing setting register 3 for controlling the operation of a DRAM control signal generated by the generation circuit 2.

The processor uses the timing setting register 3
On the other hand, the DRAM control signal timing required by the DRAM 1 is set. The setting is R / W (read / write identification signal), similar to the data space access of the processor.
The data by the setting data signal is set by the signal and the ADDR (address signal) signal. The information set in the timing setting register 3 is the timing of the operation of the DRAM control signal, and the control signal generation circuit 2
Access to the DRAM 1 is determined by the R / W signal and the ADDR signal, and a DRAM control signal synchronized with the clock signal is generated.

At this time, the operation timing of the DRAM control signal is controlled by the previously set value of the timing setting register 3.

FIG. 3 shows operation waveforms of one embodiment. DR
The AM control signals RAS and CAS are signals indicating the line address setting timing and the column address setting timing, respectively. RAS and CA at the request of DRAM1
Time t ₁ between S, line address A1 hold time t ₂ ,
If the column address A2 setup time is t ₃ and the period T of the clock signal is t ₁ = 2T and t ₂ = t ₃ = T, the timing setting register 3 stores the value corresponding to t _1. "2", so that "1" as a value corresponding to t _2, t ₃ is set.

As described above, the setting of the timing information of the timing setting register 3 is set to a value corresponding to the control timing required by the DRAM, and the DRA is set by this setting.
The control timing required by M can be flexibly dealt with.

[0013]

As described above, according to the present invention, the DRA
Since the control timing required by M can be changed flexibly, it is possible to construct a system that flexibly corresponds to the speed of the DRAM, which has a great influence on data processing such as image data processing.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 shows an operation waveform diagram of one embodiment of the present invention.

FIG. 3 is a conventional configuration diagram.

[Explanation of Codes] 1 ... DRAM, 2 ... Control signal generating circuit, 3 ... Timing setting register.

Claims (1)

[Claims] 1. A device for controlling access to data in a DRAM, comprising: a timing setting register for controlling an operation timing of a DRAM control signal generated by a DRAM control signal generation circuit for controlling an operation of the DRAM by a set data value, and the timing setting. The set data value of the register is set to a value corresponding to the DRAM so as to control the operation timing of the DRAM control signal.
RAM control method.