JPH04134695A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To facilitate a performance discrimination at the time of writing by applying an independent clock not to be used normally to a write pulse generating circuit, and setting the timing of a write pulse optionally. CONSTITUTION:First, at the normal operation, a line 104 (a clock A) is used to fix at a value '0'. At this time, if a write request is the value '1', the value '1' is set in a write request register 4, and the write pulse (a line 115) is generated. And if the write request is the value '0', a line 112 becomes the value '0', so the line 115 turns to the value '0' as well, and a write is suppressed. Next, at a function testing time, a clock B (a line 105) is used. In this case, if the write request (a line 103) is the value '1', a write pulse generating circuit 5 generates the write pulse by the edge of the clock B inputted from a line 114. At this time, if the timing of the clock B to the clock A is set, for example, faster by a DELTAt, the write pulse is shifted by the DELTAt from the normal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory, and particularly to a circuit for measuring performance during writing.

[Conventional technology]

In recent years, as memory speeds have increased, some devices have incorporated registers into memory elements and have attempted to effectively improve performance using a clock synchronization method. For example, as shown in FIG. 4, write data 116 is set in write data register 11 and sent to RAM 12 via line 121. Address 117 is set in address register 13 and sent to RAM 12 on line 122. A write request 118 is set in the write request register 14 and connected to line 1.
23 to the write pulse generation circuit 15. Clock 119 clocks write data register 11. Address register 13. The write request register 14 is set. It is also sent to the write pulse generation circuit 15, and the write pulse generation circuit 15 generates a write pulse at a predetermined timing according to the edge of the clock 119 and the write request (line 123), and outputs it from the line 124 to the RAM 2. Send.

RAM2 uses line 121 for the address indicated by line 122.
Write the data indicated by . Further, the read data is sent out from line 120.

In such a conventional semiconductor memory, addresses and data are set by a clock 119, and a write pulse is generated internally.

[Problem to be solved by the invention]

Such a conventional semiconductor memory has a built-in write pulse generation circuit 15, and a write pulse is generated at a fixed timing by a clock 119, making it difficult to measure performance during writing.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory that solves the above problems and allows easy performance measurement during writing.

[Means to solve the problem]

The structure of the semiconductor memory of the present invention includes: an address register that includes first and second clock inputs and sets an address using the first clock; a write request register that sets a write request using the first clock; the pressure of the write request register and the first or second
a write pulse generation circuit that generates a write pulse from the leading edge of the clock of
and means for controlling the use of the second clock.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a semiconductor memory according to an embodiment of the present invention.

In FIG. 1, in this embodiment, the first clock 104
(referred to as clock A) passes through the distribution circuit 6 to the write data registers 1. Address register 3. Write request register 4. and write pulse generating circuit 5, respectively, on line 107. Line 108, line 109. and connected through line 113. Write data 101 is written on line 10
It is set in the write data register 1 by the clock A supplied from 7. The set write data is
Random access memory (RAM) 2 from line 110
will be sent to. Address 103 is set in address register 3 by clock A supplied from line 108. The set address is transferred to the RAM by line 111.
2 is sent out. Write request 103 is set in write request register 4 by clock A supplied from line 109. The set write request is set in the write pulse generation circuit 5 via line 112. A second clock 105 (referred to as clock B) passes through the delay circuit 7 and is supplied to the write pulse generation circuit 5 from a line 114. The write pulse generation circuit 5 receives a write request from a line 112.

generating a write pulse from clock A provided on line 113 and clock B provided on line 114;
It is sent to RAM2 from line 115. RAM2 is
A write pulse from line 115 writes the write data provided from line 110 to the address provided from line 111. If there is no write pulse from line 115, data at the specified address is output from line 106.

FIG. 2 is a block diagram showing the write pulse generation circuit 5 in FIG. 1 in detail. In FIG. 2, line 113 (
Clock A) and line 114 (clock B) are connected to gate circuit 8. Gate circuit 8 logically ORs line 113 and line 114, and one of the outputs is sent to delay circuit 10 from line 117. The delay circuit 10 delays the input on the line 117 by a certain period of time and sends it out on the line 118. Another output line 116 of gate circuit 8 is connected to gate circuit 9. Gate circuit 9 is connected to line 118 . Output linework 18 of delay circuit 10. and write request signal line 112, and outputs a write pulse from line 115 to RAM2.

The operation of one embodiment of the present invention will be described with the above configuration. Here, data is set in each register 1, 3, 4 at the falling edge.

First, during normal operation, line 106 (clock B
) is used by fixing it to the value “0”. The operation at this time is shown in FIG. 3(A). Write request (line 103) has value “1”
If so, the value "1" is set in the write request register 4 and a write pulse (line 115) is generated. This timing is fixed, and performance during writing cannot be measured. Also, if the write request has the value “O”, line 1
Since the line 12 has a value of "0", the line 115 also has a value of "O", and writing is inhibited.

Next, the time of functional test will be explained. At this time, clock B (line 105) is used as shown in FIG. 3(B).

In this case, if the write request (line 103) has a value of "1", the write pulse generating circuit 5 generates a write pulse based on the edge of the clock B input from the line 114. Other operations are the same as during normal operation. Since clock A and clock B can be set independently, if the timing of clock B is set earlier than clock A by, for example, Δt, the write pulse is shifted by Δt compared to normal.

〔Effect of the invention〕

As explained above, the present invention provides an independent clock that is not normally used for the write pulse generation circuit in a memory that includes an address register, a write request register, and a write pulse generation circuit, thereby generating a write pulse. Since the timing can be set arbitrarily, the writing performance can be easily improved.

For example, in FIG. 3(A), the timing of the write system is fixed, but as shown in FIG. 3(B), if the clock B is shifted by Δt, the write pulse is also shifted by Δt. The timing setting range is expanded, and the performance of the write system (jSA in FIG. 3(B)) can be measured.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a semiconductor memory according to an embodiment of the present invention, FIG. 2 is a block diagram showing the contents of the write pulse generation circuit shown in FIG. 1, and FIGS. ) are timing diagrams showing the operation of one embodiment of the present invention.
The figure is a block diagram showing a conventional semiconductor memory. 1.11...Data register, 2.12...RAM
13.13...Address register, 4.14...Register, 5.15...Write pulse generation circuit, 6...
- Distribution circuit, 7, 10... delay circuit, 8, 9... gate.

Claims (1)

[Claims] an address register having first and second clock inputs and having an address set by the first clock;
A write request register that sets a write request based on the first clock, and a write pulse generation circuit that generates a write pulse from the output of the write request register and the leading edge of the first or second clock, and is normally used. 1. A semiconductor memory comprising means for controlling such that only the first clock is used at times, and the first and second clocks are used during a functional test.