JPH08136586A - Waveform display system - Google Patents

Abstract

PURPOSE: To obtain a waveform display system which can locate a trigger point and observe a waveform before being triggered in real time by a method wherein an interrupt handling operation is performed whenever one data is converted and whether a trigger has been generated or not is judged. CONSTITUTION: In every data sample, a clock signal for an A/D converter 3 is supplied as an interrupt-handling seizing signal for a microcomputer 5. In addition, a trigger generation signal is generated from a measuring signal, and the signal is latched by a latch 4 so as to be supplied to the microcomputer 5. By the interrupt handling operation of the microcomputer 5, the generation of a trigger can be recognized, a waveform which is displayed is shifted one data by one data toward the left end of a tube face in every data sample, and new data is displayed at the right end of the tube face. In addition, when a waveform is to be updated, whether a trigger has been generated or not is judged. When the trigger has been generated, the time since the generation of the trigger with reference to the displayed waveform is displayed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform display system in a digital oscilloscope.

[0002]

2. Description of the Related Art In a low-speed range (for example, 1 s / div) of a digital oscilloscope, when displaying a waveform of 10 div, for sampling data necessary for display,
Hang for 10 seconds. At this time, all the data necessary for display,
If the waveform is displayed after sampling, the change in the waveform cannot be observed in real time.
Therefore, conventionally, every time one data is sampled, the displayed waveform is shifted toward the left end of the pipe surface by one data, and new data is displayed at the right end of the pipe surface. The scrolling method is used to display the flow from the right end to the left end, and the display is not updated until the trigger occurs.At the time the trigger occurs, all the data before the trigger is updated at once, As for data, there is a triggered roll system in which display data at corresponding positions are sequentially updated one by one.

[0003]

The above-mentioned scrolling method of the prior art has the drawback that there is no trigger point for the measured waveform because the tube surface is used like the paper of a pen recorder. In the triggered roll method, the trigger point is
However, there is a drawback that the signal before the trigger is generated cannot be measured in real time.

It is an object of the present invention to eliminate these drawbacks and to realize a waveform display system in which a trigger point exists and a signal before the trigger is generated can be measured in real time.

[0005]

In order to achieve the above object, the present invention uses the clock signal of the AD converter as the interrupt processing start signal of the microprocessor so that the microprocessor performs data processing for each data sample. As a trigger generation signal from the measurement signal,
By latching this signal and supplying it to the microprocessor, the occurrence of a trigger can be recognized in the interrupt processing of the microprocessor, and
For each data sample, the displayed waveform is divided by one data toward the left end of the tube surface, and new data is displayed at the right end of the tube surface. Further, when the waveform is updated, it is determined whether or not a trigger is generated, and when the trigger is generated, the time from the trigger generation for the displayed waveform is displayed.

[0006]

As a result, the waveform displayed on the screen appears to flow from the right end to the left end, and after the trigger occurs, the time from the displayed waveform to the trigger occurrence can be observed. it can.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. In FIG. 1, the output of the first amplifier 1 is
Is connected to the input of the AD converter 3 via the amplifier 2. It is also connected to the set (s) input of the flip-flop 7 via the comparator 6. The output of the AD converter 3 is output to the microprocessor 5 via the latch 4.
Connected to the data bus. The output of the flip-flop 7 is passed through the buffer 12 to the microprocessor 5
Connected to the data bus. Microprocessor 5
The data bus of is connected to the clock generation circuit 8, the sampling counter 10, the latch 13, the buffer memory 14, and the display memory 15. The output of the latch 13 is AN
Input of D gate 17, reset (R) of flip-flop 7, reset of sampling counter 10 (RES
ET).

The output of the AND gate 17 is connected to the stop (STOP) of the clock generation circuit 8. The output (OUT) of the clock generation circuit 8 is supplied to the clock (CL) of the sampling counter 10 via the AND gate 9.
K). The output of the clock generation circuit 8 is connected to the clock (CLK) of the AD converter 3 via the AND gate 11. The output (OUT) of the sampling counter 10 is connected to the clock (CLK) of the AD converter 3 and the interrupt request (INT) of the microprocessor 5 via the AND gate 11. The output (OUT) of the sampling counter 10 is A
It is connected to the stop (STOP) of the clock generation circuit 8 via the ND gate 17. The output of the display memory 15 is connected to the display 16.

This operation will be described below. The clock generation circuit 8 is set by the microprocessor 5,
According to the conditions, while stop (STOP) is "H", O
Clock pulses are generated from the UT output. The sampling counter 10 stops counting while RESET is “H”, and sets the OUT output to “H”. When RESET is "L", counting is started and the microprocessor 5
To the set value, the CLK input is counted, and when the set value is reached, the OUT output is set to "L". The microprocessor 5 sets STOP of the clock generation circuit 8 to “L” via the latch 13 and the AND gate 16,
Stop clock pulse. In this state, the microprocessor 5 sets the clock generation condition in the clock generation circuit 8 via the data bus. Next, the microprocessor 5 sets the input R of the flip-rop 7 to "H" and the output Q to "L" via the latch 13. Also,
Via the latch 13, the RE of the sampling counter 10
Set SET to "H". The microprocessor 5 sets the sampling data number in the sampling counter 10.
The microprocessor 5 sets each signal to “L” in the order of RESET of the sampling counter 10, STOP of the clock generation circuit 8 and input R of the flip-flop 7, and starts sampling of the input signal. The input signal is amplified by the first amplifier 1 to have a constant amplitude (for example, 1VP-P), becomes a constant voltage level (for example, 0 to -2V) at the second amplifier 2, and the clock signal is generated by the AD converter 3 in the clock generation circuit. It is converted into a digital value (0 to 255) by the clock signal from 8.
The digital value converted by the AD converter 3 is a clock signal and is held in the latch 4. Further, the clock signal generates an interrupt request to the microprocessor 5, and the microprocessor 5 transfers the digital value held in the latch 4 to the buffer memory 14 for each interrupt request, and simultaneously causes the buffer 12 to operate. The output Q of the flip-flop 7 is read in through.

The input signal amplified by the first amplifier 1 to a constant amplitude is judged by the comparator 6 to be a set voltage level, and when the voltage is higher than the set level, a pulse is generated as a trigger signal. The trigger signal generated by the comparator 6 is input S when the input R of the flip-flop 7 is "L".
It is switched by the AND gate 18 so as to be input to the flip-flop 7 and stored in the flip-flop 7. The output Q of the flip-flop 7 becomes "H" when the input R is "L" and the trigger signal is generated, and the clock pulse of the clock generation circuit 8 is supplied to the CLK of the sampling counter 10 through the AND gate 9. Sampling counter 10
Start counting. Sampling counter 10
When the clock pulse is counted up to the set value, the OUT output is set to “L”, the AD converter 3 and the clock generation circuit 8 are stopped through the AND gate 11 and the AND gate 17, and Ends sampling. The microprocessor 5 generates an interrupt request each time
When the output Q of the flip-flop 7 is read and the output Q is "L", the trigger signal is not generated, and when the output Q is "H", it is determined that the trigger signal is generated, and the digital signal held by the latch 4 is held. Handle the display of values. FIG. 2 shows the processing contents of the microprocessor 5. Microprocessor 5
Reads the output Q of the flip-flop 7 by interrupt processing every time an interrupt request is generated, recognizes whether or not a trigger signal is generated, sets a trigger flag and a trigger counter on the software work, and buffers the AD-converted digital data. Save to memory. In the main processing, the interrupt processing transfers the digital data stored in the buffer memory to the display memory so that the latest data is displayed at the right end of the display. Further, when the trigger flag is judged and the trigger signal is generated, the time from the trigger generation to the center of the display is calculated based on the value of the trigger counter and displayed as the delay time on the display. The main processing continues until the sampling is completed. Further, since the latest data of the input signal is displayed on the right end on the display, it seems that the input signal is scrolling in the horizontal direction from the right end to the left end.

[0011]

According to the present invention, the measurement signal before the trigger signal is generated can be measured in real time in the low speed range of the digital oscilloscope, and the time from the generation of the trigger signal to the measurement signal can be recognized.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of the present invention.

FIG. 2 is a processing flow chart of the microprocessor according to the embodiment of the present invention.

[Explanation of symbols]

 1 1st amplifier 2 2nd amplifier 3 AD converter 4 Latch 5 Microprocessor 6 Comparator 7 RS flip-flop 8 Clock generation circuit 10 Sampling counter 12 Tri-state buffer 13 Latch 14 Buffer memory 15 Display memory 16 Indicator

Claims (3)

[Claims] 1. An AD converter for converting an analog input signal into a digital value, a processor for processing the digital value, and a display circuit capable of displaying the digital value processed by the processor and an arbitrary character. In a device having a trigger generation circuit for generating a trigger signal pulse from an analog input signal and an arbitrarily set voltage, a circuit for generating a pulse signal as an interrupt signal to the processor for each data conversion and the trigger signal are generated. A waveform display method characterized in that it has a circuit for the processor to recognize. 2. The waveform display method according to claim 1, wherein the occurrence of a trigger signal is determined by interrupt processing of the processor for each data conversion, and the data is displayed on the screen surface every data conversion until a trigger is generated. The displayed waveform is divided by 1 data to the left end from the set trigger display position, new data is displayed at the trigger display position, and after the trigger is generated,
A waveform display method characterized in that the waveform displayed on the tube surface is updated for each data conversion from the trigger display position toward the right end. 3. The waveform display method according to claim 1, wherein each time data is converted, the waveform data displayed on the tube surface is divided by 1 data toward the left end of the tube surface, and new data is displayed at the right end. The waveform display method is characterized in that the state of the trigger signal is judged for each data conversion, and when the trigger signal occurs, the time from the trigger signal to the displayed waveform is displayed on the screen.