JPH01269067A - Envelope measuring instrument - Google Patents

Envelope measuring instrument

Info

Publication number
JPH01269067A
JPH01269067A JP9901388A JP9901388A JPH01269067A JP H01269067 A JPH01269067 A JP H01269067A JP 9901388 A JP9901388 A JP 9901388A JP 9901388 A JP9901388 A JP 9901388A JP H01269067 A JPH01269067 A JP H01269067A
Authority
JP
Japan
Prior art keywords
output
converter
frequency
sampling clock
values
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9901388A
Other languages
Japanese (ja)
Inventor
Hiromi Ozawa
小澤 広美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp filed Critical Advantest Corp
Priority to JP9901388A priority Critical patent/JPH01269067A/en
Publication of JPH01269067A publication Critical patent/JPH01269067A/en
Pending legal-status Critical Current

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  • Measurement Of Current Or Voltage (AREA)

Abstract

PURPOSE:To detect peak values with high accuracy by converting input waveforms into digital values at every sampling clock and detecting the maximum and minimum values at every frequency-dividing output of a frequency divider, and then, reading out and displaying the storing content of a memory. CONSTITUTION:Input waveforms from an input terminal 11 are converted into digital values by means of an A/D converter 13 at every sampling clock. The sampling clock is divided to 1/n by means of a frequency divider 14 and the maximum and minimum values of the output of the converter 13 are respectively detected by a maximum and minimum value detectors 15 and 16 at every frequency-dividing output. Moreover, the frequency-dividing output is sent to a write control circuit 25 and detect values of the detectors 15 and 16 are stored in a memory 26 at every frequency-dividing output. Then a CPU 27 reads out the content of the memory 26 and causes a display 28 to display envelope. Therefore, peak value can be detected with high accuracy.

Description

【発明の詳細な説明】 「産業上の利用分野」 この発明は波形のエンベロープを測定するエンベロープ
測定器に関する。
DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to an envelope measuring device for measuring the envelope of a waveform.

「従来の技術」 従来のエンベロープ測定器はアナログ技術で入力波形の
最大ピーク、最小ピークを検出してエンベロープ波形を
得ていた。しかしアナログ技術でピーク値を高い精度で
検出することは困難であり、このため忠実にエンベロー
プを得ることができなかった。
``Conventional technology'' Conventional envelope measuring instruments use analog technology to detect the maximum and minimum peaks of an input waveform to obtain an envelope waveform. However, it is difficult to detect peak values with high precision using analog technology, and therefore it has not been possible to faithfully obtain the envelope.

「課題を解決するための手段」 この発明によれば入力波形はサンプリングクロックごと
にAD変換器によりデジタル値に変換され、上記サンプ
リングクロックは分周器で0分の1に分周され、その分
周出力ごとにAD変換器の出力の最大値が最大値検出器
で検出され、最小値が最小値検出器で検出される。更に
上記分周出力ごとに最大値検出器の検出値及び最小値検
出器の検出値がメモリに記憶され、そのメモリの内容が
読み出されて表示器に表示される。
"Means for Solving the Problem" According to the present invention, an input waveform is converted into a digital value by an AD converter for each sampling clock, and the sampling clock is divided into 1/0 by a frequency divider. A maximum value detector detects the maximum value of the output of the AD converter for each frequency output, and a minimum value detector detects the minimum value. Furthermore, the detection value of the maximum value detector and the detection value of the minimum value detector are stored in a memory for each frequency-divided output, and the contents of the memory are read out and displayed on the display.

「実施例」 第1図はこの発明の実施例を示す。入力端子11よりの
入力波形はサンプリングクロック発生器12からのサン
プリングクロックごとにAD変換器13でデジタル値に
変換される。サンプリングクロックは分周器14で0分
の1に分周される。分周器14の分周出力ごとにAD変
換器13の出力の最大値が最大値検出器15で、最小値
が最小値検出器16でそれぞれ一検出される。
"Embodiment" FIG. 1 shows an embodiment of the present invention. The input waveform from the input terminal 11 is converted into a digital value by the AD converter 13 every sampling clock from the sampling clock generator 12. The sampling clock is frequency-divided by a frequency divider 14 to 1/0. For each divided output of the frequency divider 14, the maximum value of the output of the AD converter 13 is detected by the maximum value detector 15, and the minimum value is detected by the minimum value detector 16.

つまり分周器14の分周出力はオア回路17゜18をそ
れぞれ通じてラッチ19.20へそれぞれラッチ指令と
して入力され、ラッチ19,20にAD変換器13の変
換出力値がそれぞれ一時記憶される。ラッチ19.20
の各出力はコンパレータ21,22の各B端子へそれぞ
れ供給され、コンパレータ21,22の各A端子にAD
変換器13の出力が供給される。コンパレータ21では
そのA端子の入力がB端子の入力より大きいと出力は高
レベルとなり、この出力がアンド回路23へ供給され、
アンド回路23へはサンプリングクロックが供給され、
アンド回路23の出力はオア回路17へ供給される。従
ってサンプリングクロックごとにAD変換器13の出力
とラッチ19の出力とが比較され、AD変換器13の出
力の方が大きいとそのAD変換器13の出力がラッチ1
9に一時記憶され、このためラッチ19には分周器14
の分周出力が発生してからnサンプリングクロックの間
におけるAD変換器13の最大値が記憶されることにな
り、つまり最大値が検出される。
In other words, the frequency divided output of the frequency divider 14 is input as a latch command to the latches 19 and 20 through the OR circuits 17 and 18, respectively, and the converted output values of the AD converter 13 are temporarily stored in the latches 19 and 20, respectively. . latch 19.20
Each output is supplied to each B terminal of comparators 21 and 22, and each output is supplied to each A terminal of comparators 21 and 22.
The output of converter 13 is supplied. In the comparator 21, when the input at the A terminal is larger than the input at the B terminal, the output becomes a high level, and this output is supplied to the AND circuit 23.
A sampling clock is supplied to the AND circuit 23,
The output of the AND circuit 23 is supplied to the OR circuit 17. Therefore, the output of the AD converter 13 and the output of the latch 19 are compared for each sampling clock, and if the output of the AD converter 13 is larger, the output of the AD converter 13 is
Therefore, the latch 19 is temporarily stored in the frequency divider 14.
The maximum value of the AD converter 13 during n sampling clocks after generation of the divided output of is stored, that is, the maximum value is detected.

同様にコンパレータ22ではその入端子の入力がB端子
の入力より小さいと出力が高レベルとなり、この出力が
アンド回路24へ供給され、アンド回路24へはサンプ
リングクロックが供給され、アンド回路24の出力はオ
ア回路18へ供給され全。従ってサンプリングクロック
ごとにAD変換器13の出力とラッテ20の出力とが比
較され、AD変換器13の出力の方が小さいとそのAD
変換器13の出力がラッチ20に一時記憶され、このた
めラッテ20には分周器14の分周出力が発生してから
nサンプリングクロックの間におけるAD変換器1′3
の最小値が記憶されることになり、つまり最小値が検出
される。
Similarly, in the comparator 22, when the input of its input terminal is smaller than the input of the B terminal, the output becomes high level, this output is supplied to the AND circuit 24, the sampling clock is supplied to the AND circuit 24, and the output of the AND circuit 24 is is supplied to the OR circuit 18. Therefore, the output of the AD converter 13 and the output of the ratte 20 are compared for each sampling clock, and if the output of the AD converter 13 is smaller, the AD
The output of the converter 13 is temporarily stored in the latch 20, so that the output of the AD converter 1'3 is stored in the latch 20 during n sampling clocks after the frequency divided output of the frequency divider 14 is generated.
The minimum value of will be stored, that is, the minimum value will be detected.

分周器14の分周出力は書き込み制御回路25へ供給さ
れ、書き込み制御回路25により制御されて分周器14
の分周出力ごとに最大値検出器15の検出値、つまりラ
ッテ19の出力と最小値検出器16の検出値、つまりラ
ッテ20の出力とがメエンペローブが表示される。例え
ば第2図Aに示す人力波形に対し、そのエンベロープが
第2図Bに示すように表示されることになる。。
The frequency divided output of the frequency divider 14 is supplied to the write control circuit 25, which controls the frequency divider 14.
The detected value of the maximum value detector 15, that is, the output of the latte 19, and the detected value of the minimum value detector 16, that is, the output of the latte 20, are displayed in a memperobe for each frequency-divided output. For example, for the human input waveform shown in FIG. 2A, its envelope will be displayed as shown in FIG. 2B. .

第3図に示すように最大値検出器15、最小値検出器1
6の出力とAD変換器13の出力とを切替えてメモリ2
6へ記憶するようにして、入力波形を表示器28に表示
できるようにしてもよい。
As shown in FIG. 3, a maximum value detector 15 and a minimum value detector 1
6 and the output of the AD converter 13.
6, so that the input waveform can be displayed on the display 28.

「発明の効果」 以上述べたようにこの発明によれば入力波形のエンベロ
ープを検出することができる。その検出はデジタル技術
で行っているため高い精度でピーク値を検出できるため
忠実なエンベロープが得られる。
"Effects of the Invention" As described above, according to the present invention, the envelope of an input waveform can be detected. Since the detection is performed using digital technology, the peak value can be detected with high precision, resulting in a faithful envelope.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明によるエンベロープ測定器ノー例を示
すブロック図、第2図はその動作の説明に供する波形図
、第3図はこの発明の他の実施例を示すブロック図であ
る。
FIG. 1 is a block diagram showing an example of an envelope measuring device according to the present invention, FIG. 2 is a waveform diagram for explaining its operation, and FIG. 3 is a block diagram showing another embodiment of the present invention.

Claims (1)

【特許請求の範囲】[Claims] (1)入力波形をサンプリングクロックごとにデジタル
値に変換するAD変換器と、 上記サンプリングクロックをn分の1に分周する分周器
と、 その分周器の分周出力ごとに上記AD変換器の出力の最
大値を検出する最大値検出器と、上記分周出力ごとに上
記AD変換器の出力の最小値を検出する最小値検出器と
、 上記分周出力ごとに上記最大値検出器の検出値及び上記
最小値検出器の検出値を記憶するメモリと、 そのメモリの内容を読み出して表示する表示器とを具備
するエンベロープ測定器。
(1) An AD converter that converts the input waveform into a digital value for each sampling clock, a frequency divider that divides the sampling clock into 1/n, and the AD converter for each divided output of the frequency divider. a maximum value detector that detects the maximum value of the output of the AD converter, a minimum value detector that detects the minimum value of the output of the AD converter for each of the frequency division outputs, and a maximum value detector for each of the frequency division outputs. An envelope measuring instrument comprising: a memory for storing the detected value of the detection value and the detection value of the minimum value detector; and a display device for reading and displaying the contents of the memory.
JP9901388A 1988-04-20 1988-04-20 Envelope measuring instrument Pending JPH01269067A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9901388A JPH01269067A (en) 1988-04-20 1988-04-20 Envelope measuring instrument

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9901388A JPH01269067A (en) 1988-04-20 1988-04-20 Envelope measuring instrument

Publications (1)

Publication Number Publication Date
JPH01269067A true JPH01269067A (en) 1989-10-26

Family

ID=14235237

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9901388A Pending JPH01269067A (en) 1988-04-20 1988-04-20 Envelope measuring instrument

Country Status (1)

Country Link
JP (1) JPH01269067A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08160081A (en) * 1994-12-02 1996-06-21 J R C Tokki Kk Digital peak value hold circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54126442A (en) * 1978-03-07 1979-10-01 Hughes Aircraft Co Method of and device for sampling data
JPS61200476A (en) * 1985-02-28 1986-09-05 Kinki Keisokki Kk High speed developing and automatic recording apparatus therefor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54126442A (en) * 1978-03-07 1979-10-01 Hughes Aircraft Co Method of and device for sampling data
JPS61200476A (en) * 1985-02-28 1986-09-05 Kinki Keisokki Kk High speed developing and automatic recording apparatus therefor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08160081A (en) * 1994-12-02 1996-06-21 J R C Tokki Kk Digital peak value hold circuit

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