JPH01269067A - Envelope measuring instrument - Google Patents
Envelope measuring instrumentInfo
- Publication number
- JPH01269067A JPH01269067A JP9901388A JP9901388A JPH01269067A JP H01269067 A JPH01269067 A JP H01269067A JP 9901388 A JP9901388 A JP 9901388A JP 9901388 A JP9901388 A JP 9901388A JP H01269067 A JPH01269067 A JP H01269067A
- Authority
- JP
- Japan
- Prior art keywords
- output
- converter
- frequency
- sampling clock
- values
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005070 sampling Methods 0.000 claims abstract description 16
- 238000001514 detection method Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 3
- 235000015115 caffè latte Nutrition 0.000 description 2
- 241000700159 Rattus Species 0.000 description 1
Landscapes
- Measurement Of Current Or Voltage (AREA)
Abstract
Description
【発明の詳細な説明】
「産業上の利用分野」
この発明は波形のエンベロープを測定するエンベロープ
測定器に関する。DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to an envelope measuring device for measuring the envelope of a waveform.
「従来の技術」
従来のエンベロープ測定器はアナログ技術で入力波形の
最大ピーク、最小ピークを検出してエンベロープ波形を
得ていた。しかしアナログ技術でピーク値を高い精度で
検出することは困難であり、このため忠実にエンベロー
プを得ることができなかった。``Conventional technology'' Conventional envelope measuring instruments use analog technology to detect the maximum and minimum peaks of an input waveform to obtain an envelope waveform. However, it is difficult to detect peak values with high precision using analog technology, and therefore it has not been possible to faithfully obtain the envelope.
「課題を解決するための手段」
この発明によれば入力波形はサンプリングクロックごと
にＡＤ変換器によりデジタル値に変換され、上記サンプ
リングクロックは分周器で０分の１に分周され、その分
周出力ごとにＡＤ変換器の出力の最大値が最大値検出器
で検出され、最小値が最小値検出器で検出される。更に
上記分周出力ごとに最大値検出器の検出値及び最小値検
出器の検出値がメモリに記憶され、そのメモリの内容が
読み出されて表示器に表示される。"Means for Solving the Problem" According to the present invention, an input waveform is converted into a digital value by an AD converter for each sampling clock, and the sampling clock is divided into 1/0 by a frequency divider. A maximum value detector detects the maximum value of the output of the AD converter for each frequency output, and a minimum value detector detects the minimum value. Furthermore, the detection value of the maximum value detector and the detection value of the minimum value detector are stored in a memory for each frequency-divided output, and the contents of the memory are read out and displayed on the display.
「実施例」
第１図はこの発明の実施例を示す。入力端子１１よりの
入力波形はサンプリングクロック発生器１２からのサン
プリングクロックごとにＡＤ変換器１３でデジタル値に
変換される。サンプリングクロックは分周器１４で０分
の１に分周される。分周器１４の分周出力ごとにＡＤ変
換器１３の出力の最大値が最大値検出器１５で、最小値
が最小値検出器１６でそれぞれ一検出される。"Embodiment" FIG. 1 shows an embodiment of the present invention. The input waveform from the input terminal 11 is converted into a digital value by the AD converter 13 every sampling clock from the sampling clock generator 12. The sampling clock is frequency-divided by a frequency divider 14 to 1/0. For each divided output of the frequency divider 14, the maximum value of the output of the AD converter 13 is detected by the maximum value detector 15, and the minimum value is detected by the minimum value detector 16.
つまり分周器１４の分周出力はオア回路１７゜１８をそ
れぞれ通じてラッチ１９．２０へそれぞれラッチ指令と
して入力され、ラッチ１９，２０にＡＤ変換器１３の変
換出力値がそれぞれ一時記憶される。ラッチ１９．２０
の各出力はコンパレータ２１，２２の各Ｂ端子へそれぞ
れ供給され、コンパレータ２１，２２の各Ａ端子にＡＤ
変換器１３の出力が供給される。コンパレータ２１では
そのＡ端子の入力がＢ端子の入力より大きいと出力は高
レベルとなり、この出力がアンド回路２３へ供給され、
アンド回路２３へはサンプリングクロックが供給され、
アンド回路２３の出力はオア回路１７へ供給される。従
ってサンプリングクロックごとにＡＤ変換器１３の出力
とラッチ１９の出力とが比較され、ＡＤ変換器１３の出
力の方が大きいとそのＡＤ変換器１３の出力がラッチ１
９に一時記憶され、このためラッチ１９には分周器１４
の分周出力が発生してからｎサンプリングクロックの間
におけるＡＤ変換器１３の最大値が記憶されることにな
り、つまり最大値が検出される。In other words, the frequency divided output of the frequency divider 14 is input as a latch command to the latches 19 and 20 through the OR circuits 17 and 18, respectively, and the converted output values of the AD converter 13 are temporarily stored in the latches 19 and 20, respectively. . latch 19.20
Each output is supplied to each B terminal of comparators 21 and 22, and each output is supplied to each A terminal of comparators 21 and 22.
The output of converter 13 is supplied. In the comparator 21, when the input at the A terminal is larger than the input at the B terminal, the output becomes a high level, and this output is supplied to the AND circuit 23.
A sampling clock is supplied to the AND circuit 23,
The output of the AND circuit 23 is supplied to the OR circuit 17. Therefore, the output of the AD converter 13 and the output of the latch 19 are compared for each sampling clock, and if the output of the AD converter 13 is larger, the output of the AD converter 13 is
Therefore, the latch 19 is temporarily stored in the frequency divider 14.
The maximum value of the AD converter 13 during n sampling clocks after generation of the divided output of is stored, that is, the maximum value is detected.
同様にコンパレータ２２ではその入端子の入力がＢ端子
の入力より小さいと出力が高レベルとなり、この出力が
アンド回路２４へ供給され、アンド回路２４へはサンプ
リングクロックが供給され、アンド回路２４の出力はオ
ア回路１８へ供給され全。従ってサンプリングクロック
ごとにＡＤ変換器１３の出力とラッテ２０の出力とが比
較され、ＡＤ変換器１３の出力の方が小さいとそのＡＤ
変換器１３の出力がラッチ２０に一時記憶され、このた
めラッテ２０には分周器１４の分周出力が発生してから
ｎサンプリングクロックの間におけるＡＤ変換器１′３
の最小値が記憶されることになり、つまり最小値が検出
される。Similarly, in the comparator 22, when the input of its input terminal is smaller than the input of the B terminal, the output becomes high level, this output is supplied to the AND circuit 24, the sampling clock is supplied to the AND circuit 24, and the output of the AND circuit 24 is is supplied to the OR circuit 18. Therefore, the output of the AD converter 13 and the output of the ratte 20 are compared for each sampling clock, and if the output of the AD converter 13 is smaller, the AD
The output of the converter 13 is temporarily stored in the latch 20, so that the output of the AD converter 1'3 is stored in the latch 20 during n sampling clocks after the frequency divided output of the frequency divider 14 is generated.
The minimum value of will be stored, that is, the minimum value will be detected.
分周器１４の分周出力は書き込み制御回路２５へ供給さ
れ、書き込み制御回路２５により制御されて分周器１４
の分周出力ごとに最大値検出器１５の検出値、つまりラ
ッテ１９の出力と最小値検出器１６の検出値、つまりラ
ッテ２０の出力とがメエンペローブが表示される。例え
ば第２図Ａに示す人力波形に対し、そのエンベロープが
第２図Ｂに示すように表示されることになる。。The frequency divided output of the frequency divider 14 is supplied to the write control circuit 25, which controls the frequency divider 14.
The detected value of the maximum value detector 15, that is, the output of the latte 19, and the detected value of the minimum value detector 16, that is, the output of the latte 20, are displayed in a memperobe for each frequency-divided output. For example, for the human input waveform shown in FIG. 2A, its envelope will be displayed as shown in FIG. 2B. .
第３図に示すように最大値検出器１５、最小値検出器１
６の出力とＡＤ変換器１３の出力とを切替えてメモリ２
６へ記憶するようにして、入力波形を表示器２８に表示
できるようにしてもよい。As shown in FIG. 3, a maximum value detector 15 and a minimum value detector 1
6 and the output of the AD converter 13.
6, so that the input waveform can be displayed on the display 28.
「発明の効果」
以上述べたようにこの発明によれば入力波形のエンベロ
ープを検出することができる。その検出はデジタル技術
で行っているため高い精度でピーク値を検出できるため
忠実なエンベロープが得られる。"Effects of the Invention" As described above, according to the present invention, the envelope of an input waveform can be detected. Since the detection is performed using digital technology, the peak value can be detected with high precision, resulting in a faithful envelope.
第１図はこの発明によるエンベロープ測定器ノー例を示
すブロック図、第２図はその動作の説明に供する波形図
、第３図はこの発明の他の実施例を示すブロック図であ
る。FIG. 1 is a block diagram showing an example of an envelope measuring device according to the present invention, FIG. 2 is a waveform diagram for explaining its operation, and FIG. 3 is a block diagram showing another embodiment of the present invention.
Claims (1)
値に変換するＡＤ変換器と、 上記サンプリングクロックをｎ分の１に分周する分周器
と、 その分周器の分周出力ごとに上記ＡＤ変換器の出力の最
大値を検出する最大値検出器と、上記分周出力ごとに上
記ＡＤ変換器の出力の最小値を検出する最小値検出器と
、 上記分周出力ごとに上記最大値検出器の検出値及び上記
最小値検出器の検出値を記憶するメモリと、 そのメモリの内容を読み出して表示する表示器とを具備
するエンベロープ測定器。(1) An AD converter that converts the input waveform into a digital value for each sampling clock, a frequency divider that divides the sampling clock into 1/n, and the AD converter for each divided output of the frequency divider. a maximum value detector that detects the maximum value of the output of the AD converter, a minimum value detector that detects the minimum value of the output of the AD converter for each of the frequency division outputs, and a maximum value detector for each of the frequency division outputs. An envelope measuring instrument comprising: a memory for storing the detected value of the detection value and the detection value of the minimum value detector; and a display device for reading and displaying the contents of the memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9901388A JPH01269067A (en) | 1988-04-20 | 1988-04-20 | Envelope measuring instrument |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9901388A JPH01269067A (en) | 1988-04-20 | 1988-04-20 | Envelope measuring instrument |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01269067A true JPH01269067A (en) | 1989-10-26 |
Family
ID=14235237
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9901388A Pending JPH01269067A (en) | 1988-04-20 | 1988-04-20 | Envelope measuring instrument |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01269067A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08160081A (en) * | 1994-12-02 | 1996-06-21 | J R C Tokki Kk | Digital peak value hold circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54126442A (en) * | 1978-03-07 | 1979-10-01 | Hughes Aircraft Co | Method of and device for sampling data |
| JPS61200476A (en) * | 1985-02-28 | 1986-09-05 | Kinki Keisokki Kk | High speed developing and automatic recording apparatus therefor |
-
1988
- 1988-04-20 JP JP9901388A patent/JPH01269067A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54126442A (en) * | 1978-03-07 | 1979-10-01 | Hughes Aircraft Co | Method of and device for sampling data |
| JPS61200476A (en) * | 1985-02-28 | 1986-09-05 | Kinki Keisokki Kk | High speed developing and automatic recording apparatus therefor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08160081A (en) * | 1994-12-02 | 1996-06-21 | J R C Tokki Kk | Digital peak value hold circuit |
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