JPH08130244A - Forming method of local wiring - Google Patents

Abstract

PURPOSE: To form local wiring without causing damage to a substrate. CONSTITUTION: Cobalt silicide layers 9a are formed on upper surfaces of gate electrodes 7a, 7b and surfaces of N<+> impurity diffusion layers 5a, 5b at a low temperature wherein cobalt silicide is not agglomerated. Then, local wirings 10 are formed on the cobalt silicide layers 9a. After the local wirings 10 are formed, the cobalt silicide layers 9a are heat-treated at a high temperature higher than or equal to about 800 deg.C.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a local wiring, and more particularly to a method for forming a local wiring which can avoid etching damage to a substrate when patterning the local wiring.

[0002]

2. Description of the Related Art In recent years, in order to meet the demand for higher integration and higher speed of VLSI, a salicide (Self-Aligned silicide) technique for forming a silicide layer in a self-aligned manner and a local wiring for connecting adjacent transistors. Technology is being developed. Hereinafter, a method of manufacturing a semiconductor device using a salicide technique or a local wiring technique will be described with reference to FIGS. FIG. 14 is a partial cross-sectional view of a conventional semiconductor device having local wiring. First, the structure of a conventional semiconductor device having local wiring will be described with reference to FIG.

Referring to FIG. 14, isolation oxide film 2 is selectively formed on the main surface of p type silicon substrate 1. In the element formation region defined by the isolation oxide film 2,
N-impurity diffusion layers 4a and 4b and n + impurity diffusion layers 5a and 5b are formed at intervals. On the main surface of p-type silicon substrate 1 sandwiched by n-impurity diffusion layers 4a and 4b, gate insulating film 6 made of a silicon oxide film or the like is formed.
A gate electrode 7a is formed with the interposition of.

Further, another gate electrode 7b extends on the isolation oxide film 2. The gate electrodes 7a and 7b are preferably composed of polycrystalline silicon or the like. Sidewall spacers 8 made of a silicon oxide film or a silicon nitride film are formed on the side walls of the gate electrodes 7a and 7b. A cobalt silicide (CoSi ₂ ) layer 9 is formed on the upper surfaces of the gate electrodes 7a and 7b and the surfaces of the n + impurity diffusion layers 5a and 5b.

Then, a local wiring 10 is formed so as to extend from the surface of the cobalt silicide layer 9 formed on the surface of the n + impurity diffusion layer 5a to the cobalt silicide layer 9 formed on the upper surface of the gate electrode 7b. . The local wiring 10 is composed of a titanium layer 10a and a titanium nitride layer 10b. The local wiring 10 electrically connects the n + impurity diffusion layer 5a and the gate electrode 7b. Then, the local wiring 10 and the gate electrodes 7a and 7b
An interlayer insulating layer 11 made of a silicon oxide film or the like is formed so as to cover and.

Next, a method of manufacturing the semiconductor device shown in FIG. 14 will be described with reference to FIGS. FIG.
5 to 22 are cross-sectional views showing the first to eighth steps of the manufacturing process of the semiconductor device shown in FIG.

First, referring to FIG. 15, LOCOS (LOCal Oxidation of Silico) is formed on the main surface of p type silicon substrate 1.
n) method is used to form an isolation oxide film 2 for element isolation having a thickness of about 500 nm. Then, using the thermal oxidation method, 1
The gate insulating film 6 having a thickness of about 0 to 20 nm is formed.

Next, referring to FIG. 16, CVD (Chemic
Al vapor deposition method or the like is used to form a conductive film of polycrystalline silicon or the like to a thickness of about 300 to 500 nm. Then, the conductive film is patterned by using the photolithography technique and the anisotropic etching technique. Thereby, the gate electrodes 7a and 7b are formed. At that time, the gate insulating film 6 and the isolation oxide film 2 function as an etching stopper. Next, using the isolation oxide film 2 and the gate electrodes 7a and 7b as a mask, arsenic (A
An n-type impurity such as s) is injected into the main surface of the p-type silicon substrate 1. Then, a low-concentration (10 ¹⁷ to 10 ¹⁸ / cm ³ ) n-impurity diffusion layers 4a and 4b are formed by performing a thermal diffusion process.

Then, referring to FIG. 17, an insulating film such as a silicon oxide film or a silicon nitride film is formed to a thickness of about 100 to 200 nm by the CVD method or the like. Then, the insulating film is anisotropically etched. Thereby, the sidewall spacers 8 are formed on the sidewalls of the gate electrodes 7a and 7b. At this time, due to over-etching, the gate insulating film 6 other than directly under the gate electrodes 7a and 7b is
Are removed. The thickness of the isolation oxide film 2 is reduced by about 20 nm, but since the thickness of the isolation oxide film 2 is about 500 nm, there is no substantial influence.

Then, using gate electrodes 7a and 7b, sidewall spacer 8 and isolation oxide film 2 as a mask, an n-type impurity such as arsenic (As) is implanted into the main surface of p-type silicon substrate 1. Then, a thermal diffusion process is performed.
Thereby, high concentration (10 ¹⁹ to 10 ²⁰ / cm ³ ) of n +
Impurity diffusion layers 5a and 5b are formed, respectively. Note that n
-The heat treatment in forming the impurity diffusion layers 4a and 4b may be omitted, and the impurities may be activated by the heat treatment in this step.

Next, referring to FIG. 18, the upper surfaces of the gate electrodes 7a and 7b and the n + impurity diffusion layer 5 during transportation or the like.
Sputter etching is performed to remove the natural oxide film 12 formed on the surfaces of a and 5b. After that, as shown in FIG.
A cobalt (Co) layer 17 having a thickness of about 0 nm is formed. Then, the cobalt layer 17 is subjected to the first heat treatment. This first heat treatment is performed for 1 minute at a temperature of about 450 ° C. to 500 ° C. in nitrogen, argon or vacuum. As a result, the cobalt silicide layer is formed only at the portions where the cobalt layer 17 and the gate electrodes 7a and 7b or the n + impurity diffusion layers 5a and 5b are in contact with each other.
After that, the cobalt layer 17 that has not been silicidized is removed by, for example, a chemical solution containing hydrogen peroxide as a main component.

As a result, the cobalt silicide layer 9a is formed as shown in FIG. The cobalt silicide layer 9a formed at this time is made of Co ₂ S.
This is a layer containing a large amount of metal such as i and CoSi.

Then, referring to FIG. 21, the cobalt silicide layer 9a is subjected to a second heat treatment. This second heat treatment is performed at 800 ° C in nitrogen, argon or vacuum.
The temperature is about 1 minute. Thereby, the silicide reaction is further advanced. Thereby, for example, C
As in the case of oSi _2, the cobalt silicide layer 9 having a silicon content (composition ratio) relatively higher than a metal content (composition ratio) is formed.

Now, the reason why the above-described two-step heat treatment is performed to form the cobalt silicide layer 9 will be described. First, as described above, the first heat treatment is performed at a low temperature of about 450 ° C. to 500 ° C. for 800 times from the beginning.
When the cobalt silicide layer is formed at a high temperature of about ℃, silicon diffuses up to the side wall spacer 8 and the cobalt silicide layer is also formed on the side wall spacer 8. The cobalt silicide layer is formed in a region other than the desired region. This is because there is a concern that they will be connected by. In order to prevent such a phenomenon, first, the first heat treatment is performed at a low temperature at which the diffusion rate of silicon is low, and only the portion where silicon and the cobalt layer 17 are in contact with each other is selectively reacted to form the cobalt silicide layer 9a. ing. However, the cobalt silicide layer 9a formed at such a low temperature has a drawback that the sheet resistance is high. Further, the stress generated when forming the cobalt silicide layer 9a easily causes defects in the p-type silicon substrate 1. In order to recover such defects of the silicon substrate 1 and reduce the resistance of the cobalt silicide layer 9a,
A second heat treatment at a high temperature of about 800 ° C. is required. In view of the above contents, the two-step heat treatment as described above has been performed.

Next, the titanium layer 10a is formed to a desired thickness by using a sputtering method or the like, and the titanium layer 10a is formed.
The titanium nitride layer 10 is formed on the upper surface by using a sputtering method or the like.
b is formed. Then, the titanium layer 10a and the titanium nitride layer 10b are patterned by using the photolithography technique and the anisotropic etching technique. At this time, a chlorine-based gas is used for etching the titanium nitride layer 10b and the titanium layer 10a. As a result, the local wiring 10 is formed as shown in FIG.

Thereafter, the interlayer insulating layer 11 is formed by CVD or the like so as to cover the local wiring 10 and the gate electrodes 7a and 7b. Through the above steps, the semiconductor device having the conventional local wiring 10 shown in FIG. 14 is formed.

[0017]

It has been confirmed by TEM observation that the silicidation proceeds by the above-described two-step heat treatment, a silicide layer having a lower resistance can be formed, and crystal defects of the silicon substrate 1 can be recovered. There is. However, the above-described method of manufacturing a semiconductor device has the following problems. Regarding the problem, FIG. 23 to FIG.
This will be described using 5. In FIG. 23, the second heat treatment is 700
FIG. 9 is an enlarged cross-sectional view of a cobalt silicide layer 9c when performed at a temperature of about ° C. In FIG. 24, the second heat treatment is 8
FIG. 4 is an enlarged cross-sectional view of cobalt silicide layer 9 when performed at a temperature of about 00 ° C. FIG. 25 is an enlarged cross-sectional view showing a state where the main surface of p-type silicon substrate 1 is damaged by etching due to the patterning of local wiring 10.

First, referring to FIG. 23, a second heat treatment is performed at 80.
The necessity of performing at a high temperature of about 0 ° C will be described. Figure 2
7, when the second heat treatment is performed at a temperature of about 700 ° C., metal silicide layer 9c is not aggregated and is formed substantially uniformly. However, at such a temperature, the crystal defects of the silicon substrate 1, which particularly occur in the region 18 near the edge of the isolation oxide film 2, are not recovered. for that reason,
In this region 18, there arises a problem that a leak current easily occurs. Also, the cobalt silicide layer 9c
There is also a problem that the sheet resistance of can not be reduced sufficiently. This kind of problem is caused by the second problem at high temperatures above 800 ° C.
This can be solved by performing the heat treatment of.

However, as shown in FIG.
When the second heat treatment is performed at a high temperature of about 800 ° C. or higher, the cobalt silicide layer 9 aggregates and its end portion 19
At, the thickness becomes extremely thin. More specifically, the thickness of the cobalt silicide layer 9 becomes extremely thin in the vicinity of the sidewall spacer 8 or in the vicinity of the end portion of the isolation oxide film 2. As a result, the main surface of the silicon substrate 1 in the vicinity of the sidewall spacer 8 or the isolation oxide film 2 may be exposed.

The cobalt silicide layer 9 in such a state
FIG. 25 shows a case where the local wiring 10 is formed on the top. In anisotropic etching for forming the local wiring 10, chlorine-based gas is mainly used as described above. The cobalt silicide layer 9 is hardly etched by the chlorine-based gas, but the silicon substrate 1 is etched by the chlorine-based gas. Therefore, as shown in FIG. 25, when the cobalt silicide layer 9 becomes extremely thin and the silicon substrate 1 is exposed, the silicon substrate 1 is etched when the local wiring 10 is patterned. As a result, a recess is formed in the area 20 or the area 21 in FIG. If the recess is formed, for example, in the region 21 so as to penetrate the n + impurity diffusion layer 5a, there arises a problem of causing a junction breakdown. That is, there arises a problem that the reliability of the semiconductor device is deteriorated.

The present invention has been made to solve the above problems. An object of the present invention is to provide a method for forming a local wiring that can effectively prevent a reduction in reliability of a semiconductor device due to etching damage to a substrate during patterning of the local wiring.

[0022]

In the method for forming a local wiring according to the present invention, first, a first heat treatment is performed at a first temperature at which metal silicide does not aggregate, thereby forming a first heat treatment on the main surface of a semiconductor substrate. The first and second metal silicide layers are formed with a space. Then, a conductive layer is formed so as to cover the first and second metal silicide layers. By patterning this conductive layer, a local wiring that electrically connects the first and second metal silicide layers is formed. After forming the local wiring, the first and second metal silicide layers are subjected to a second heat treatment at a second temperature higher than the first temperature to reduce the resistance of the first and second metal silicide layers. Reduce.

[0023]

According to the local wiring forming method of the present invention,
First, the first and second metal silicide layers are formed at a first temperature at which the metal silicide does not aggregate. Therefore, at this stage, aggregation of the first and second metal silicide layers does not occur. That is, at this stage, the main surface of the semiconductor substrate is not exposed in the vicinity of the ends of the first and second metal silicide layers. Then, local wiring is formed on the first and second metal silicide layers in such a state. Therefore, when the local wiring is patterned, the first and second metal silicide layers sufficiently function as etching stoppers even in the vicinity of the end portions thereof. As a result, it becomes possible to effectively prevent the semiconductor substrate from being damaged by etching near the edges of the first and second metal silicide layers as in the conventional example. Then, after forming the local wiring, the first and second metal silicide layers are subjected to the second heat treatment, and the resistances of the first and second metal silicide layers are sufficiently reduced.

[0024]

Embodiments of the present invention will be described below with reference to FIGS.

(First Embodiment) First, a first embodiment of the present invention will be described with reference to FIGS. FIG.
FIG. 3 is a partial cross-sectional view showing a semiconductor device having a local wiring according to the first embodiment of the present invention. First, the structure of a semiconductor device having a local wiring according to the first embodiment of the present invention will be described with reference to FIG.

Referring to FIG. 1, isolation oxide film 2 is selectively formed on the main surface of p type silicon substrate 1. Then, the MOS transistor 3 is formed in the element forming region surrounded by the isolation oxide film 2. MOS transistor 3 has n-impurity diffusion layers 4a and 4b, n + impurity diffusion layers 5a and 5b, a gate insulating film 6, and a gate electrode 7a.

A cobalt silicide layer 9 is formed on the surfaces of the n + impurity diffusion layers 5a and 5b. Further, the cobalt silicide layer 9 is also formed on the upper surface of the gate electrode 7a.
Are formed. On the other hand, another gate electrode 7b extends on the isolation oxide film 2. The cobalt silicide layer 9 is also formed on the upper surface of the gate electrode 7b.

A sidewall spacer 8 made of a silicon oxide film or the like is formed on the sidewalls of the gate electrodes 7a and 7b. Then, from the cobalt silicide layer 9 formed on the surface of the n + impurity diffusion layer 5a to the gate electrode 7b.
The local wiring 10 is formed so as to extend on the surface of the cobalt silicide layer 9 formed on the upper surface of the. In this case, the local wiring 10 is composed of a titanium layer 10a and a titanium nitride layer 10b. An interlayer insulating layer 11 made of a silicon oxide film or the like is formed so as to cover the local wiring 10 and the gate electrodes 7a and 7b.

Next, a method of manufacturing the semiconductor device having the local wiring shown in FIG. 1 will be described with reference to FIGS. 2 to 5 are cross-sectional views showing characteristic first to fourth steps of the manufacturing process of the semiconductor device having the local wiring shown in FIG.

First, referring to FIG. 2, metal silicide layer 9a is formed through the same steps as in the conventional example. At this time, the metal silicide layer 9a is 450 ° C. to 500 ° C.
Since it is formed by heat treatment at about low temperature, it has a high metal content. More specifically, the cobalt silicide layer 9a is mainly composed of Co ₂ Si or Co.
It is made of Si. Moreover, since the cobalt silicide layer 9a is formed at a low temperature as described above, no aggregation occurs in the cobalt silicide layer 9a. Therefore, the cobalt silicide layer 9a is formed almost uniformly over the entire surface of the exposed n + impurity diffusion layers 5a and 5b.

Further, the cobalt silicide layer 9a is evenly formed over the entire upper surfaces of the gate electrodes 7a and 7b. A natural oxide film 12 may be formed on the surface of the cobalt silicide layer 9a during transportation of the semiconductor device. This natural oxide film 12 is removed by performing sputter etching. Thereby, the structure shown in FIG. 3 is obtained. In this way, the natural oxide film 12
It is possible to reduce the contact resistance between the local wiring 10 and the cobalt silicide layer 9a which will be formed in a later step by removing the.

The natural oxide film 12 is formed of hydrogen fluoride (H
In an atmosphere containing F) or BCl ₃Wafer to plasma
May be removed by exposing. In this case,
The native oxide film 12 was removed by sputter etching
Compared to the case, the generation of particles (dust) is less
You. As a result, the device yield can be improved.
It will be possible.

Further, in the conventional example, the method of removing the natural oxide film by sputter etching before forming the cobalt layer 17 has been described, but a method similar to the above case may be used instead of sputter etching. . Thereby, the surface of the silicon substrate 1 is not damaged by sputter etching, and the good quality cobalt silicide layer 9a can be formed. Here, "good quality" means that the interface between the cobalt silicide layer 9a and the silicon substrate 1 is smooth. Thereby, even if the impurity diffusion layer is formed shallow, the leak current can be reduced.

Next, referring to FIG. 4, a titanium layer 10a having a thickness of about 20 nm and a titanium nitride layer 10b having a thickness of about 100 nm are sequentially formed by the CVD method or the sputtering method. Then, the titanium layer 10a and the titanium nitride layer 10b are patterned by using the photolithography technique and the anisotropic etching technique. Thereby, the local wiring 10 is formed. At this time, the local wiring 10
A chlorine-based gas is mainly used in anisotropic etching for patterning the cobalt silicide layer 9a.
Are formed almost uniformly on the surface of the n + impurity diffusion layer 5a, so that the cobalt silicide layer 9a sufficiently functions as an etching stopper even in the vicinity of its end.
This makes it possible to prevent the silicon substrate 1 from being damaged by etching.

Next, referring to FIG. 5, after the local wiring 10 is formed, the second heat treatment is performed to the cobalt silicide layer 9a.
Is applied to. The conditions are nitrogen, argon or vacuum and a temperature of about 800 ° C. for 1 minute. Thereby,
A cobalt silicide layer 9 having a high silicon content is formed. More specifically, this cobalt silicide layer 9
Will be composed essentially of CoSi ₂ . As a result, the sheet resistance value of the cobalt silicide layer 9 can be sufficiently reduced. Specifically, the sheet resistance of the cobalt silicide layer 9 is about 1/5 of the sheet resistance of the cobalt silicide layer 9a.

By this second heat treatment, it becomes possible to recover the crystal defects of the silicon substrate 1 when the cobalt silicide layer 9a is formed. Thereby,
It is also possible to effectively suppress the generation of leak current. Furthermore, since the local wiring 10 has the titanium layer 10a, even if a natural oxide film is formed on the surface of the cobalt silicide layer 9, the natural oxide film can be reduced. As a result, the contact resistance between the local wiring 10 and the cobalt silicide layer 9 can be reduced.

6 and 7 are enlarged cross-sectional views of the vicinity of the n + impurity diffusion layer 5a or the vicinity of the gate electrode 7b after the above second heat treatment. 6 and 7, cobalt silicide layer 9 is aggregated by the second heat treatment described above, and the thickness thereof is extremely small at the end portion. However, since the local wiring 10 is already patterned, etching damage is not given to the main surface of the silicon substrate 1 unlike the conventional example.

Since the second heat treatment is performed with the local wiring 10 formed on the cobalt silicide layer 9a, titanium is deposited on the entire surfaces 13a and 13b of the titanium layer 10a and the cobalt silicide layer 9. An alloy layer of cobalt and silicon is formed. That is, the interfaces 13a and 13b
At, cobalt, titanium and silicon are mixed. Thereby, the contact between the cobalt silicide layer 9 and the local wiring 10 becomes more reliable. As a result, it is possible to further reduce the contact resistance between the local interconnection 10 and the n + impurity diffusion layer 5a and the gate electrode 7b.
Specifically, the resistance value when the 3000 local wirings 10 are connected is conventionally 140 ± 9 kΩ, but is 108 ± 9 kΩ.
It was reduced to 7 kΩ.

After the second heat treatment as described above,
The interlayer insulating layer 11 is formed by the same method as in the conventional example. Through the above steps, the semiconductor device shown in FIG. 1 is formed.

In the first embodiment, the interlayer insulating layer 11 was formed after the second heat treatment was completed.
However, the interlayer insulating layer 11 may be formed before performing the second heat treatment. In this case, the interlayer insulating layer 11 is preferably formed at a low temperature of 400 ° C. or lower. As a result, it is possible to effectively prevent the titanium nitride layer 10b from being oxidized and increasing the sheet resistance of the local wiring 10.

In the first embodiment described above, when the wafer is loaded into the heating chamber of the annealing apparatus for performing the second heat treatment, air is introduced into the heating chamber, and the titanium nitride layer is formed during the second heat treatment. There is concern that 10b may be oxidized. However, as in this case, the local wiring 10 is previously prepared at a low temperature.
By performing the second heat treatment with the interlayer insulating layer 11 formed so as to cover the titanium nitride layer 10b, it is possible to effectively oxidize the titanium nitride layer 10b even if air enters the heating chamber during the second heat treatment. It becomes possible to prevent it.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIGS. FIG.
[FIG. 3] is a cross-sectional view for explaining a problem of concern in the first embodiment described above.

In the first embodiment described above, the process of removing the natural oxide film 12 formed on the surface of the cobalt silicide layer 9a was performed before the formation of the local wiring 10. When sputter etching is used in this process, the cobalt silicide layer 9a itself is also etched. Here, since the cobalt silicide layer 9a is composed of two types of cobalt silicide layers of Co ₂ Si and CoSi as described above, there is a difference in the sputter etching rates thereof. Therefore, as shown in FIG. 8, the thickness of the cobalt silicide layer 9a may become uneven after the sputter etching.

Since this cobalt silicide layer 9a is formed by the first heat treatment, its thickness is about twice the thickness of the cobalt layer 17. And the second
By this heat treatment, the thickness of the cobalt silicide layer 9 becomes about four times the thickness of the cobalt layer 17. Therefore, the reduction amount of the thickness of the cobalt silicide layer 9a after the first heat treatment is doubled after the second heat treatment. Therefore, when there is a large amount of decrease in the thickness of the cobalt silicide layer 9a and a small amount of decrease in the thickness of the cobalt silicide layer 9a, the difference in thickness is further increased. As a result, there arises a problem that the variation in sheet resistance of the cobalt silicide layer 9 becomes large. This embodiment was devised to solve the above problems.

First, the cobalt silicide layer 9a is formed through the same steps as those in the first embodiment. Then, the cobalt silicide layer 9a is subjected to heat treatment at a temperature higher than in the case of the first heat treatment and lower than in the case of the second heat treatment. For example, about 650 ° C
Heat treatment is performed at a temperature of about 700 ° C. As a result, the silicide formation of the cobalt silicide layer 9a progresses, and the cobalt silicide layer (Co) having a high silicon content (composition ratio) is formed.
Si ₂ ) 9b is formed. However, 650 ° C to 700
Agglomeration of cobalt silicide does not occur at a temperature of about ° C. The thickness of the cobalt silicide layer 9b is about 3.5 times the thickness of the cobalt layer 17.

Next, the natural oxide film (not shown) on the surface of the cobalt silicide layer 9b is removed by using, for example, a sputter etching method before forming the local wiring 10. At this time, the cobalt silicide layer 9b is almost uniformly etched because it is almost composed of CoSi ₂ . This makes it possible to suppress variations in the thickness of the cobalt silicide layer 9b to be small.

After that, the local wiring 10 is formed by the same method as in the case of the first embodiment. After forming the local wiring 10, the metal silicide layer 9b is subjected to the second heat treatment under the same conditions as in the case of the first embodiment. Thereby, the cobalt silicide layer 9 is formed. By this second heat treatment, the crystal defects of the silicon substrate 1 are recovered and the cobalt silicide layer 9 is agglomerated. However, the thickness of the cobalt silicide layer 9 is more uniform than in the case of performing the sputter etching before forming the local wiring 10 in the first embodiment.

Also in this embodiment, as in the case of the first embodiment described above, after the interlayer insulating layer 11 is formed at a low temperature so as to cover the local wiring 10 and the gate electrodes 7a and 7b, the second insulating film 11 is formed. The heat treatment may be performed. Thereby,
The same effect as in the case of the first embodiment can be obtained.

Next, modified examples of the first and second embodiments described above will be described with reference to FIGS. 12 and 13.
12 and 13 are cross-sectional views showing modified examples of the first and second embodiments described above.

First, referring to FIG. 12, a silicon oxide film 14 into which no impurities are introduced is formed so as to cover local interconnection 10 and gate electrodes 7a and 7b, and silicon nitride film 15 is formed on this silicon oxide film 14. Is formed. BPSG (Boro Phospho Sil) is formed on the silicon nitride film 15.
An icate glass) film 16 is formed. in this way,
Silicon oxide film 14, silicon nitride film 15 and BPS
After forming the G film 16, the second heat treatment in the first and second embodiments may be performed. This heat treatment can also serve as reflow of the BPSG film 16. At this time, by having the silicon nitride film 15, it becomes possible to effectively suppress the diffusion of oxygen in the vicinity of the local wiring 10. Further, by forming the silicon oxide film 14 in which impurities are not introduced,
It is possible to prevent the diffusion of impurities such as boron and phosphorus. Thereby, it becomes possible to effectively prevent the titanium nitride layer 10b in the local wiring 10 from being oxidized.

Next, referring to FIG. 13, in this case, silicon nitride film 1 is formed without forming silicon oxide film 14.
5 and the BPSG film 16 are formed. Also in this case, the same effect as that shown in FIG. 12 is obtained.

In each of the above embodiments, the case where the cobalt silicide layer is formed as the metal silicide layer has been described. However, Ni, Pt, W, Ti, T
Any metal may be used to form the metal silicide, such as a, Mo, or Re, which is a metal that forms the metal silicide. Further, instead of the cobalt layer 17, each of the above metals (Ni,
Any alloy of Pt, W, Ti, Ta, Mo, Re) or a laminated film of these metals may be used. Further, as the local wiring 10, a laminated structure of a titanium layer and a titanium silicide layer may be used. Also in this case, patterning can be performed using a chlorine-based gas.

[0053]

As described above, according to the present invention, the metal silicide layer can effectively function as an etching stopper when patterning a local wiring. This makes it possible to form the local wiring without damaging the semiconductor substrate by etching. This makes it possible to form a semiconductor device having highly reliable local wiring.

[Brief description of drawings]

FIG. 1 is a partial cross-sectional view showing a semiconductor device having a local wiring according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a characteristic first step in the manufacturing process of the semiconductor device having the local wiring shown in FIG.

FIG. 3 is a cross-sectional view showing a characteristic second step in the manufacturing process of the semiconductor device having the local wiring shown in FIG.

FIG. 4 is a cross-sectional view showing a characteristic third step of the manufacturing process of the semiconductor device having the local wiring shown in FIG. 1.

5 is a cross-sectional view showing a characteristic fourth step of the manufacturing process of the semiconductor device having the local wiring shown in FIG. 1. FIG.

6 is an enlarged cross-sectional view of the vicinity of an n + impurity diffusion layer in FIG.

FIG. 7 is an enlarged cross-sectional view of the vicinity of a gate electrode extending on the isolation oxide film in FIG.

FIG. 8 is a cross-sectional view for explaining a problem of concern in the first embodiment.

FIG. 9 is a sectional view showing a characteristic first step in the manufacturing process of the semiconductor device having the local wiring according to the second embodiment of the present invention.

FIG. 10 is a sectional view showing a characteristic second step in the manufacturing process of the semiconductor device having the local wiring according to the second embodiment of the present invention.

FIG. 11 is a sectional view showing a characteristic third step of the manufacturing process of the semiconductor device having the local wiring according to the second embodiment of the present invention.

FIG. 12 is a partial cross-sectional view showing a semiconductor device having local wiring in a modification of the first and second embodiments.

FIG. 13 is a partial cross-sectional view showing a semiconductor device having local wiring in a modification of the first and second embodiments.

FIG. 14 is a partial cross-sectional view showing a conventional semiconductor device having local wiring.

FIG. 15 is a partial cross-sectional view showing a first step of the manufacturing process of the semiconductor device having the conventional local wiring shown in FIG.

16 is a partial cross sectional view showing a second step of the manufacturing process for the semiconductor device having the conventional local wiring shown in FIG.

17 is a partial cross sectional view showing a third step of the manufacturing process for the semiconductor device having the conventional local wiring shown in FIG.

FIG. 18 is a partial cross sectional view showing a fourth step of the manufacturing process for the semiconductor device having the conventional local wiring shown in FIG.

FIG. 19 is a partial cross sectional view showing a fifth step of the manufacturing process for the semiconductor device having the conventional local wiring shown in FIG. 14.

FIG. 20 is a partial cross sectional view showing a sixth step of the manufacturing process for the semiconductor device having the conventional local wiring shown in FIG. 14.

21 is a partial cross sectional view showing a seventh step of the manufacturing process of the semiconductor device having the conventional local wiring shown in FIG. 14. FIG.

22 is a partial cross-sectional view showing an eighth step of manufacturing the semiconductor device having the conventional local wiring shown in FIG.

FIG. 23 is a partial cross-sectional view showing the shape of a cobalt silicide layer when the second heat treatment is performed at a temperature of about 700 ° C.

FIG. 24 is an enlarged cross-sectional view of the vicinity of the n + impurity diffusion layer in FIG.

FIG. 25 is a cross-sectional view showing a problem of a conventional method of forming a local wiring.

[Explanation of symbols]

1 p-type silicon substrate, 2 isolation oxide film, 3 MOS transistor, 4a, 4b n-impurity diffusion layer, 5a, 5
b n + impurity diffusion layer, 6 gate insulating film, 7a, 7b
Gate electrode, 8 Sidewall spacer, 9, 9
a, 9b, 9c cobalt silicide layer, 10a titanium layer, 10b titanium nitride layer, 10 local wiring, 11 interlayer insulating layer, 12 natural oxide film, 13a, 13b interface,
14 silicon oxide film, 15 silicon nitride film, 16
BPSG film, 17 cobalt layer.

Claims (10)

[Claims] 1. A step of forming a first and a second metal silicide layers at intervals on a main surface of a semiconductor substrate by performing a first heat treatment at a first temperature at which metal silicide does not aggregate. A step of forming a conductive layer so as to cover the first and second metal silicide layers, and a local wiring for electrically connecting the first and second metal silicide layers by patterning the conductive layer And a step of forming the local wiring and then subjecting the first and second metal silicide layers to a second heat treatment at a second temperature higher than the first temperature. And a step of reducing the resistance of the second metal silicide layer. 2. The step of forming the first and second metal silicide layers comprises: after the first heat treatment and before forming the conductive layer,
The method according to claim 1, further comprising performing a third heat treatment at a third temperature that is higher than the first temperature and lower than the second temperature and that does not cause the first and second metal silicide layers to aggregate. Method of forming local wiring. 3. In the third heat treatment, a composition ratio of silicon contained in the first and second metal silicide layers is higher than a composition ratio of metals contained in the first and second metal silicide layers. The method for forming a local wiring according to claim 2, wherein the method is performed under a temperature condition that increases the temperature. 4. The step of performing the second heat treatment, the step of forming an interlayer insulating layer so as to cover the local wiring, and the step of performing the second heat treatment with the interlayer insulating layer formed. The method for forming a local wiring according to claim 1, further comprising: 5. The interlayer insulating layer has a laminated structure of a silicon oxide film and a silicon nitride film, and the step of forming the interlayer insulating layer includes the step of forming the silicon oxide film and the step of forming the silicon nitride film. The method for forming a local wiring according to claim 4, further comprising a step of forming. 6. The step of forming the conductive layer comprises applying hydrogen fluoride or BCl ₃ plasma to the first and second steps.
The method for forming a local wiring according to claim 1, further comprising the step of forming the conductive layer after exposing the surface of the metal silicide layer of. 7. The local wiring has a laminated structure of a titanium layer and a metal nitride layer formed on the titanium layer, and the first and second metal silicide layers are cobalt silicide layers. The step of performing the second heat treatment includes the step of forming an alloy layer containing titanium, cobalt, and silicon on the entire interface between the local wiring and the first and second metal silicide layers. A method for forming a local wiring as described in 1. 8. An impurity diffusion layer is formed on the main surface of the semiconductor substrate, and a gate electrode is formed on the main surface of the semiconductor substrate at a distance from the impurity diffusion layer. In the step of forming the metal silicide layer, the step of forming a metal layer so as to cover the impurity diffusion layer and the gate electrode, and the first heat treatment of the metal layer to form a surface of the impurity diffusion layer. 2. The method for forming a local wiring according to claim 1, further comprising: a step of forming the first and second metal silicide layers on the upper surface of the gate electrode; and a step of removing the unreacted metal layer. . 9. The local wiring has a laminated structure of a titanium layer and a titanium silicide layer or a titanium nitride layer formed on the titanium layer, and the conductive layer forming step includes: The step of forming the titanium layer so as to cover the second metal silicide layer, and the step of forming the titanium silicide layer or the titanium nitride layer on the titanium layer. The method for forming a local wiring according to claim 1, comprising a step of sequentially etching the titanium silicide layer or titanium nitride layer and the titanium layer using a system gas. 10. The step of forming the first and second metal silicide layers, wherein the composition ratio of the metals contained in the first and second metal silicide layers is the same as that of the first and second metal silicide layers. The step of forming the first and second metal silicide layers so as to have a composition ratio of silicon contained therein or higher, and the step of performing the second heat treatment includes the steps of forming the first and second metal silicide layers in the first and second metal silicide layers. A relatively high temperature heat treatment on the first and second metal silicide layers so that the composition ratio of silicon contained in the first and second metal silicide layers is higher than that of the metals contained in the first and second metal silicide layers. The method for forming a local wiring according to claim 1, further comprising: