JPH08129836A - Digital information signal recorder and reproducer - Google Patents

Abstract

PURPOSE: To drastically reduce the number of access times by equipping a C2 code generating circuit and a C2 arithmetic circuit to carry out signal processing in using a C2 code memory and moreover a C2 correction circuit for performing correction processing in using a picture memory. CONSTITUTION: The C2 code memory can be incorporated into a signal processing circuit 7 when LSI is applied to this circuit. Moreover, by equipping the C2 correction circuit for performing correction processing in using a memory, e.g. the picture memory to be used for signal processing after an error correcting circuit, a compressed video signal stored in the picture memory 1 can be accessed, and hence correction processing can be performed on the compressed video signal. Then, by efficiently storing audio data, a storage capacity of the memory can be suppressed, and hence the memory can be incorporated into the signal processing circuit 7 when LSI is applied to this circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PCM signal reproducing apparatus, and more particularly to signal processing for digital audio, digital VTR and the like.

[0002]

2. Description of the Related Art PCM signal recording / reproducing technology has been applied in various fields in recent years. As an example of applying this technology to a home digital VTR, IEE, Transactions on Consumer Electronics, Vol. 35, No. 3, August 1989, pp. 450-457 (IEEE, Transactions)
on Consumer Electronics, V
ol. 35, No. 3, AUGUST 1989, pp
450-457). In this description example, 8 vertical pixels and 8 horizontal pixels on the video screen are considered as one block from the pixel data stored in the frame memory that stores digital video signals for one frame. In this method, data compression is performed and several compressed blocks are collectively encoded and a Reed-Solomon code that is double-encoded is added as an error correction code to form a data frame, which is recorded on a magnetic tape. As described above, in the system in which the error correction code double-coded in the orthogonal direction is added and the recording / reproduction is performed, the outer code (C2
After generating the code), it is necessary to store the data and all the generated C2 codes in the memory once, and generate the inner code (C1 code) while reading from the memory. Also,
At the time of reproduction, it is necessary to store C1 decoded data and all C2 codes in the memory once, and perform C2 decoding while reading from the memory.

As described above, a digital VTR that compresses / expands a video signal in frame units, adds an error correction code, and records / reproduces it. In addition to the frame memory, a memory dedicated to the error correction process is required. Furthermore, when recording and reproducing digital audio signals at the same time, a memory dedicated to audio signal processing is required.

[0004]

In order to realize a home digital VTR with the configuration shown in the prior art, a memory dedicated to video signal processing and a memory dedicated to audio signal processing are required in addition to the frame memory. Increased cost is a challenge. Since the home-use digital VTR is targeted for home use, keeping the cost low is an important issue.

An object of the present invention is to reduce the number of memories, thereby suppressing an increase in cost, and to make a digital VT for home use.
To provide R.

[0006]

In order to achieve the above object, the present invention provides an image signal processing circuit for performing image signal processing, an image memory, and an error correction process of a double-encoded error correction code. In a digital VTR composed of a signal processing circuit for performing, a C2 code generation circuit for performing signal processing using a C2 code memory, a C2 arithmetic circuit, and a C2 correction circuit for performing a correction process using an image memory are provided.
Built-in memory to store audio data.

[0007]

Since the C1 code sequence is the same as the time-series order of recording / reproduction, the generation and decoding of the C1 code may be processed in the time-series order, and a large-scale memory is not required. Since the generation and decoding of the C2 code is different from the time series order of recording and reproduction, it is necessary to store all the data once in a large-scale memory. However, by providing a C2 code generation circuit and a C2 arithmetic circuit that perform signal processing using a C2 code memory that stores a C2 code, a memory with a capacity for storing the C2 code is sufficient, and a large-scale memory is used. Instead, the C2 code can be generated and operated. This C2 code memory can be incorporated when the signal processing circuit is formed into an LSI. Further, by providing a memory used for signal processing after the error correction processing, for example, a C2 correction circuit for performing correction processing using an image memory, it is possible to access the compressed video signal stored in the image memory. It is possible to correct the compressed video signal. Further, by efficiently storing the audio data, the storage capacity of the memory can be suppressed, and the memory can be built in when the signal processing circuit is formed into an LSI.

As described above, the external memory required for the signal processing circuit for generating and decoding the C2 code and the external memory for processing the audio signal can be reduced and the cost can be suppressed. it can.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the present invention. The first embodiment is applied to a digital VTR that converts a video signal and an audio signal into a digital signal, compresses the video signal, adds an error correction code, and records and reproduces.

First, the recording format will be described with reference to FIGS. 2 and 3. FIG. 2 is a track format diagram recorded on the magnetic tape. As shown in FIG.
Video signal Video signal and audio signal for one frame are
It is divided into 10 tracks and recorded. The video signal and the audio signal are shuffled within 10 tracks to minimize the influence of burst error. Each track is a video signal track 21 and an audio signal track 22.
And each of them has the data format shown in FIG. FIG. 3A shows a block 31 forming a data format, which includes a header 3
2 and compressed video / audio data, C2 code 33, C
It is composed of a reference numeral 34. FIG. 3B shows a video signal data format 35, which has a configuration in which 149 blocks 31 shown in FIG. The compressed video data 38 shown in the figure is composed of a compressed video signal and auxiliary data. FIG. 3C shows a data format 37 of an audio signal, which is composed of a block 31 like a video signal, and audio data 39 is composed of a digital audio signal and auxiliary data. As shown in FIG. 3, the C1 code sequence is the same in the recording direction and is common to the video signal and the audio signal. Therefore, the generation of the C1 code 34 and the error correction process may be performed in time series during recording and reproduction, so that no memory is required and the circuit can be shared by the video signal and the audio signal. However, since the C2 code sequence is in the recording direction, that is, the direction orthogonal to the C1 code sequence, it cannot be processed in time series order during recording and reproduction. Therefore, generation of the C2 code 36 and error correction processing require a memory, and separate processing is required for the video signal and audio signal.

Next, the operation during recording will be described first. The video signal to be recorded is converted into a digital video signal by the AD converter 2, and the converted digital video signal is input to the image signal processing circuit 6. In the image signal processing circuit 6,
The video signal is compressed and the C2 code is generated. FIG. 4 is a block diagram showing an example of the image compression circuit 6. The input digital video signal is input to the image memory 1 through the interface circuit (I / F circuit) 41, and the digital video signal for one frame is stored. The one-frame digital video signal stored in the image memory 1 is image-compressed by the image compression / expansion circuit 43, and the compressed image-compressed video signal is stored again in the image memory 1. next,
The compressed video signals stored in the image memory 1 are read out in the order of the C1 code sequence and output to the signal processing circuit 7 via the I / F circuit 44.

The signal processing circuit 7 generates the C2 code and the C1 code of the compressed video signal and the digital audio signal, forms the data format shown in FIG. 3 and outputs them as a recording signal. FIG. 5 is a block diagram showing an example of the signal processing circuit 7. The compressed video signal input from the image signal processing circuit 6 through the I / F circuit 57 is input to the C1 code generation circuit 59 and the C2 code generation circuit 510, and C
1, C2 code is generated. The C1 code can be generated without using a memory because the C1 code is read out from the image memory 1 in the order of the C1 code sequence. However, since the C2 code sequence is orthogonal to the C1 code sequence, the C2 code is generated while the calculation result is held in the C2 code memory 511. C2 in FIG.
FIG. 7 is a block diagram showing an example of the configuration of the code generation circuit and the C2 code memory. FIG. 6 is basically a Reed-Solomon coding circuit. However, since the C2 code is not reproduced in chronological order, it is necessary to store the calculation result in the C2 code memory 511 for each C2 code series. It uses memory. In the configuration of FIG. 6, a C2 code arithmetic circuit and a C2 code memory are set as one set and arranged by the number of C2 codes, and 11 sets of the C2 code arithmetic circuit and the C2 code memory are required in this embodiment. In 6 the first set and 1
Only the first set is shown and the others are omitted. The data stored in each C2 code memory stores the portion shown in the data format diagram of FIG. For example, C2 code memory 16
Reference numeral 4 is the first C2 code and has an address area in the direction of the C1 code sequence. That is, one C2 code memory is 77
It has a capacity of bytes, which is the number of C2 codes, that is, 11
Exist individually. Memory capacity is 77 × 11 × 8 = 6.8k
It becomes a bit and is a capacity that can be built in when the signal processing circuit is made into an LSI.

Next, the operation will be described. C input
The m-th (m = 1 to 77) compressed video signal of one code sequence is input to an arithmetic circuit to be arithmetically operated, and the C2 code arithmetic circuit 1
The output from 63 to the C2 code arithmetic circuit 1165. The address controller 62 sets the address of the C2 code memory to m
I see it as a byte. The C2 code arithmetic circuit n of the n-th group is (n>
1), while holding the output of the m-th byte of the C2 code memory (n-1), the output of the arithmetic circuit is operated and the result is C2.
It is stored in the mth byte of the code memory n. in this way,
By reading / writing the C2 code memory 511 every time one data of the C1 code sequence is input,
It is possible to generate the C2 code of the compressed video signal read in the order of the code sequence. The C2 code is determined when all the compressed video signals are input, and each C2 code memory is sequentially read from the beginning of the C2 code memory 164, so that the generated C2 code becomes the C1 code sequence, and the C1 code generation circuit. Input to 59 to generate a C1 code.

On the other hand, the digital audio signal is I /
It is stored in the audio memory 53 via the F circuit 51.
Here, the audio memory 53 needs a processing time for one frame in order to perform the compression processing on the video signal,
Further, since the digital audio signal is shuffled and recorded during one frame, it is necessary to hold the digital audio signal for two frames. The digital audio signal for 2 frames is data for 20 tracks from the track format of FIG. According to the data format shown in FIG. 3, the data amount of the audio data 39 consisting of the digital audio signal of one track and the auxiliary data is 77 × 9 = 693 bytes. Considering that the flag is stored in the error correction process during reproduction, 78 × 1
0 = 780 bytes are required. Furthermore, the amount of data of C2 code is required for the track immediately before recording,
It is 8 × 14 = 1092 bytes. Therefore, the amount of data held in the audio memory is (780 × 19 + 1092) × 8 = 127.296 kbits when expressed in bits. In other words, 128k bits (2 to the 17th power bit)
It is sufficient if there is a memory of the signal processing circuit 7 as an LSI.
It is a scale that can be built in when it becomes. The digital audio signal stored in the audio memory 53 is read in the order of the C2 code sequence, the C2 code is generated by the C2 code generation circuit 56, and the generated C2 code is stored in the audio memory 53. The generated C2 code and digital audio signal are read out in the order of the C1 code sequence and output to the C1 code generation circuit 59 to generate and add the C1 code. Also, the compressed video signal and its C2 code are I / O in the order of the C1 code sequence.
It is inputted to the C1 code generation circuit 59 via the F circuit 57
1 code is generated and added. Since the C1 code sequence is the same as the time-series order to be recorded, the generation of the C1 code requires only a small-scale buffer for adjusting the timing, and does not require a memory or the like. The compressed video signal and digital audio signal to which the C1 code and the C2 code are added are stored in the buffer 51.
3 and outputs the signal to the modulation circuit 514 in synchronization with the cylinder head 8. In the modulation circuit 514, modulation is performed by a modulation method suitable for the magnetic tape and recorded on the magnetic tape 9.

Next, the operation during reproduction will be described. At the time of reproduction, the reproduction signal reproduced from the magnetic tape 9 using the cylinder head 8 is demodulated in the signal processing circuit, and error correction (C1 decoding) using the C1 code is performed. The reproduction signal input to the signal processing circuit 7 is input to the demodulation circuit 515 of FIG. 5 to demodulate the reproduction signal and input to the buffer 513. The buffer 513 rebuilds the time series in the variable speed reproduction and adjusts the timing, and outputs the reproduction signal to the C1 decoding circuit 58. The C1 decoding circuit 58 performs error correction using the C1 code. Since the C1 code sequence matches the time series order of the reproduced signal, a storage circuit such as a memory is not required. The compressed video signal and the digital audio signal which have been error-corrected using the C1 code and the respective C2 codes are distributed and output. The compressed video signal and its C2 code are output to the image signal processing circuit 6 via the C2 arithmetic circuit 512 and the I / F circuit 57, and further to the image signal processing circuit 6 the error correction state flag at the time of C1 decoding. By using the flag at the time of C1 decoding at the time of C2 decoding, the reliability of error correction processing can be improved. The address information of the compressed video signal is obtained by extracting the address information from the decoding result by the I / F circuit 57, and is used when the image compression / expansion circuit 43 performs the expansion processing at the time of variable speed reproduction. The digital audio signal, its C2 code, and flag information at the time of C1 decoding are output to and stored in the audio memory 53.

In the C2 arithmetic circuit 512, the C1 decoding circuit 5
The C2 code is calculated using the error-correction-processed compressed video signal output from S8 and the C2 code. Since the C2 code sequence does not match the time-series order of the reproduced signal, the calculation result is held in the C2 code memory 511 as in the recording. FIG. 8 is a block diagram showing an example of the C2 arithmetic circuit. FIG. 8 is basically a Reed-Solomon code syndrome operation circuit, but a memory is used instead of a register so as to hold the operation result. Although there are as many C2 code arithmetic circuits and C2 code memories as the number of C2 codes in the configuration, the first, second, and eleventh groups are omitted in FIG.

The operation is basically the same as that of the C2 code generation circuit. The input m-th compressed video signal of the C1 code sequence and the C2 code are input from the C2 arithmetic circuit 181 to the C2 arithmetic circuit 1183. The address controller 62 includes the C2 code memory 1 64 to the C2 code memory 1 66.
The address is set to the m-th byte, and the m-th byte data of each C2 code memory is output. The n-th set of C2 code operation circuit n performs an operation while holding the output from the C2 code memory n, and stores the result in the C2 code memory n. Thus, every time one piece of data of the C1 code sequence is input, C2
By reading / writing the code memory 511,
It is possible to perform the syndrome calculation of the C2 code of the compressed video signal reproduced in the order of the C1 code sequence. The C2 calculation result obtained by the C2 calculation circuit 512 is output to the image signal processing circuit 6.

At the time of reproduction, the image signal processing circuit 6 reproduces the original digital video signal by performing correction processing and image expansion processing of the compressed video signal by the C2 code. The compressed video signal and the flag input to the image signal processing circuit 6 are temporarily stored in the image memory 1 based on the address information. C2 correction circuit 4
5, the flag indicating the error state at the time of C1 decoding and C2
Data for C2 correction is obtained from the calculation result, and error correction processing is performed while accessing the image memory 1. here,
The image correction circuit 42 exchanges the block data of the previous frame for the block in which the uncorrectable data is generated after the error correction process or the block which is not reproduced in the variable speed reproduction. The compressed video signal subjected to the error correction processing and the image correction processing is expanded by an image compression / expansion circuit to output a digital video signal, and DA converted by a DA converter 3 to obtain a video signal. On the other hand, the digital audio signal is the C1 decoded digital audio signal and its C
The error correction process using the C2 code is performed from the 2 code, and the frame is stored in the audio memory 53 for 2 frames to match the timing with the video signal to be reproduced as in the recording, and the digital audio signal is output. Converter 5
To perform DA conversion to reproduce an audio signal.

According to the embodiment, since the C2 code can be generated and decoded and the signal processing of the audio signal can be performed without providing an external memory, the memory such as an external memory required for the signal processing circuit is stored. A circuit is not required, external parts can be reduced, and cost can be reduced. Moreover, since the image memory 1 is not used for the generation of the C2 code or the syndrome calculation, the number of accesses to the image memory 1 can be significantly reduced.

In the embodiment, the image signal processing circuit is described as the signal processing for compressing / expanding an image. However, one track is added to information for signal processing in a unit of a plurality of tracks such as signal processing for compressing / expanding an audio signal. If the system which records and reproduces by adding the error correction code completed in 1) is used, the number of memories can be saved by using the present invention.

[0021]

According to the present invention, since the C2 code can be generated and decoded without providing an external memory, a storage circuit such as a memory which is necessary for the signal processing circuit is not required, and the external circuit is not required. The number of parts can be reduced and the cost can be reduced. In addition, since the memory used for other processing such as the image memory is not used for the generation of the C2 code and the syndrome calculation, the load on other processing and the number of times of access to the memory are significantly reduced. Can be made.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of the present invention.

FIG. 2 is a track format diagram showing the structure of a track of the present invention.

FIG. 3 is a data format diagram showing a data structure of the present invention.

FIG. 4 is a block diagram of an image signal processing circuit according to the present invention.

FIG. 5 is a block diagram of a signal processing circuit according to the present invention.

FIG. 6 is a block diagram of a C2 code generation circuit according to the present invention.

FIG. 7 is a data format diagram showing an arrangement of a C2 code memory of the present invention.

FIG. 8 is a block diagram of a C2 code arithmetic circuit according to the present invention.

[Explanation of symbols]

 1 ... Image memory, 2 and 4 ... AD converter, 3 and 5 ... DA converter, 6 ... Image signal processing circuit, 7 ... Signal processing circuit, 8 ... Cylinder head, 9 ... Magnetic tape.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical display location H04N 5/93 H04N 5/93 C Z

Claims (6)

[Claims] 1. A digital information signal recording device for recording a digital information signal by adding an error correction code double-encoded with a C1 code and a C2 code, and a C2 code memory for storing the C2 code, and a recording device. The digital information signal and the C2 input in time series
The output of the code memory is operated, the operation result is stored in the C2 code memory for each sequence of the C2 code, the C2 code generating circuit for generating the C2 code, and the digital information input in time series to be recorded. An apparatus for recording a digital information signal, comprising: a signal; and a C1 code generation circuit for reading the C2 code stored in the C2 code memory in a time-series order to generate the C1 code. 2. A digital information signal reproducing apparatus which reproduces a signal recorded by adding an error correction code double-encoded with a C1 code and a C2 code to a digital information signal, and the signals are inputted in a time-series reproduced order. A C1 decoding circuit for performing C1 decoding of the digital information signal and the C2 code and outputting a decoding result in time series order, a C2 code memory for storing the C2 code, a decoding result and the C2 code memory. A C2 arithmetic circuit that calculates the output, stores the calculation result in the C2 code memory for each sequence of the C2 code, and performs the syndrome calculation of the C2 code, and stores the decoding result and the syndrome calculation result of the C2 code. Memory and a C2 correction circuit for correcting the decoding result stored in the memory based on the syndrome calculation result of the C2 code. An apparatus for reproducing a digital information signal, comprising: 3. An audio data composed of a digital audio signal and auxiliary data in one video frame period is divided, and is completed by one of the divided audio data.
In a digital information signal recording apparatus for adding an error correction code double-encoded with a 1 code and a C2 code to the divided audio data to form a data format for recording, the audio data in two video frame periods, A memory that stores the C2 code for one data format, and the audio data stored in the memory is read by a code sequence of the C2 code to generate the C2 code, and the generated C2 code is stored in the memory. C2 to remember
A digital information signal, comprising: a code generation circuit; and a C1 code generation circuit for reading the audio data and the C2 code stored in the memory in time series for recording, generating the C1 code and adding the C1 code. Recording device. 4. The audio data according to claim 3, wherein the audio data is divided into 10 pieces, one piece of the divided audio data is 77 × 9 bytes or less, 8 bytes of the C1 code are generated, and the C2 code is 5 bytes. A device for recording a digital information signal, in which bytes are generated and added to the divided audio data to form and record the data format of 85 × 14 bytes, and the storage capacity of the memory is set to 2 17 bits or less. 5. An audio data composed of a digital audio signal and auxiliary data in one video frame period is divided, and is completed by one of the divided audio data.
A digital information signal reproducing apparatus which reproduces a recorded signal by adding an error correction code double-encoded with a 1 code and a C2 code to the divided audio data to form a data format and reproduces the recorded signal. Audio data, a C1 code flag generated when C1 decoding the data format in the two video frame periods, and C2 generated when C2 decoding the audio data in the two video frame periods
A code flag and the C for one data format
A memory for storing two codes, C1 decoding of the reproduced data format, C1 decoded digital audio signal, C2 code, and C1 code flag indicating a state of C1 decoding are stored in the memory. A C1 decoding circuit for performing the C2 decoding based on the digital audio signal stored in the memory, the C2 code, and the C1 code flag, and showing the C2 decoded digital audio signal and the C2 decoding state. And a C2 decoding circuit for storing the C2 code flag in the memory. 6. The audio data according to claim 5, wherein the audio data is divided into 10 pieces, and the divided audio data is 77 × 9 bytes or less,
8 bytes of the C1 code and 5 bytes of the C2 code are added to the divided audio data.
The recorded signal is reproduced by configuring the data format of 5 × 14 bytes, and the storage capacity of the memory is 2 to 17.
A device for reproducing a digital information signal with a power of 2 bits or less.