JPH0812845B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0812845B2 JPH0812845B2 JP8569089A JP8569089A JPH0812845B2 JP H0812845 B2 JPH0812845 B2 JP H0812845B2 JP 8569089 A JP8569089 A JP 8569089A JP 8569089 A JP8569089 A JP 8569089A JP H0812845 B2 JPH0812845 B2 JP H0812845B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- wiring
- protective insulating
- film
- final protective
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は半導体装置の製造方法、特に、配線上の最終
保護用絶縁膜の製造方法に関するものである。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a final protective insulating film on a wiring.
（従来の技術） 従来、Al配線上の最終保護用絶縁膜の形成方法は、第
２図に示すような構成であった。(Prior Art) Conventionally, a method for forming a final protective insulating film on an Al wiring has a structure as shown in FIG.
第２図において、１は半導体基板、２は絶縁膜、３は
Al配線、４は第１の最終保護用絶縁膜、５はボイドを示
す。すなわち、第２図のように、まず半導体基板１の表
面に絶縁膜２を形成した後、Al配線３を形成する。次に
シランとアンモニアを原料ガスとして、プラズマ気相成
長（CVD）法により、8000〜10000Åのシリコンナイトラ
イド膜を蒸着し、第１の最終保護用絶縁膜４を形成す
る。In FIG. 2, 1 is a semiconductor substrate, 2 is an insulating film, and 3 is
Al wiring, 4 is a first final protective insulating film, and 5 is a void. That is, as shown in FIG. 2, the insulating film 2 is first formed on the surface of the semiconductor substrate 1, and then the Al wiring 3 is formed. Next, using silane and ammonia as source gases, a silicon nitride film of 8000 to 10000Å is deposited by plasma vapor deposition (CVD) method to form a first final protective insulating film 4.
（発明が解決しようとする課題） このような従来の方法では、Al配線３の上部の第１の
最終保護用絶縁膜４がオーバーハングになり、Al配線間
隔が１μｍ以下になるとオーバーハングの上部同士がつ
ながるため第１の最終保護用絶縁膜４中にボイド５が発
生し、コンタミネーションをトラップし、その結果、配
線の信頼性を低下させるという問題があった。また、第
１の最終保護用絶縁膜４であるシリコンナイトライド膜
は、膜応力が著しく大きく、Al配線３のストレスマイグ
レーションを増大させ、Al配線３を断線させるという問
題もあった。(Problems to be Solved by the Invention) In such a conventional method, the first final protective insulating film 4 on the Al wiring 3 becomes an overhang, and when the Al wiring interval becomes 1 μm or less, the upper portion of the overhang is formed. Since they are connected to each other, a void 5 is generated in the first final protective insulating film 4 to trap contamination, and as a result, the reliability of the wiring is lowered. Further, the silicon nitride film, which is the first final protective insulating film 4, has a remarkably large film stress, which increases the stress migration of the Al wiring 3 and causes a disconnection of the Al wiring 3.
本発明はこのような課題を解決するもので、Al配線３
上の最終保護用絶縁膜中でのボイドの発生を防止すると
共に、Al配線のストレスマイグレーションによる断線不
良を抑制できる半導体装置の製造方法を提供することを
目的とするものである。The present invention solves such a problem by using the Al wiring 3
It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of preventing the occurrence of voids in the final protective insulating film and suppressing the disconnection failure due to the stress migration of Al wiring.
（課題を解決するための手段） 本発明は上記目的を達成するために、半導体基板の絶
縁膜上に形成された［（ｔ−（C4H9O）2SiNH2］2NH（ビ
スジターシャリブトキシアミノシランイミド）を原料と
して、減圧下でプラズマCVD法または光CVD法により、シ
リコンオキシナイトライド膜を形成する工程を具備する
ものである。(Means for Solving the Problem) In order to achieve the above-mentioned object, the present invention is to form [(t- (C 4 H 9 O) 2 SiNH 2 ] 2 NH (bis-dither) formed on an insulating film of a semiconductor substrate. It is provided with a step of forming a silicon oxynitride film by a plasma CVD method or a photo CVD method under reduced pressure, using a raw material of (salibutoxyaminosilaneimide).
（作 用） したがって、本発明では、原料ガスとして、分子中に
アルコキシ基を有するビスジターシャリブトキシアミノ
シランイミドを用いているため、表面反応が支配的であ
り、TEOS（テトラエトキシシラン）と同様にAl配線上に
形成される最終保護用絶縁膜の段差被覆性は著しく向上
し、Al配線間隔が１μｍ以下となってもオーバーハング
を防止でき、その結果、最終保護用絶縁膜中でのボイド
の発生を抑制でき、またビスジターシャリブトキシアミ
ノシランイミドは、分子中にＯ−Si−Ｎ結合をもつため
最終保護用絶縁膜はシリコンオキシナイトライド膜とな
り膜応力を著しく低減でき、Al配線のストレスマイグレ
ーションによる断線不良を抑制できる。(Operation) Therefore, in the present invention, since the bisditertiarybutoxyaminosilane imide having an alkoxy group in the molecule is used as the source gas, the surface reaction is predominant, and similar to TEOS (tetraethoxysilane). The step coverage of the final protective insulating film formed on the Al wiring is significantly improved, and overhang can be prevented even when the Al wiring interval is 1 μm or less. As a result, voids in the final protective insulating film are prevented. The generation of bisditertiarybutoxyaminosilane imide has an O-Si-N bond in the molecule, so the final protective insulating film becomes a silicon oxynitride film, which can significantly reduce the film stress and stress migration of Al wiring. It is possible to suppress the disconnection failure due to.
（実施例） 第１図は本発明の一実施例における保護用絶縁膜形成
の構成断面を示した図である。第１図において、まず半
導体基板１の表面に絶縁膜２を形成した後、Al配線３を
形成する。次に、原料ガスとして、［（ｔ−（C4H9O）2
SiNH2］2NH（ビスジターシャリブトキシアミノシランイ
ミド）を用いて、プラズマCVD法により反応圧力10〜20T
orr、成長温度350〜400℃にて、屈折率が1.70〜1.80
で、膜の圧縮応力が３〜８×108dyne/cm2のシリコンオ
キシナイトライド膜を8000〜10000Å程度成長して、膜
中にボイドの発生しない第２の最終保護用絶縁膜６を形
成する。(Embodiment) FIG. 1 is a diagram showing a cross section of a structure for forming a protective insulating film in an embodiment of the present invention. In FIG. 1, first, the insulating film 2 is formed on the surface of the semiconductor substrate 1, and then the Al wiring 3 is formed. Next, [(t- (C 4 H 9 O) 2
SiNH 2 ] 2 NH (bisditertiarybutoxyaminosilane imide) is used and the reaction pressure is 10 to 20 T by plasma CVD method.
Refractive index of 1.70 to 1.80 at orr and growth temperature of 350 to 400 ℃
Then, a silicon oxynitride film having a film compressive stress of 3 to 8 × 10 8 dyne / cm 2 is grown to about 8000 to 10000Å to form a second final protective insulating film 6 in which no void is generated in the film. To do.
（発明の効果） 上記実施例より明らかなように、本発明によれば、Al
配線上に形成される最終保護用絶縁膜の段差被覆性は著
しく向上し、Al配線間隔が１μｍ以下となってもオーバ
ーハングを防止でき、その結果、最終保護用絶縁膜中で
のボイドの発生を抑制できるだけでなく、最終保護用絶
縁膜をシリコンオキシナイトライド膜とすることにより
膜応力を著しく低減でき、Al配線のストレスマイグレー
ションによる断線不良を抑制でき、配線の信頼性を著し
く向上させる効果が得られ、所望の特性の半導体装置を
提供することができる。(Effects of the Invention) As is clear from the above-described examples, according to the present invention, Al
The step coverage of the final protective insulating film formed on the wiring is significantly improved, and overhang can be prevented even when the Al wiring interval is 1 μm or less, and as a result, voids are generated in the final protective insulating film. In addition to suppressing the above, it is possible to significantly reduce the film stress by using a silicon oxynitride film as the final protective insulating film, suppress disconnection failure due to stress migration of Al wiring, and improve the reliability of wiring significantly. A semiconductor device having the desired characteristics can be provided.
第１図は本発明の一実施例における保護用絶縁膜形成の
構成断面図、第２図は従来例の保護用絶縁膜形成の構成
断面図である。 １……半導体基板、２……絶縁膜、３……Al配線、４…
…第１の最終保護用絶縁膜、５……ボイド、６……第２
の最終保護用絶縁膜。FIG. 1 is a sectional view showing the structure of forming a protective insulating film in one embodiment of the present invention, and FIG. 2 is a sectional view showing the structure of forming a conventional protective insulating film. 1 ... Semiconductor substrate, 2 ... Insulating film, 3 ... Al wiring, 4 ...
… First insulating film for final protection, 5 …… Void, 6 …… Second
Final protective insulating film.
Claims (1)
に、［（ｔ−（C4H9O）2SiNH2］2NH（ビスジターシャリ
ブトキシアミノシランイミド）を原料として、減圧下で
プラズマCVD法または光CVD法により、シリコンオキシナ
イトライド膜を形成する工程を具備することを特徴とす
る半導体装置の製造方法。1. A wiring formed on an insulating film of a semiconductor substrate, under reduced pressure, using [(t- (C 4 H 9 O) 2 SiNH 2 ] 2 NH (bisditertiary riboxyaminosilane imide) as a raw material. 2. A method of manufacturing a semiconductor device, comprising the step of forming a silicon oxynitride film by plasma CVD or photo CVD.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8569089A JPH0812845B2 (en) | 1989-04-06 | 1989-04-06 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8569089A JPH0812845B2 (en) | 1989-04-06 | 1989-04-06 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02265242A JPH02265242A (en) | 1990-10-30 |
| JPH0812845B2 true JPH0812845B2 (en) | 1996-02-07 |
Family
ID=13865840
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8569089A Expired - Fee Related JPH0812845B2 (en) | 1989-04-06 | 1989-04-06 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0812845B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2714960B1 (en) | 2011-06-03 | 2018-02-28 | Versum Materials US, LLC | Compositions and processes for depositing carbon-doped silicon-containing films |
| WO2018182318A1 (en) * | 2017-03-29 | 2018-10-04 | Dnf Co., Ltd. | Composition for depositing silicon-containing thin film and method for manufacturing silicon-containing thin film using the same |
-
1989
- 1989-04-06 JP JP8569089A patent/JPH0812845B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02265242A (en) | 1990-10-30 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |