JPS63232349A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63232349A JPS63232349A JP6715987A JP6715987A JPS63232349A JP S63232349 A JPS63232349 A JP S63232349A JP 6715987 A JP6715987 A JP 6715987A JP 6715987 A JP6715987 A JP 6715987A JP S63232349 A JPS63232349 A JP S63232349A
- Authority
- JP
- Japan
- Prior art keywords
- film
- groove
- etching
- polycrystalline silicon
- etched
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 238000005530 etching Methods 0.000 claims abstract description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 25
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 230000001681 protective effect Effects 0.000 claims abstract description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 19
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 238000001020 plasma etching Methods 0.000 claims description 2
- 238000000926 separation method Methods 0.000 abstract description 6
- 229910052681 coesite Inorganic materials 0.000 abstract description 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 3
- 229910052682 stishovite Inorganic materials 0.000 abstract description 3
- 229910052905 tridymite Inorganic materials 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 10
- 238000002955 isolation Methods 0.000 description 9
- 239000003795 chemical substances by application Substances 0.000 description 6
- 238000004380 ashing Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 239000011800 void material Substances 0.000 description 3
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910007277 Si3 N4 Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910005091 Si3N Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Landscapes
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
［概要コ
Ｕ溝の形成方法であって、半導体基板上に選択的に酸化
シリコン膜、窒化シリコン膜および保護絶縁膜（エツチ
ング保護マスク）を形成した後、Ｕ溝をエツチング形成
する。次いで、Ｕ溝側面の窒化シリコン膜をサイドエツ
チングし、保護絶縁膜を除去した後、前記Ｕ溝内部に酸
化シリコン膜を介して多結晶シリコン膜を埋没する。[Detailed Description of the Invention] [Summary] A method for forming a U-groove, in which a silicon oxide film, a silicon nitride film, and a protective insulating film (etching protection mask) are selectively formed on a semiconductor substrate, and then a U-groove is formed. Form by etching. Next, the silicon nitride film on the side surfaces of the U-groove is side-etched to remove the protective insulating film, and then a polycrystalline silicon film is buried inside the U-groove via a silicon oxide film.
そうすれは、多結晶シリコン膜をＵ溝内部に空隙なく成
長させることができる。In this way, a polycrystalline silicon film can be grown inside the U-groove without any voids.
［産業上の利用分野］
本発明はＩＣなど、半導体装置の製造方法に係り、特に
、素子分離のためのＵ溝形成方法に関する。[Industrial Field of Application] The present invention relates to a method of manufacturing semiconductor devices such as ICs, and particularly relates to a method of forming a U-groove for element isolation.
半導体装置の製造方法においては、ＩＣを高集積化する
目的で素子分離帯としてＵ溝分離（トレンチ分離； ｔ
ｒｅｎｃｈ ５ｅｐａｒａｔｉｏｎ ）が利用されてい
る。しかし、このようなＵ溝は狭隘な凹部を形成する方
法であるから、品質上の問題が生じないように、十分に
考慮した形成方法が望ましい。In the manufacturing method of semiconductor devices, U-groove isolation (trench isolation; t
rench 5eparation) is used. However, since such a U-groove is a method of forming a narrow concave portion, it is desirable that the formation method be carefully considered so as not to cause quality problems.
［従来の技術］
従前、素子分離帯としてｐｎ接合分離や絶縁膜分離が用
いられていたが、前者のｐｎ接合分離は拡散して形成す
るために、横方向に拡がりが起こって微細化することが
難しく、また、後者の絶縁膜分離はバーズビークの発生
で、同様に微細化が難しい。従って、最近、幅１〜２μ
ｍ程度に微細に形成できるＵ溝分離が重用されている。[Prior art] Previously, pn junction isolation and insulating film isolation were used as element isolation bands, but since the former pn junction isolation is formed by diffusion, it spreads laterally and becomes finer. In addition, the latter type of insulating film separation causes bird's beaks, making it similarly difficult to miniaturize. Therefore, recently, width 1~2μ
U-groove separation, which can be formed as finely as 100 m in diameter, is widely used.
さて、従来のＵ溝の形成方法を説明すると、第２図（ａ
ｌ〜（８）にその形成工程順断面図を示しており同図に
よって順を追って説明する。Now, to explain the conventional method of forming a U-groove, Fig. 2 (a)
1 to (8) are sequential cross-sectional views of the formation process, and the explanation will be given in sequence with reference to the figures.
第２図（ａ）参照；まず、シリコン基板１上に酸化シリ
：２７ （Ｓｉ０２）膜２（膜厚６０００人）を形成し
。Refer to FIG. 2(a); First, a silicon oxide:27 (Si02) film 2 (film thickness: 6,000 yen) is formed on a silicon substrate 1.
その上に窒化シリコン（Ｓｉａ Ｎ４ ）膜３（膜厚２
゜００人）を被着し、その上に燐シリケートガラス（Ｐ
ＳＧ）膜４（膜厚１．３．ｃｒｍ）を被着し、更に、そ
の上に選択的にレジスト膜マスク５を形成する。On top of that, a silicon nitride (Sia N4) film 3 (thickness 2
゜00 people) and phosphorus silicate glass (P
SG) film 4 (thickness: 1.3 crm) is deposited, and a resist film mask 5 is selectively formed thereon.
なお、ＳｉＯ□膜２が膜厚６０００人と厚いのは、これ
を素子内部のフィールド絶縁膜として利用するためで、
Ｕ溝を形成する前に形成されているもので、このような
Ｕ溝とフィールド絶縁膜とを組み合わせた構造をＵ−Ｆ
ＯＸ構造と呼んでいる・第２図（ｂ）参照；次いで、レ
ジスト膜マスク５を用いて、ＰＳＧ膜４． Ｓｉ３ Ｎ
４膜３および５ｉ０２膜２をパターンニングした後、塩
素系の反応ガスを用いたりアクティブイオンエツチング
（ＲＩ Ｂ）によってエツチングして、幅１．５μｍ、
深さ約３μｍのＵ溝６を形成する。この時、レジスト膜
マスク５は大部分が消耗して、ＰＳＧ膜４がエラ２
チング保護マスクとしての役目をする。また、この工程
でＰＳＧ膜４．Ｓｉ３Ｎ４膜３および５ｉ０２膜２をパ
ターンニングした後、レジスト膜マスク５を除去して、
ＰＳＧ膜４のみをエツチング保護マスクとしても良い。The reason why the SiO□ film 2 is 6,000 thick is because it is used as a field insulating film inside the device.
It is formed before forming the U-groove, and the structure that combines such a U-groove and field insulating film is called U-F.
This is called an OX structure (see FIG. 2(b)); then, using a resist film mask 5, a PSG film 4. Si3N
After patterning the 4 film 3 and the 5i02 film 2, they are etched using a chlorine-based reactive gas or by active ion etching (RIB) to form a pattern with a width of 1.5 μm.
A U-groove 6 with a depth of about 3 μm is formed. At this time, most of the resist film mask 5 has been consumed, and the PSG film 4 has an error 2.
Acts as a protective mask. Also, in this step, the PSG film 4. After patterning the Si3N4 film 3 and the 5i02 film 2, the resist film mask 5 is removed.
Only the PSG film 4 may be used as an etching protection mask.
第２図（Ｃ）参照；次いで、残存しているレジスト膜ヤ
スク５をアッシング（灰化）除去した後、弗酸系のエツ
チング剤によってＰＳＧ膜４をエツチング除去し、更に
、弗酸・硝酸系の強いエツチング剤によってＵ溝６の内
部を洗浄する。この工程において、Ｕ溝６の内部に露出
した５ｔ０２膜２側面にはサイドエツチングが起きる。Refer to FIG. 2(C); Next, after removing the remaining resist film yask 5 by ashing (ashing), the PSG film 4 is removed by etching with a hydrofluoric acid-based etching agent, and then The inside of the U groove 6 is cleaned with a strong etching agent. In this step, side etching occurs on the side surfaces of the 5t02 film 2 exposed inside the U-groove 6.
第２図（ｄ）参照；次いで、高温熱処理してＵ溝６の内
部を酸化して、５ｉ０２膜７（膜厚５００人）を生成し
た後、化学気相成長（ＣＶ Ｄ）法で多結晶シリコン膜
８を被着して、Ｕ溝６の内部を埋没させる。この時、多
結晶シリコン膜８はＵ溝の側面から成長して溝中央に進
み、かくして溝内部が埋没される。See FIG. 2(d); Next, the inside of the U-groove 6 is oxidized by high-temperature heat treatment to form a 5i02 film 7 (thickness: 500 mm), and then polycrystalline is formed by chemical vapor deposition (CVD). A silicon film 8 is deposited to bury the inside of the U-groove 6. At this time, the polycrystalline silicon film 8 grows from the side surfaces of the U-groove and advances to the center of the groove, thus filling the inside of the groove.
第２図（ｅ）参照；次いで、化学研磨法で多結晶シリコ
ン膜８を研磨して除去する。この場合、５ｉｙＮ４膜３
がエツチング阻止層の役目を果たすことになる。Refer to FIG. 2(e); next, the polycrystalline silicon film 8 is polished and removed using a chemical polishing method. In this case, 5iyN4 film 3
serves as an etching prevention layer.
しかる後、Ｓ３３ Ｎ４膜３をエツチング除去し、多結
晶シリコン膜８の表面を熱酸化して５ｉ０２膜（図示せ
ず）を生成して完了する。このようにして、５ｉ０２膜
７を介して多結晶シリコン膜８を埋没させたＵ溝分離帯
が形成される。なお、このようなＵ溝分離法は別名をＩ
ＯＰ （Ｉｓｏｌａｔｉｏｎ ｗｉｔｈＯｘｉｄｅ
ａｎｄ Ｐｏ１ｙｓｉｌｉｃｏｎ）法と呼んでいる。Thereafter, the S33N4 film 3 is removed by etching, and the surface of the polycrystalline silicon film 8 is thermally oxidized to form a 5i02 film (not shown). In this way, a U-groove isolation zone is formed in which the polycrystalline silicon film 8 is buried through the 5i02 film 7. Note that this U-groove separation method is also known as I
OP (Isolation with Oxide
and Polysilicon) method.
［発明が解決しようとする問題点］
ところが、上記のようなＵ溝分離帯の形成方法において
、弗酸系のエツチング剤によってＰＳＧ膜４をエツチン
グしたり、また、弗酸・硝酸系の強いエツチング剤によ
ってＵ溝内部を洗浄したりすると、Ｕ溝６の内部に露出
した５ｔ０２膜２がサイドエツチングされる（第２図（
Ｃ）参照）。[Problems to be Solved by the Invention] However, in the method for forming the U-groove separator as described above, the PSG film 4 is etched with a hydrofluoric acid-based etching agent, and the PSG film 4 is etched with a strong etching agent based on hydrofluoric acid or nitric acid. When the inside of the U-groove is cleaned with a chemical, the 5t02 film 2 exposed inside the U-groove 6 is side-etched (see FIG. 2).
See C).
そうすれば、Ｕ溝６内ではＳｉ３ Ｎ４膜がひさし状に
突き出して、下の５ｆ０２膜２の部分が横に拡がった形
状になり、そのような形状のＵ溝内部にＣＶＤ法で多結
晶シリコン膜８を成長して埋没させると、多結晶シリコ
ン膜はＵ溝の側面から成長するため、拡がった形状の５
ｉ０２膜２の部分に空隙が生じたまま、上面まで多結晶
シリコン膜によって埋没される。即ち、Ｕ溝の上部中央
に空隙ができた状態になる（第２図（ｄｌ参照）。従っ
て、次工程で上面の多結晶シリコン膜８を研磨して除去
すると、Ｕ溝の中央に空隙が表出して陥没部分ができ、
その部分を酸化して５ｉ０２膜を生成しても、その上面
に配線層を形成すると、配線層が断線する障害が起こる
。By doing so, the Si3 N4 film protrudes like an eaves inside the U-groove 6, and the lower 5f02 film 2 becomes shaped to spread laterally. When the film 8 is grown and buried, the polycrystalline silicon film grows from the sides of the U-groove, so the expanded shape 5
The i02 film 2 is filled with the polycrystalline silicon film up to its upper surface, leaving a void therein. In other words, a void is created in the center of the upper part of the U-groove (see Figure 2 (dl)).Therefore, when the polycrystalline silicon film 8 on the top surface is polished and removed in the next step, a void is created in the center of the U-groove. It comes out and creates a depressed area,
Even if a 5i02 film is produced by oxidizing that portion, if a wiring layer is formed on the top surface, a problem occurs in which the wiring layer is disconnected.
本発明は、このような多結晶シリコン膜の空隙を解消さ
せて、信頼性を高めるＵ溝の形成方法を提案するもので
ある。The present invention proposes a method for forming a U-groove that eliminates such voids in a polycrystalline silicon film and improves reliability.
［問題点を解決するための手段］
その目的は、半導体基板上に選択的に酸化シリコン膜と
窒化シリコン膜と保護絶縁膜からなる三層のエツチング
保護マスクとを形成して、前記シリコン基板をリアクテ
ィブイオンエツチングしてＵ溝を形成する工程、次いで
、Ｕ溝内の側面に露出した窒化シリコン膜をサイドエツ
チングし、更に、保護絶縁膜をエツチング除去した後、
前記Ｕ溝内部に酸化シリコン膜を介して多結晶シリコン
膜を埋没させる工程が含まれる半導体装置の製造方法に
よって達成される。[Means for Solving the Problems] The purpose is to selectively form a three-layer etching protection mask consisting of a silicon oxide film, a silicon nitride film, and a protective insulating film on a semiconductor substrate, and then remove the silicon substrate. After forming a U-groove by reactive ion etching, side-etching the silicon nitride film exposed on the side surfaces inside the U-groove, and removing the protective insulating film by etching,
This is achieved by a method for manufacturing a semiconductor device that includes a step of burying a polycrystalline silicon film inside the U-groove via a silicon oxide film.
［作用コ
即ち、本発明は、多結晶シリコン膜をＵ溝内部に被着す
る前に、Ｓｉ３Ｎ４膜をサイドエツチングして、ひさし
状のＳｉ３ Ｎ４ ’Ａ’Ｊ、をなくし、Ｕ溝の上面が
テーパー状に開いた形状にする。そうして、多結晶シリ
コン膜を成長すれば、Ｕ溝内部に多結晶シリコン膜を空
隙なく成長させることができ、ＩＣの信頼性が向上する
。[In other words, in the present invention, before depositing the polycrystalline silicon film inside the U-groove, the Si3N4 film is side-etched to eliminate the canopy-shaped Si3N4 'A'J, so that the top surface of the U-groove is Create a tapered open shape. If the polycrystalline silicon film is grown in this manner, the polycrystalline silicon film can be grown inside the U-groove without any voids, and the reliability of the IC is improved.
［実施例］ 以下、図面を参照して実施例によって詳細に説明する。[Example] Hereinafter, embodiments will be described in detail with reference to the drawings.
第１図（ａ）〜（ｅ）は本発明にかかるυ溝の形成方法
の工程順断面図を示している。FIGS. 1(a) to 1(e) show cross-sectional views in the order of steps of the method for forming a υ groove according to the present invention.
第１図（ａ）参照；従来の工程と同様に、シリコン基板
１１上に５ｉ０２膜１２（膜厚６０００人）およびＳｉ
３Ｎ４膜１３（膜厚２０００人）を積層被着し、その上
にＰＳＧ呻１４（膜厚１．３μｍ；保護絶縁膜）を被着
し、更に、その上に選択的にレジスト膜マスク１５を形
成して、次に、レジスト膜マスク１５によってＰＳＧ膜
１４． Ｓｉ３ Ｎ４膜１３および５ｉ０２膜１２をパ
ターンニングした後、塩素系の反応ガスを用いノ；ＲＩ
Ｅによってシリコン基板１１をエツチングして、幅１．
５μｍ、深さ３μｍ程度のＵ溝１６を形成する。See FIG. 1(a); similar to the conventional process, a 5i02 film 12 (thickness: 6000) and a Si
A 3N4 film 13 (thickness: 2000 layers) is deposited, a PSG film 14 (thickness: 1.3 μm; protective insulating film) is deposited thereon, and a resist film mask 15 is selectively deposited on top of it. Then, a PSG film 14. is formed using a resist film mask 15. After patterning the Si3N4 film 13 and the 5i02 film 12, RI is performed using a chlorine-based reactive gas.
Etching the silicon substrate 11 with E etching the width 1.
A U-groove 16 of approximately 5 μm and depth of 3 μm is formed.
なお、５ｉ０２膜２が厚いのは、Ｕ−ＦＯＸ構造にして
、Ｕ溝を形成する前に厚い５ｉ０２膜２を形成している
からである。The 5i02 film 2 is thick because it has a U-FOX structure and the thick 5i02 film 2 is formed before forming the U-groove.
第１図（ｂ）参照；次いで、若しレジスト膜マスク１５
が残存していれば、それをアッシング除去して、次に、
熱燐酸液に３０分間浸漬して、Ｕ溝内に露出したＳｉ３
Ｎ４膜１３をサイドエツチングする。そのエツチング量
は２０００〜３０００人程度にする。Refer to FIG. 1(b); Next, resist film mask 15
If remains, remove it by ashing and then
Immersed in hot phosphoric acid solution for 30 minutes to remove Si3 exposed in the U groove.
The N4 film 13 is side etched. The amount of etching will be approximately 2,000 to 3,000 people.
第ｔｍ（ｃ＋参照；次いで、弗酸系のエツチング剤によ
ってＰＳＧ膜１４をエツチング除去し、次に、弗酸・硝
酸系の強いエツチング剤によってＵ溝１６の内部を洗浄
する。この工程において、Ｕ溝１６側面に露出した５ｉ
０２膜１２はサイドエツチングが起こる。tm (see c+; next, the PSG film 14 is etched away using a hydrofluoric acid-based etching agent, and then the inside of the U groove 16 is cleaned using a strong hydrofluoric acid/nitric acid-based etching agent. 5i exposed on the side of groove 16
Side etching occurs in the 02 film 12.
第１図（ｄ）参照；次いで、高温熱処理してＵ溝６の内
部を酸化して、５ｉ０２膜１７（膜厚５００人）を生成
した後、ＣＶＤ法で多結晶シリコン膜１８を成長して、
Ｕ溝１６の内部を埋没させる。この場合、多結晶シリコ
ン膜１８は溝側面から成長して溝中央に進むが、前記工
程によってＳｉ３ Ｎ４膜１３をサイドエツチングして
いるために、上記工程によって５ｉ０２膜１２のサイド
エツチングが起こっても、Ｓｉ３Ｎ４膜がひさし状に突
き出すことなく、テーパー形状のＵ溝上部が形成される
。従って、多結晶シリコン膜は空隙を残すことなしに、
溝中央の凹部にも多結晶シリコン膜の成長が進み、最後
に多結晶シリコン膜１８の凹部が最上面に形成されて、
溝内部は完全に埋没される。Refer to FIG. 1(d); Next, the inside of the U-groove 6 is oxidized by high-temperature heat treatment to form a 5i02 film 17 (thickness: 500 mm), and then a polycrystalline silicon film 18 is grown by CVD. ,
The inside of the U groove 16 is buried. In this case, the polycrystalline silicon film 18 grows from the side surfaces of the trench and advances toward the center of the trench, but since the Si3N4 film 13 is side-etched in the above process, even if the 5i02 film 12 is side-etched in the above process, , the tapered upper part of the U-groove is formed without the Si3N4 film protruding like a canopy. Therefore, the polycrystalline silicon film can be formed without leaving any voids.
The growth of the polycrystalline silicon film also progresses in the recess at the center of the groove, and finally, the recess of the polycrystalline silicon film 18 is formed on the top surface.
The inside of the trench will be completely buried.
第２図（ｅｌ参照；次いで、多結晶シリコン膜１８を研
磨除去する。そうすれば、空隙がなく、密度の高い多結
晶シリコン膜がＵ溝内に充填される。2 (see el; next, the polycrystalline silicon film 18 is removed by polishing. Thereby, the U-groove is filled with a polycrystalline silicon film having no voids and high density.
しかる後、Ｓｉ３ Ｎ４膜３をエツチング除去し、表面
を酸化して５ｉ０２ｋ （図示せず）を生成して、Ｕ溝
分離帯が完成される。このような形成方法によれば、Ｕ
溝分離帯の表面は段差なく平坦化され、従って、その上
面に配線層を形成しても、断線のない信頼性の高い配線
が形成されて、ＩＣが高倍転化される。Thereafter, the Si3 N4 film 3 is removed by etching and the surface is oxidized to produce 5i02k (not shown) to complete the U-groove separation zone. According to such a forming method, U
The surface of the groove separation band is flattened without any difference in level, so even if a wiring layer is formed on the upper surface, highly reliable wiring without disconnection is formed, and the IC can be made to have a high conversion rate.
［発明の効果］
以上の説明から判るように、本発明にかかる形成方法に
よればＩＣの信頼性向上に顕著に貢献するものである。[Effects of the Invention] As can be seen from the above description, the forming method according to the present invention significantly contributes to improving the reliability of ICs.
第１図（ａ）〜（ｅｌは本発明にかかる形成方法の工程
順断面図、
第２図（ａ）〜Ｔｅ）は従来の形成方法の工程順断面図
である。
図において、
１．１１はシリコン基板、２，１２は５ｉ０２膜、３．
１３はＳｉ３Ｎ４膜、 ４，１４はＰＳＧ膜、５．１５
はレジスト膜マスク、
６．１６はＵ溝、 ７，１７は５ｉ０２膜、８
．１８は多結晶シリコン膜
第１図FIGS. 1A to 1E are step-by-step cross-sectional views of a forming method according to the present invention, and FIGS. 2A-Te are step-by-step cross-sectional views of a conventional forming method. In the figure, 1.11 is a silicon substrate, 2 and 12 are 5i02 films, and 3.
13 is Si3N4 film, 4, 14 is PSG film, 5.15
is a resist film mask, 6.16 is a U groove, 7 and 17 are 5i02 films, 8
．． 18 is a polycrystalline silicon film.
Claims (1)
膜と保護絶縁膜からなる三層のエッチング保護マスクと
を形成して、前記シリコン基板をリアクティブイオンエ
ッチングしてＵ溝を形成する工程、 次いで、Ｕ溝内の側面に露出した窒化シリコン膜をサイ
ドエッチングして、更に、保護絶縁膜をエッチング除去
した後、前記Ｕ溝内部に酸化シリコン膜を介して多結晶
シリコン膜を埋没させる工程が含まれてなることを特徴
とする半導体装置の製造方法。[Claims] A three-layer etching protection mask consisting of a silicon oxide film, a silicon nitride film, and a protective insulating film is selectively formed on a semiconductor substrate, and the silicon substrate is subjected to reactive ion etching to form a U-groove. Next, after side-etching the silicon nitride film exposed on the side surfaces in the U-groove and etching away the protective insulating film, a polycrystalline silicon film is formed inside the U-groove via a silicon oxide film. 1. A method for manufacturing a semiconductor device, comprising the step of burying a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6715987A JPS63232349A (en) | 1987-03-19 | 1987-03-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6715987A JPS63232349A (en) | 1987-03-19 | 1987-03-19 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63232349A true JPS63232349A (en) | 1988-09-28 |
Family
ID=13336835
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6715987A Pending JPS63232349A (en) | 1987-03-19 | 1987-03-19 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63232349A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6121113A (en) * | 1997-06-30 | 2000-09-19 | Fujitsu Limited | Method for production of semiconductor device |
| US6177331B1 (en) | 1997-06-04 | 2001-01-23 | Nec Corporation | Method for manufacturing semiconductor device |
-
1987
- 1987-03-19 JP JP6715987A patent/JPS63232349A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6177331B1 (en) | 1997-06-04 | 2001-01-23 | Nec Corporation | Method for manufacturing semiconductor device |
| US6121113A (en) * | 1997-06-30 | 2000-09-19 | Fujitsu Limited | Method for production of semiconductor device |
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