JPH08125338A - Circuit board for inner layer, and multilayer printed circuit board using the same circuit board - Google Patents

Circuit board for inner layer, and multilayer printed circuit board using the same circuit board

Info

Publication number
JPH08125338A
JPH08125338A JP26301894A JP26301894A JPH08125338A JP H08125338 A JPH08125338 A JP H08125338A JP 26301894 A JP26301894 A JP 26301894A JP 26301894 A JP26301894 A JP 26301894A JP H08125338 A JPH08125338 A JP H08125338A
Authority
JP
Japan
Prior art keywords
circuit board
inner layer
multilayer printed
layer
printed wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP26301894A
Other languages
Japanese (ja)
Inventor
Hiroaki Fujiwara
弘明 藤原
Shuji Maeda
修二 前田
Eiichiro Saito
英一郎 斉藤
Masayuki Ishihara
政行 石原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP26301894A priority Critical patent/JPH08125338A/en
Publication of JPH08125338A publication Critical patent/JPH08125338A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits

Landscapes

  • Structure Of Printed Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE: To provide a circuit board for an inner layer in which a crack due to thermal impact scarcely occurs at the insulating layer of a multilayer printed circuit board and the multilayer printed circuit board using the circuit board. CONSTITUTION: A circuit board for an inner layer comprises an insulating board layer 2, and a conductor circuit 3 formed by etching the surface of the layer 2, wherein the upper edge 3a of the circuit 3 is chamfered to form a curved surface. A multilayer printed circuit board comprises the circuit board for the inner layer, and an insulating layer 4 covered with the circuit 3 of the circuit board for the inner layer.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は内層用回路板、及びこの
内層用回路板を用いた多層のプリント配線板に関するも
のである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inner layer circuit board and a multilayer printed wiring board using the inner layer circuit board.

【0002】[0002]

【従来の技術】電子機器、電気機器に用いられるプリン
ト配線板は、近年、高密度化、小型化、薄型化が要求さ
れてきている。これらの要求に伴って、プリント配線板
に汎用されるガラス基材エポキシ樹脂絶縁基板を用いた
内層用回路板においても、例えば、導体回路にエポキシ
樹脂等の樹脂を塗布することにより絶縁層を形成する方
式(以下ビルドアップ方式と記す)が採用されている。
2. Description of the Related Art In recent years, printed wiring boards used in electronic equipment and electric equipment have been required to have higher density, smaller size and thinner thickness. In response to these demands, even in an inner layer circuit board using a glass-based epoxy resin insulating substrate that is commonly used for printed wiring boards, for example, an insulating layer is formed by applying a resin such as epoxy resin to a conductor circuit. The method (hereinafter referred to as the build-up method) is adopted.

【0003】[0003]

【発明が解決しようとする課題】上記方式で絶縁層を形
成した多層のプリント配線板は、この絶縁層にガラス基
材に樹脂を含浸したプリプレグを用いないため、絶縁層
の厚さを数10μm程度の薄さに形成できるため、薄型
化には適しているが、吸湿や半田等の熱衝撃を繰り返し
受けるとクラックが入り、耐電圧や吸湿による絶縁性の
低下が起こるので、多層のプリント配線板として十分な
信頼性を得ることが困難である。
A multilayer printed wiring board having an insulating layer formed by the above method does not use a prepreg in which a glass base material is impregnated with a resin, so that the insulating layer has a thickness of several tens of μm. Since it can be formed to a thin thickness, it is suitable for thinning, but cracks occur when moisture absorption or thermal shock such as solder is repeatedly applied, resulting in deterioration of insulation due to withstand voltage and moisture absorption. It is difficult to obtain sufficient reliability as a plate.

【0004】上記内層用回路板の要部断面を図2(a)
に示し、この内層用回路板を用いた多層のプリント配線
板の要部断面を図2(b)に示す。図2(a)に示す如
く、内層用回路板11の絶縁基板層12の表面に形成さ
れた導体回路13の断面は、オーバーエッチングによ
り、弓形にくびれ15を有している。そのため、導体回
路13の上端縁13aは鋭角に尖っている。図2(b)
に示す如く、このような状態の内層用回路板11を用い
て樹脂を塗布することにより絶縁層14を形成すると、
上記導体回路13の上端縁13aと接した絶縁層14に
クラック16が生じ易い。このクラックが時間が経過す
るに伴って、薄い絶縁層14の表面に達する。上記絶縁
層14が薄い多層のプリント配線板で耐電圧や吸湿によ
る絶縁性の低下が起こるのは、このクラックから吸湿に
よりマイブレーションが起き易いためと推測される。
FIG. 2 (a) is a sectional view of the main part of the inner layer circuit board.
FIG. 2B shows a cross section of the main part of a multilayer printed wiring board using this inner layer circuit board. As shown in FIG. 2A, the cross section of the conductor circuit 13 formed on the surface of the insulating substrate layer 12 of the inner layer circuit board 11 has an arcuate constriction 15 due to overetching. Therefore, the upper edge 13a of the conductor circuit 13 is sharply sharpened. Figure 2 (b)
As shown in, when the insulating layer 14 is formed by applying a resin using the inner layer circuit board 11 in such a state,
Cracks 16 are likely to occur in the insulating layer 14 in contact with the upper edge 13a of the conductor circuit 13. This crack reaches the surface of the thin insulating layer 14 as time passes. The reason why the insulation property is deteriorated due to the withstand voltage and moisture absorption in a multilayer printed wiring board having a thin insulating layer 14 is presumed to be that migration easily occurs due to moisture absorption from the cracks.

【0005】本発明は上記事実に鑑みてなされたもの
で、その目的とするところは、多層プリント配線板の絶
縁層に熱衝撃によるクラックの起きにくい内層用回路
板、及び、この内層用回路板を用いた多層のプリント配
線板を提供することにある。
The present invention has been made in view of the above facts, and an object of the present invention is to provide an inner-layer circuit board in which cracks due to thermal shock do not easily occur in an insulating layer of a multilayer printed wiring board, and the inner-layer circuit board. It is to provide a multilayer printed wiring board using.

【0006】[0006]

【課題を解決するための手段】本発明の請求項1に係る
内層用回路板は、絶縁基板層2と、この絶縁基板層2の
表面にエッチング形成された導体回路3を備えた内層用
回路板であって、上記導体回路3の上端縁3aが面取り
され、曲面を形成していることを特徴とする。
An inner layer circuit board according to claim 1 of the present invention is an inner layer circuit comprising an insulating substrate layer 2 and a conductor circuit 3 formed by etching on the surface of the insulating substrate layer 2. The plate is characterized in that the upper end edge 3a of the conductor circuit 3 is chamfered to form a curved surface.

【0007】本発明の請求項2に係る内層用回路板は、
請求項1記載の内層用回路板において、上記導体回路3
の上端縁3aが曲率半径10μm以上の曲面を形成して
いることを特徴とする。
An inner layer circuit board according to claim 2 of the present invention is
The inner layer circuit board according to claim 1, wherein the conductor circuit 3 is provided.
Is characterized in that the upper edge 3a thereof forms a curved surface having a radius of curvature of 10 μm or more.

【0008】本発明の請求項3に係る多層のプリント配
線板は、請求項1又は請求項2記載の内層用回路板、及
び、この内層用回路板の導体回路3を被覆した絶縁層4
からなることを特徴とする。
A multilayer printed wiring board according to claim 3 of the present invention is an inner layer circuit board according to claim 1 or 2, and an insulating layer 4 covering the conductor circuit 3 of the inner layer circuit board.
It is characterized by consisting of.

【0009】以下、本発明を図面に基づいて説明する。
図1(a)は本発明の一実施例に係る内層用回路板の要
部断面図であり、(b)は本発明の一実施例に係る多層
のプリント配線板の要部断面図である。
The present invention will be described below with reference to the drawings.
FIG. 1A is a cross-sectional view of an essential part of an inner layer circuit board according to an embodiment of the present invention, and FIG. 1B is a cross-sectional view of an essential part of a multilayer printed wiring board according to an embodiment of the present invention. .

【0010】図1(a)に示す如く、本発明の内層用回
路板は、絶縁基板層2と、この絶縁基板層2の表面に導
体回路3が形成されている。上記導体回路3は多層のプ
リント配線板の内層回路として用いられる。上記絶縁基
板層2は、基材に樹脂を含浸して得られるプリプレグの
樹脂を硬化させた基板である。上記樹脂としてはエポキ
シ樹脂、ポリイミド樹脂、フッ素樹脂、フェノール樹
脂、PPO樹脂等の単独、変性物、混合物等が挙げられ
る。上記基材としては、特に限定しないが、ガラス繊維
等の無機材料の方が耐熱性、耐湿性に優れて好ましい。
また、耐熱性に優れる有機繊維布基材及びこれらの混合
物を用いることもできる。上記導体回路3は、上記絶縁
基板層1の表面に配設された銅等の金属箔をエッチング
することにより形成される。
As shown in FIG. 1A, in the circuit board for an inner layer of the present invention, an insulating substrate layer 2 and a conductor circuit 3 are formed on the surface of the insulating substrate layer 2. The conductor circuit 3 is used as an inner layer circuit of a multilayer printed wiring board. The insulating substrate layer 2 is a substrate obtained by curing a resin of a prepreg obtained by impregnating a base material with a resin. Examples of the resin include epoxy resins, polyimide resins, fluororesins, phenol resins, PPO resins, and the like alone, modified products, and mixtures. The base material is not particularly limited, but an inorganic material such as glass fiber is preferable because it is superior in heat resistance and moisture resistance.
Further, an organic fiber cloth base material having excellent heat resistance and a mixture thereof can also be used. The conductor circuit 3 is formed by etching a metal foil such as copper provided on the surface of the insulating substrate layer 1.

【0011】上記エッチング形成した導体回路3は上端
縁3aが面取りされ、曲面を形成している。上記面取り
は、導体回路3をエッチング形成した後に行われる。上
記導体回路3の上端縁3aを面取りする方法は、例え
ば、バフ研磨やスクラブ研磨等の機械的に研磨する方
法、及び、ソフトエッチング等により化学的に処理する
方法がある。上記導体回路3の上端縁3aに形成した曲
面の丸みは曲率半径(R)が10μm以上であることが
望ましい。上記曲面の丸みが曲率半径(R)10μm以
上であると、多層のプリント配線板に用いた際に後述す
る絶縁層にクラックを生じにくい。
The upper edge 3a of the conductor circuit 3 formed by etching is chamfered to form a curved surface. The chamfering is performed after the conductor circuit 3 is formed by etching. Examples of methods for chamfering the upper edge 3a of the conductor circuit 3 include mechanical polishing methods such as buff polishing and scrub polishing, and chemical treatment methods such as soft etching. The radius of curvature (R) of the roundness of the curved surface formed on the upper edge 3a of the conductor circuit 3 is preferably 10 μm or more. When the radius of curvature of the curved surface (R) is 10 μm or more, cracks are less likely to occur in the insulating layer described below when used in a multilayer printed wiring board.

【0012】図1(b)に示す如く、本発明の多層のプ
リント配線板は、上記内層用回路板1と、この内層用回
路板1の導体回路3を被覆した絶縁層4を備える。上記
絶縁層4は樹脂が硬化した層である。上記樹脂として
は、絶縁基板層4を構成する樹脂が挙げられ、絶縁基板
層4と同一の樹脂でも異なる樹脂でもよいが、同一の樹
脂の方が寸法挙動が同じ点で好ましい。なかでも、エポ
キシ樹脂を用いた場合に耐電圧や吸湿による絶縁性の低
下防止の効果が顕著に表れる。
As shown in FIG. 1B, the multilayer printed wiring board of the present invention comprises the inner layer circuit board 1 and an insulating layer 4 covering the conductor circuit 3 of the inner layer circuit board 1. The insulating layer 4 is a resin cured layer. Examples of the resin include the resin forming the insulating substrate layer 4, and may be the same resin as the insulating substrate layer 4 or different resins, but the same resin is preferable in terms of the same dimensional behavior. Among them, when an epoxy resin is used, the effect of preventing a decrease in insulation due to withstand voltage or moisture absorption is remarkably exhibited.

【0013】上記絶縁層4は上記導体回路3に樹脂を塗
布し、この塗布した樹脂を硬化することにより形成して
もよいし、基材に樹脂を含浸したプリプレグの樹脂を硬
化して形成してもよい。樹脂を塗布するビルドアップ方
式の方が、絶縁層4の厚さを数10μm程度の薄さに形
成できるため、薄型化には好ましい。
The insulating layer 4 may be formed by applying a resin to the conductor circuit 3 and curing the applied resin, or may be formed by curing a resin of a prepreg in which a base material is impregnated with the resin. May be. The build-up method in which a resin is applied is preferable for thinning because the thickness of the insulating layer 4 can be formed to be as thin as several tens of μm.

【0014】上記多層のプリント配線板は、サブトクラ
ティブ、アディティブ等を用いて絶縁層4上に外層導体
回路5が形成されている。さらに、必要によりスルホー
ルメッキが施され、スルホールに導電路(図示せず)が
形成される。
In the above-mentioned multilayer printed wiring board, the outer conductor circuit 5 is formed on the insulating layer 4 by using subtocratic, additive or the like. Further, if necessary, through-hole plating is applied to form conductive paths (not shown) in the through-holes.

【0015】上述の如く、本発明の多層のプリント配線
板は、導体回路3の上端縁3aが面取りされ、曲面を形
成した内層用回路板1を用いるので、上記導体回路3の
上端縁3aと接する絶縁層4にクラックが発生するのを
抑える。従って、クラックから吸湿によりマイブレーシ
ョンが起こることがない。その結果、熱衝撃を繰り返し
受けても耐電圧や吸湿による絶縁性の低下が起こらな
い。
As described above, the multilayer printed wiring board of the present invention uses the inner layer circuit board 1 in which the upper end edge 3a of the conductor circuit 3 is chamfered to form a curved surface. The generation of cracks in the contacting insulating layer 4 is suppressed. Therefore, no migration occurs due to moisture absorption from the cracks. As a result, even if it is repeatedly subjected to thermal shock, the dielectric strength does not deteriorate due to withstand voltage and moisture absorption.

【0016】[0016]

【作用】本発明の請求項1又は請求項2に係る内層用回
路板は、導体回路3の上端縁3aが、面取りされた曲面
を形成しているので、多層のプリント配線板に用いた際
に導体回路3の上端縁3aと接する絶縁層4にクラック
を生じさせない。
In the inner layer circuit board according to the first or second aspect of the present invention, since the upper edge 3a of the conductor circuit 3 forms a chamfered curved surface, when used for a multilayer printed wiring board. In addition, no crack is generated in the insulating layer 4 in contact with the upper edge 3a of the conductor circuit 3.

【0017】本発明の請求項3に係る多層のプリント配
線板は、上記内層用回路板1と、この内層用回路板1の
導体回路3を被覆した絶縁層4を有しているので、絶縁
層4にクラックが発生しにくく、従って、クラックから
吸湿によりマイブレーションが起こることがない。
Since the multilayer printed wiring board according to claim 3 of the present invention has the inner-layer circuit board 1 and the insulating layer 4 covering the conductor circuit 3 of the inner-layer circuit board 1, it is insulated. Cracks are unlikely to occur in the layer 4, and therefore, no migration occurs due to moisture absorption from the cracks.

【0018】[0018]

【実施例】【Example】

実施例1 内層用回路板として、35μm厚さの銅箔を両面に配設
した厚み1.6mmのガラス布基材エポキシ樹脂積層板
を用い、ランド径1.0mm、導体回路幅0.2mm、
ランドの中心間隔2.54mmピッチで格子状の導体回
路をエッチングにより作製した。ランドは200個作製
した。
Example 1 As a circuit board for the inner layer, a glass cloth base material epoxy resin laminated board having a thickness of 1.6 mm, in which a copper foil having a thickness of 35 μm is arranged on both sides, a land diameter of 1.0 mm, a conductor circuit width of 0.2 mm,
Lattice-shaped conductor circuits were produced by etching with a land center interval of 2.54 mm pitch. 200 lands were produced.

【0019】次に、粗さ#600のバフを用いて導体回
路のバフ研磨を行った。得られた内層用回路板の断面を
光学顕微鏡で観察し、導体回路の上端縁の曲面の曲率半
径(R)を測定したところ、曲率半径(R)は30μm
であった。上記内層用回路板の導体回路が形成された両
面に、エポキシ樹脂を塗布し、厚さ80μmの絶縁層を
形成し、多層のプリント配線板とした。
Next, buffing of the conductor circuit was performed using a buff having a roughness of # 600. The cross section of the obtained inner layer circuit board was observed with an optical microscope, and the radius of curvature (R) of the curved surface of the upper edge of the conductor circuit was measured. The radius of curvature (R) was 30 μm.
Met. Epoxy resin was applied to both surfaces of the inner-layer circuit board on which the conductor circuits were formed to form an insulating layer having a thickness of 80 μm to obtain a multilayer printed wiring board.

【0020】得られた多層のプリント配線板の熱衝撃に
よるクラックが発生するまでの時間を評価した。この評
価試験はJIS−C−5012の熱衝撃に準じて行っ
た。温度260℃のオイルに10秒、温度20の水に1
0秒、温度20℃の有機溶剤に10秒の順に浸漬し、こ
れを1サイクルとする熱衝撃試験を行った。この多層プ
リント配線板の絶縁層にクラックが発生する迄のサイク
ルを測定した。クラックの測定は、クラックの個所で屈
折率が変化し白くみえるので、絶縁層に白化現象が発生
した個所が有るかどうかで判定した。結果は表1に示す
とおり、クラック発生まで70サイクルを要した。
The time until cracks due to thermal shock were generated in the obtained multilayer printed wiring board was evaluated. This evaluation test was performed according to the thermal shock of JIS-C-5012. 10 seconds for oil at a temperature of 260 ° C, 1 for water at a temperature of 20
A thermal shock test was conducted by immersing the solution in an organic solvent having a temperature of 20 ° C. for 0 second in the order of 10 seconds, and setting this as one cycle. The cycle until a crack was generated in the insulating layer of this multilayer printed wiring board was measured. In the crack measurement, the refractive index changed at the location of the crack so that it looked white. Therefore, it was judged whether there was a location where the whitening phenomenon occurred in the insulating layer. As shown in Table 1, the results required 70 cycles until crack initiation.

【0021】実施例2 粗さ#1000のバフを用いてバフ研磨を行った以外は
実施例1と同様にして多層のプリント配線板を作製し
た。内層用回路板の導体回路の上端縁の曲率半径(R)
は10μmであった。次に、実施例1と同様にして、ク
ラックが発生するまでの時間を測定した。結果は表1に
示すとおり、クラック発生まで65サイクルを要した。
Example 2 A multilayer printed wiring board was produced in the same manner as in Example 1 except that buffing was performed using a buff having a roughness of # 1000. Curvature radius (R) of the upper edge of the conductor circuit of the inner layer circuit board
Was 10 μm. Next, in the same manner as in Example 1, the time until the occurrence of cracks was measured. As the result is shown in Table 1, it took 65 cycles until a crack was generated.

【0022】実施例3 実施例1のバフ研磨に代えて、スクラブ研磨機(CIB
A−GEIGY社製:probimer−120)を用
いて1分間、スクラブ研磨を行った以外は実施例1と同
様にして多層のプリント配線板を作製した。内層用回路
板の導体回路の上端縁の曲率半径(R)は25μmであ
った。次に、実施例1と同様にして、クラックが発生す
るまでの時間を測定した。結果は表1に示すとおり、ク
ラック発生まで66サイクルを要した。
Example 3 Instead of the buffing in Example 1, a scrubbing machine (CIB) was used.
A multilayer printed wiring board was prepared in the same manner as in Example 1 except that scrubbing was performed for 1 minute using A-GEIGY Co .: producer-120). The radius of curvature (R) of the upper edge of the conductor circuit of the inner layer circuit board was 25 μm. Next, in the same manner as in Example 1, the time until the occurrence of cracks was measured. As shown in Table 1, 66 cycles were required until cracks were generated.

【0023】実施例4 実施例3のスクラブ研磨時間を3分間行った以外は実施
例3と同様にして多層のプリント配線板を作製した。内
層用回路板の導体回路の上端縁の曲率半径(R)は40
μmであった。次に、実施例1と同様にして、クラック
が発生するまでの時間を測定した。結果は表1に示すと
おり、クラック発生まで75サイクルを要した。
Example 4 A multilayer printed wiring board was prepared in the same manner as in Example 3 except that the scrubbing time in Example 3 was 3 minutes. The radius of curvature (R) of the upper edge of the conductor circuit of the inner layer circuit board is 40.
μm. Next, in the same manner as in Example 1, the time until the occurrence of cracks was measured. As shown in Table 1, it took 75 cycles until cracks occurred.

【0024】実施例5 実施例1のバフ研磨に代えて、ソフトエッチング液を用
いて2分間、ソフトエッチングを行った以外は実施例1
と同様にして多層のプリント配線板を作製した。上記ソ
フトエッチング液は、塩化第二銅(CuCl2 )が30
g/リットル、塩酸(HCl)が3.0モル/リットル
の割合で配合した、液温40℃のものを用いた。内層用
回路板の導体回路の上端縁の曲率半径(R)は50μm
であった。次に、実施例1と同様にして、クラックが発
生するまでの時間を測定した。結果は表1に示すとお
り、クラック発生まで79サイクルを要した。
Example 5 Example 1 was repeated except that the buffing in Example 1 was replaced by soft etching using a soft etching solution for 2 minutes.
A multilayer printed wiring board was produced in the same manner as in. The above soft etching solution contains 30 parts of cupric chloride (CuCl 2 ).
A liquid having a liquid temperature of 40 ° C. was used in which g / l and hydrochloric acid (HCl) were mixed at a ratio of 3.0 mol / l. The radius of curvature (R) of the upper edge of the conductor circuit of the inner layer circuit board is 50 μm
Met. Next, in the same manner as in Example 1, the time until the occurrence of cracks was measured. As the result is shown in Table 1, 79 cycles were required until crack initiation.

【0025】実施例6 実施例5のソフトエッチング時間を4分間行った以外は
実施例5と同様にして多層のプリント配線板を作製し
た。内層用回路板の導体回路の上端縁の曲率半径(R)
は35μmであった。次に、実施例5と同様にして、ク
ラックが発生するまでの時間を測定した。結果は表1に
示すとおり、クラック発生まで71サイクルを要した。
Example 6 A multilayer printed wiring board was produced in the same manner as in Example 5 except that the soft etching time in Example 5 was 4 minutes. Curvature radius (R) of the upper edge of the conductor circuit of the inner layer circuit board
Was 35 μm. Next, in the same manner as in Example 5, the time until the occurrence of cracks was measured. As shown in Table 1, the results required 71 cycles until crack initiation.

【0026】比較例1 実施例1と同様に内層用回路板の導体回路をエッチング
により作製した。得られた内層用回路板の断面を光学顕
微鏡で観察したところ、導体回路の上端縁は鋭角に尖っ
ていた。この内層用回路板を用い、実施例1と同様に、
厚さ80μmの絶縁層を形成し、多層のプリント配線板
を作製した。次に、実施例1と同様にして、クラックが
発生するまでの時間を測定した。結果は表1に示すとお
り、55サイクルでクラックが発生した。
Comparative Example 1 In the same manner as in Example 1, a conductor circuit of an inner layer circuit board was produced by etching. When the cross section of the obtained inner layer circuit board was observed with an optical microscope, the upper edge of the conductor circuit was sharply pointed. Using this inner layer circuit board, as in Example 1,
An insulating layer having a thickness of 80 μm was formed to produce a multilayer printed wiring board. Next, in the same manner as in Example 1, the time until the occurrence of cracks was measured. As shown in Table 1, the results showed that cracks occurred in 55 cycles.

【0027】[0027]

【表1】 [Table 1]

【0028】実施例7 実施例1と同様に内層用回路板の導体回路をエッチング
により作製した。その後、粗さ#600のバフを用いて
バフ研磨を行った。得られた内層用回路板の導体回路の
上端縁の曲率半径(R)は30μmであった。
Example 7 In the same manner as in Example 1, a conductor circuit of the inner layer circuit board was produced by etching. Then, buffing was performed using a buff having a roughness of # 600. The radius of curvature (R) of the upper edge of the conductor circuit of the obtained inner layer circuit board was 30 μm.

【0029】次に、上記内層用回路板の導体回路を形成
した両面に、厚さ0.1mmのガラス布にエポキシ樹脂
を含浸したプリプレグを1枚配設し、加熱加圧して厚さ
110μmの絶縁層を形成し、多層のプリント配線板と
した。次に、実施例1と同様にして、クラックが発生す
るまでの時間を測定した。結果は表2に示すとおり、ク
ラックが発生するまで80サイクルを要した。
Next, one prepreg in which a glass cloth having a thickness of 0.1 mm is impregnated with an epoxy resin is arranged on both surfaces of the inner-layer circuit board on which the conductor circuit is formed, and heated and pressed to have a thickness of 110 μm. An insulating layer was formed to obtain a multilayer printed wiring board. Next, in the same manner as in Example 1, the time until the occurrence of cracks was measured. As shown in Table 2, the results required 80 cycles until cracks occurred.

【0030】実施例8 実施例7のバフ研磨に代えて、スクラブ研磨機(CIB
A−GEIGY社製:probimer−120)を用
いて1分間、スクラブ研磨を行った以外は実施例7と同
様にして多層のプリント配線板を作製した。内層用回路
板の導体回路の上端縁の曲率半径(R)は25μmであ
った。次に、実施例7と同様にして、クラックが発生す
るまでの時間を測定した。結果は表2に示すとおり、ク
ラックが発生するまで77サイクルを要した。
Example 8 Instead of the buffing of Example 7, a scrubbing machine (CIB) was used.
A multilayer printed wiring board was produced in the same manner as in Example 7 except that scrubbing was performed for 1 minute using A-GEIGY Co .: producer-120). The radius of curvature (R) of the upper edge of the conductor circuit of the inner layer circuit board was 25 μm. Next, in the same manner as in Example 7, the time until the occurrence of cracks was measured. As shown in Table 2, 77 cycles were required until cracks occurred.

【0031】実施例9 実施例7のバフ研磨に代えて、実施例5のソフトエッチ
ング液を用いて2分間、ソフトエッチングを行った以外
は実施例7と同様にして多層のプリント配線板を作製し
た。内層用回路板の導体回路の上端縁の曲率半径(R)
は50μmであった。次に、実施例7と同様にして、ク
ラックが発生するまでの時間を測定した。結果は表2に
示すとおり、クラックが発生するまで90サイクルを要
した。
Example 9 A multilayer printed wiring board was prepared in the same manner as in Example 7, except that the soft etching solution of Example 5 was used for soft etching for 2 minutes instead of the buffing of Example 7. did. Curvature radius (R) of the upper edge of the conductor circuit of the inner layer circuit board
Was 50 μm. Next, in the same manner as in Example 7, the time until the occurrence of cracks was measured. As shown in Table 2, it took 90 cycles for cracks to occur.

【0032】比較例2 実施例7と同様に内層用回路板の導体回路をエッチング
により作製した。得られた内層用回路板の断面を光学顕
微鏡で観察したところ、導体回路の上端縁は鋭角に尖っ
ていた。この内層用回路板を用い、実施例7と同様に、
厚さ110μmの絶縁層を形成し、多層のプリント配線
板とした。次に、実施例7と同様にして、クラックが発
生するまでの時間を測定した。結果は表2に示すとお
り、65サイクルでクラックが発生した。
Comparative Example 2 In the same manner as in Example 7, a conductor circuit of the inner layer circuit board was produced by etching. When the cross section of the obtained inner layer circuit board was observed with an optical microscope, the upper edge of the conductor circuit was sharply pointed. Using this inner layer circuit board, as in Example 7,
An insulating layer having a thickness of 110 μm was formed to obtain a multilayer printed wiring board. Next, in the same manner as in Example 7, the time until the occurrence of cracks was measured. As shown in Table 2, the results showed that cracks occurred in 65 cycles.

【0033】[0033]

【表2】 [Table 2]

【0034】[0034]

【発明の効果】本発明の請求項1又は請求項2に係る内
層用回路板は、導体回路3の上端縁3aが、面取りされ
た曲面を形成しているので、多層のプリント配線板に用
いた際に導体回路3の上端縁3aと接する絶縁層4にク
ラックを生じさせない。その結果、熱衝撃を繰り返し受
けても耐電圧や吸湿による絶縁性の低下が起こらない。
The inner layer circuit board according to claim 1 or 2 of the present invention is used for a multilayer printed wiring board because the upper edge 3a of the conductor circuit 3 forms a chamfered curved surface. In this case, the insulating layer 4 in contact with the upper edge 3a of the conductor circuit 3 is not cracked. As a result, even if it is repeatedly subjected to thermal shock, the dielectric strength does not deteriorate due to withstand voltage and moisture absorption.

【0035】本発明の請求項3に係る多層のプリント配
線板は、上記内層用回路板1と、この内層用回路板1の
導体回路3を被覆した絶縁層4を有しているので、絶縁
層4にクラックが発生しにくく、吸湿や半田等の熱衝撃
を繰り返し受けても耐電圧や吸湿による絶縁性の低下が
起こりにくい。その結果、多層のプリント配線板とし
て、高い信頼性を得ることができる。なかでも、薄い絶
縁層4を有する多層のプリント配線板に、特に有効であ
る。
Since the multilayer printed wiring board according to claim 3 of the present invention has the inner-layer circuit board 1 and the insulating layer 4 covering the conductor circuit 3 of the inner-layer circuit board 1, it is insulated. The layer 4 is unlikely to be cracked, and even if it is repeatedly subjected to moisture absorption or thermal shock such as soldering, the withstand voltage and the insulation property are less likely to be deteriorated due to moisture absorption. As a result, high reliability can be obtained as a multilayer printed wiring board. Above all, it is particularly effective for a multilayer printed wiring board having a thin insulating layer 4.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a)は本発明の一実施例に係る内層用回路板
の要部断面図であり、(b)は本発明の一実施例に係る
多層のプリント配線板の要部断面図である。
FIG. 1A is a cross-sectional view of an essential part of an inner layer circuit board according to an embodiment of the present invention, and FIG. 1B is a cross-sectional view of an essential part of a multilayer printed wiring board according to an embodiment of the present invention. Is.

【図2】(a)は従来の内層用回路板の要部断面図であ
り、(b)は従来の多層のプリント配線板の要部断面図
である。
FIG. 2A is a cross-sectional view of a main part of a conventional circuit board for inner layer, and FIG. 2B is a cross-sectional view of a main part of a conventional multilayer printed wiring board.

【符号の説明】[Explanation of symbols]

1 内層用回路板 2 絶縁基板層 3 導体回路 3a 上端縁 4 絶縁層 1 inner layer circuit board 2 insulating substrate layer 3 conductor circuit 3a upper edge 4 insulating layer

フロントページの続き (72)発明者 石原 政行 大阪府門真市大字門真1048番地松下電工株 式会社内Front page continuation (72) Inventor Masayuki Ishihara 1048 Kadoma, Kadoma-shi, Osaka Matsushita Electric Works Co., Ltd.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 絶縁基板層(2)と、この絶縁基板層
(2)の表面にエッチング形成された導体回路(3)を
備えた内層用回路板であって、上記導体回路(3)の上
端縁(3a)が面取りされ、曲面を形成していることを
特徴とする内層用回路板。
1. An inner-layer circuit board comprising an insulating substrate layer (2) and a conductor circuit (3) formed by etching on the surface of the insulating substrate layer (2), said conductor circuit (3) comprising: An inner-layer circuit board, wherein the upper edge (3a) is chamfered to form a curved surface.
【請求項2】 上記導体回路(3)の上端縁(3a)が
曲率半径10μm以上の曲面を形成していることを特徴
とする請求項1記載の内層用回路板。
2. The inner-layer circuit board according to claim 1, wherein the upper edge (3a) of the conductor circuit (3) forms a curved surface with a radius of curvature of 10 μm or more.
【請求項3】 請求項1又は請求項2記載の内層用回路
板、及び、この内層用回路板の導体回路(3)を被覆し
た絶縁層(4)からなることを特徴とする多層のプリン
ト配線板。
3. A multi-layered print comprising an inner layer circuit board according to claim 1 or 2, and an insulating layer (4) covering a conductor circuit (3) of the inner layer circuit board. Wiring board.
JP26301894A 1994-10-27 1994-10-27 Circuit board for inner layer, and multilayer printed circuit board using the same circuit board Withdrawn JPH08125338A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26301894A JPH08125338A (en) 1994-10-27 1994-10-27 Circuit board for inner layer, and multilayer printed circuit board using the same circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26301894A JPH08125338A (en) 1994-10-27 1994-10-27 Circuit board for inner layer, and multilayer printed circuit board using the same circuit board

Publications (1)

Publication Number Publication Date
JPH08125338A true JPH08125338A (en) 1996-05-17

Family

ID=17383746

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26301894A Withdrawn JPH08125338A (en) 1994-10-27 1994-10-27 Circuit board for inner layer, and multilayer printed circuit board using the same circuit board

Country Status (1)

Country Link
JP (1) JPH08125338A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008098406A (en) * 2006-10-12 2008-04-24 Furukawa Electric Co Ltd:The Method for manufacturing printed circuit board
JP2013191711A (en) * 2012-03-13 2013-09-26 Sumitomo Metal Mining Co Ltd Three-dimensional circuit board, method of manufacturing film-like circuit board, and method of manufacturing three-dimensional circuit board using the same
CN114765927A (en) * 2021-01-14 2022-07-19 深南电路股份有限公司 Printed circuit board manufacturing method and printed circuit board

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008098406A (en) * 2006-10-12 2008-04-24 Furukawa Electric Co Ltd:The Method for manufacturing printed circuit board
JP4676411B2 (en) * 2006-10-12 2011-04-27 古河電気工業株式会社 Method for manufacturing printed wiring board
JP2013191711A (en) * 2012-03-13 2013-09-26 Sumitomo Metal Mining Co Ltd Three-dimensional circuit board, method of manufacturing film-like circuit board, and method of manufacturing three-dimensional circuit board using the same
CN114765927A (en) * 2021-01-14 2022-07-19 深南电路股份有限公司 Printed circuit board manufacturing method and printed circuit board

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