JPH08125315A - Semiconductor package enabling direct die-attachment - Google Patents

Abstract

PURPOSE: To provide an inexpensive and highly reliable semiconductor package which enables direct adhesion without adopting die-attaching technique which is usually used when mounting a semiconductor element in a a semiconductor package production process. CONSTITUTION: A semiconductor package is obtained, wherein a metallic base substrate with a copper foil layer wherein a circuit is machined through an insulation layer on a metallic plate is used and a semiconductor element is thermally compressed directly on an adherent insulation layer wherein a semiconductor package with a brim part which is machined into a soup dish shape through press molding, etc., in the metallic base substrate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package for a semiconductor integrated circuit device, and more particularly to a semiconductor package in which a semiconductor integrated circuit device is directly die-attached with a thermoplastic polyimide.

[0002]

2. Description of the Related Art Semiconductor packages for integrated circuits include DIP (Dual In-line Package) and SOP (Small).
There are various types such as Outline Package) and QFP (Quad Flat Package). For example, a conventional semiconductor package manufacturing process is shown in FIG. 4, in which a semiconductor integrated circuit element is bonded (die-attached) to a die pad portion on a lead frame via an adhesive to form an electrode portion of the integrated circuit element. After connecting the inner lead portion with a bonding wire, the entire body except the outer lead portion is molded with resin.
By the way, as semiconductor devices (chips) are being integrated on a large scale and operating at high speed, semiconductor packages are also required to have a large number of pins, heat dissipation and reliability. In order to meet these demands, for example, the package described in JP-A-1-132147 or the JP-A-4-6893 by the present inventors.
The electronic circuit package described in the publication has been proposed. These semiconductor packages do not use a conventional lead frame, but in the package manufacturing process, as shown in [FIG. 5], a semiconductor element is formed on a die pad portion formed of a copper foil as in a conventional semiconductor package. After bonding with an adhesive and connecting the semiconductor element and the copper foil pattern portion corresponding to the inner lead with a bonding wire, resin sealing is performed.

[0003]

In order to bond (die attach) a semiconductor element to a die pad portion, a gold-silicon eutectic method and a polymer adhesive method are usually used. The gold-silicon eutectic method is used for gold-silicon alloys (6% silicon, 9%
A thin plate of 4% gold) is inserted between the chip and the die pad portion, and heated and melted at 420 to 450 ° C. to be bonded. This method has very high adhesive strength and high connection reliability. However, in the bonding process, a considerably high temperature of 420 to 450 ° C. is required, and when the difference in the coefficient of thermal expansion between the material of the die pad and the chip (silicon) is large (for example, copper and silicon), the thermal stress causes the chip There is a problem that it can be applied only to limited materials (42 alloy, Kovar) due to cracks and the like.

On the other hand, in the method of using an adhesive such as a polymer adhesive, a paste such as silver epoxy or silver polyimide is applied as an adhesive onto a die pad, and after mounting a chip, 1
It is cured at 50 ° C. for 30 to 60 minutes and bonded. At present, a low stress type having a low elastic modulus has been developed as this polymer adhesive, and since it can relieve the thermal stress of the die pad part and the chip considerably, it is widely used in the combination of copper-silicon. However, these silver-filled polymer adhesives have poor thermal stability and cannot be used in highly reliable semiconductor packages that require airtightness, including problems such as outgassing. At present, chips are die-attached with a polymer adhesive for general-purpose and inexpensive semiconductor packages, but there are still many technical issues in the die-attach method with high reliability such as adhesive strength and thermal stress. There are cost problems. It is an object of the present invention to provide a semiconductor package which is inexpensive and can perform highly reliable die attach in a short time without using a conventional gold-silicon eutectic method or a polymer adhesive (silver epoxy, silver polyimide). .

[0005]

That is, the present invention uses a metal base substrate in which a copper foil layer and a base metal plate are laminated via an insulating layer, and the copper foil layer is subjected to circuit processing. Then, in a three-dimensional printed board for mounting a semiconductor integrated circuit element formed into a shape having a brim by bending or drawing the metal base substrate, on the exposed insulating layer on the three-dimensional printed board. It is a semiconductor package characterized in that a semiconductor element is directly bonded by thermocompression bonding, and the temperature is 200 to 400 ° C., preferably 25 ° C., on the exposed insulating layer of the three-dimensional printed board.
0 to 350 ° C., pressure 1 to 30 kg / cm ^2, preferably,
A semiconductor package in which a semiconductor element is thermocompression bonded under the conditions of 3 to 10 Kg / cm ² and a pressure application time of 1 to 5 seconds, the shape of the three-dimensional printed board is a soup plate, and the radius of curvature of the bent portion is , 0.1 mm or more and 5 mm or less, and the insulating layer used for the three-dimensional printed board has an elongation of 30% or more and a glass transition temperature of 160 ° C. or more and 350 ° C. or less. A semiconductor package made of plastic polyimide, and a semiconductor package in which a plurality of insulating layers and copper foil layers used for the three-dimensional printed circuit board are alternately laminated, and a plurality of semiconductor integrated circuit devices can be mounted. .

Further, the present invention is a metal base substrate, which can be suitably used for the above-mentioned semiconductor package, in which a semiconductor element can be directly adhered onto the exposed insulating layer, and the exposed insulating layer is also provided. The above is a metal base substrate suitable for a semiconductor package, to which a semiconductor element can be directly bonded under the above conditions. A further preferred embodiment is a semiconductor package in which at least the surface of the insulating layer is made of a thermoplastic polyimide resin, or a metal base substrate suitable for this.

The constituent features of the present invention will be described below. The present inventors have already proposed JP-A-4-68.
In the semiconductor package described in Japanese Patent Publication No. 93,
A metal base substrate is used in which a copper foil layer circuit-processed via an insulating layer is laminated on a metal plate, and a brim portion is provided on the periphery of the opening surface by bending or drawing the metal base substrate. It has a shape. Then, a portion of the circuit-processed copper foil layer corresponds to the die pad portion for die-attaching the semiconductor element. In the present invention, the copper foil die pad portion is removed to expose the insulating layer, and the semiconductor element Is directly bonded to the exposed insulating layer without using an adhesive. However, the insulating layer has self-adhesiveness as described later, and is originally intended to bond the metal plate and the copper foil layer, but it also has adhesiveness to the semiconductor element (silicon material). Further, since the insulating layer is thermoplastic, the copper foil and the metal plate are bonded to each other by hot pressing at the time of manufacturing the metal base substrate, but after removing the copper foil layer, the semiconductor element is repeatedly thermocompression bonded to the exposed insulating layer portion. Can be glued.

In the semiconductor package of the present invention, a metal base substrate having a thickness of about 0.05 to 2.0 mm is used, preferably 0.1 to 1.0 mm of aluminum, nickel silver or brass. Copper alloy, copper, copper clad invar, stainless steel, iron, silicon steel, electrolytic acid-treated aluminum, etc. can be used.

The insulating layer used in the present invention includes thermosetting resins such as epoxyphenol and bismaleimide, thermoplastic resins such as polyamideimide, polysulfone, polyparabanic acid and polyphenylene sulfide, and precursors of thermoplastic polyimide. A polyamic acid varnish which is obtained by heating and imidizing the varnish can also be used. Alternatively, a heat resistant organic polymer film such as polyimide,
A film obtained by heating and imidizing a polyamic acid varnish, which is a precursor of a thermoplastic polyimide, on both surfaces of each film of polyamide imide, aramid, polyether sulfone, polyether ether ketone, etc. can also be used. In the case of a thermoplastic polyimide soluble in an organic solvent, a thermoplastic varnish is cast in the same manner as the above-mentioned film forming method, or a film obtained by coating and drying,
An extruded film or sheet of thermoplastic polyimide can also be used. Furthermore, on the back surface of the metal base substrate used and / or the copper foil used for forming the conductor layer,
The polyimide varnish or thermoplastic polyimide may be applied, dried, and laminated.

It is also possible to use a combination of the above-mentioned insulating layer materials. Further, for the purpose of improving heat dissipation, an inorganic filler may be added to the insulating layer as long as the machinability such as bending is not impaired. As these fillers,
Alumina, silica, silicon carbide, aluminum nitride, boron nitride, etc. may be mentioned.

Of these insulating layers, the most preferable one in the present invention is a thermoplastic polyimide having an imide structure in the main chain and having a glass transition temperature (Tg) of 16
0 ° C to 350 ° C, JIS (Japanese Industrial Standard)
-The elongation at break measured by the method specified in C2318 is 30% or more. Thus, it is preferable to form the insulating layer or at least the surface of the insulating layer.

By defining the glass transition temperature as described above, both the adhesive strength between the metal plate and the copper foil layer and the thermal reliability during wire bonding become excellent. Further, when the elongation rate is 30% or more, the reliability during machining becomes excellent. Also in such a thermoplastic polyimide, it is of course possible to mix an inorganic filler.

As the copper foil layer used in the present invention, commercially available electrolytic copper foil, rolled copper foil and the like which are relatively inexpensive and easily available are used. It is of course possible to use other metal foil layers instead of the copper foil layers in some cases. As a method for connecting the metal plate as a base, the insulating layer, and the copper foil layer to each other, there are a hot roll method, a hot press method, and the like. A build-up method in which copper is formed as a conductor layer by a vapor deposition method or a plating method after forming an insulating layer on a metal plate can also be used.

In the present invention, when it becomes necessary to mount a semiconductor integrated circuit element directly on a metal plate, in the case of a hot pressing method for removing the insulating layer, the removed portion is punched or an NC router is used. Cutting removal by, wet or dry etching method, laser processing method is used.

When the insulating layer is polyimide, the wet etching is an alkaline solution etching. For example, an alcohol solution such as potassium hydroxide or sodium hydroxide may be used, and a hydrazine compound may be added thereto if necessary. Dry etching includes a plasma ashing method using oxygen plasma and a reactive ion etching method,
If necessary, a fluorocarbon-based gas such as CF ₄ may be mixed. As the laser processing method, for example, an ArF-based or KrF-based excimer laser, or a carbon dioxide gas laser can be used.

The drawing and bending mechanical processing in the present invention can be carried out by press processing using an ordinary die. The conductor portion of the three-dimensional printed board may be resin-coated on the surface of the mold for protection during drawing, or a concave shape may be provided in the mold according to the shape of the wiring pattern. In deep drawing and bending with a small radius of curvature, processing such as application of heat or processing such as swelling the insulating layer with a solvent or the like may be performed. The cross-sectional shape of the semiconductor package of the present invention having a brim portion can be appropriately selected, but for the sake of processing advantages, for example, a soup dish shape is used, and the brim portion is machined within a radius of curvature of about 0.1 to 5.0 mm. It is desirable to do. In the examples described below, the thickness is 1.0 mm.

The semiconductor package of the present invention is characterized in that the semiconductor integrated circuit element and the three-dimensional printed circuit board are bonded by using a thermocompression bonding method as die bonding. Therefore, at the time of circuit processing of the copper foil layer, the copper foil layer (die pad portion) where the semiconductor element is mounted is removed in advance to expose the insulating layer portion.

As the thermocompression bonding method, the semiconductor package is heated from the metal substrate side to the glass transition temperature (Tg) or higher of the insulating layer, that is, 200 to 400 ° C., preferably 250 to 35.
By heating at 0 ° C. and pressing the semiconductor element against the exposed insulating layer portion with a jig, the semiconductor element is bonded by thermocompression. The pressure at this time is 1 to 30 Kg / cm ^2, preferably 3 to 10 Kg / cm ² , and the pressure application time is 1 to
5 seconds. In this case, in order to improve the adhesion between the insulating layer and the semiconductor element, the back surface of the semiconductor element may be chemically etched.

The semiconductor element thermocompression-bonded by the present invention can be removed by applying heat again, and the defective element after the inspection can be removed, and the semiconductor element can be repeatedly bonded to the insulating layer many times. It also has the same effect. Wire bonding is used for the subsequent electrical connection between the semiconductor integrated circuit element and the copper foil wiring pattern of the three-dimensional printed board.

Of course, the number of semiconductor integrated circuit elements mounted on a semiconductor package using this three-dimensional printed board is 1
The number of elements is not limited to one, and a plurality of elements can be mounted. When mounting a plurality of elements, mutual wiring of each element uses a copper wiring pattern of a three-dimensional printed board or a method of using bonding wires together.

The mounted semiconductor integrated circuit element is generally hermetically sealed. For the hermetic sealing, transfer molding or potting method using epoxy resin or the like can be used. Inorganic fillers (alumina, silica, aluminum nitride, silicon nitride, boron nitride) are mixed into the sealing resin, if necessary, from the viewpoint of heat dissipation and matching of thermal expansion coefficient.

When the semiconductor package of the present invention is surface-mounted on a printed board, a usual solder cream printing method is used. As the solder cream, eutectic solder (Sn 63%, Pb 37%) or high temperature solder (Sn 5%, Pb 95%) whose grain type is indefinite or spherical is used.

After the solder cream printing, after mounting the semiconductor package of the present invention on a printed circuit board by an automatic mounting machine,
Solder using a reflow oven. As the reflow furnace at this time, it is desirable to use an infrared heating and air combined type and a nitrogen reflow and vapor phase type. Hereinafter, the present invention will be specifically described with reference to examples.

[0024]

【Example】

Example 1 Example 1 will be described with reference to the drawings. FIG. 1 is a top perspective view of a semiconductor package manufacturing process of one embodiment of the present invention. In FIG. 1, chip die bonding is, of course, “chip die attach”. A sectional view is shown in FIG. What is described as die bonding in FIG. 2 is, of course, “die attach”. This semiconductor package mounts a semiconductor integrated circuit element, and includes a metal base substrate in which a copper foil layer is formed on a metal plate via an insulating layer,
After the circuit pattern is formed, it is bent or drawn to form a soup plate having an opening surface. The radius of curvature of the bent portion of the soup plate-shaped brim portion is 1.0 mm. In this embodiment, in the central portion where the semiconductor element is mounted,
The copper foil layer does not exist, the insulating layer is exposed, and the wiring pattern is formed from the inner lead region in the vicinity to the outer peripheral region of the package.

Copper having a thickness of 0.2 mm was used as the metal plate, thermoplastic polyimide manufactured by Mitsui Toatsu Chemicals, Inc. was used as the insulating layer, and the thickness of each insulating layer was 20 μm. The copper foil layer had a thickness of 18 μm, and the metal plate, the insulating layer, and the copper foil layer were bonded to each other by a hot pressing method.

The copper foil layer is patterned to form a circuit for electrically connecting the inner lead portion in the central portion to the outer lead portion in the peripheral portion. The semiconductor element mounting portion corresponds to the die pad portion in the center. The copper foil portion is removed to expose the insulating layer.

In this embodiment, one semiconductor element is mounted, but a plurality of semiconductor elements can be mounted. The semiconductor element is mounted (die-attached) at the center of the semiconductor package from the opening surface. The semiconductor package is previously heated to 250 ° C. from the package lower surface (metal plate side), and the semiconductor element is sucked with a jig of a vacuum chuck.
Thermocompression bonding was performed at a predetermined position with a pressure of 5 kg / cm ² . The pressure application time at this time is 2 seconds.

After mounting the semiconductor element on the semiconductor package, the semiconductor element is electrically connected to a region corresponding to the inner lead portion in the vicinity by a bonding wire. Further, in order to hermetically seal the semiconductor integrated circuit element and the bonding wire, an epoxy resin containing a filler (alumina, silica, aluminum nitride, boron nitride, etc.) is filled by transfer molding except for the collar portion. . By filling the epoxy resin in the semiconductor package, the mechanical strength of the semiconductor package is also improved.

[Embodiment 2] The technique of directly bonding a semiconductor element on the insulating layer of the present invention is not limited to the semiconductor package. That is, as shown in FIG.
Even when a semiconductor element is mounted on an ordinary metal base substrate that is not mechanically bent and drawn, it is clear that direct mounting by thermocompression bonding is possible as long as the insulating layer according to the present invention is used. Ah

[0030]

As described above, the present invention utilizes a self-adhesive property of the exposed insulating layer in a semiconductor package having a copper foil layer circuit-processed through the insulating layer, so that the semiconductor element is directly packaged. It is to be glued. Therefore, as compared with the conventionally used gold-silicon eutectic method, the bonding can be performed at a considerably low temperature, and the insulating layer used in the present invention has a low elastic modulus, so that the thermal expansion due to the difference in thermal expansion coefficient between the semiconductor element and the metal base substrate The stress is relieved, and highly reliable bonding is possible. In addition, compared to the method using a polymer adhesive such as silver epoxy, the time required for adhesion can be shortened considerably,
Moreover, since the insulating layer used in the present invention has a small amount of impurities inside, it has high thermal stability and can be applied to a highly reliable semiconductor package having high airtightness without problems such as outgassing. As described above, it is possible to provide a low-cost and highly reliable semiconductor package without using the die attach technology which has been conventionally used.

[Brief description of drawings]

FIG. 1 is a top perspective view showing a semiconductor package manufacturing process of the present invention.

FIG. 2 is a sectional view thereof

FIG. 3 is an explanatory diagram showing direct die attachment to a metal base substrate.

FIG. 4 is an explanatory diagram showing a conventional semiconductor package manufacturing process.

FIG. 5 is an explanatory diagram showing a conventional semiconductor package manufacturing process.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Naoshi Mineta 1190 Kasama-cho, Sakae-ku, Yokohama-shi, Kanagawa Mitsui Toatsu Chemical Co., Ltd.

Claims (9)

[Claims] 1. A metal base substrate in which a copper foil layer and a metal plate of a base are laminated via an insulating layer, and the copper foil layer is subjected to circuit processing, and the metal base substrate is bent or bent. In a three-dimensional printed board for mounting a semiconductor integrated circuit element formed into a shape having a brim by performing a drawing process, the semiconductor element is directly bonded by thermocompression bonding on the exposed insulating layer on the three-dimensional printed board. A semiconductor package characterized by the following. 2. A temperature of 200 to 400 ° C. and a pressure of 1 to 30 kg / cm on the exposed insulating layer of the three-dimensional printed board.
^2. The semiconductor package according to claim 1, wherein the semiconductor element is thermocompression bonded under the condition that the pressure application time is 1 to 5 seconds. 3. The shape of the three-dimensional printed board is on a soup plate, and the radius of curvature of the bent portion is 0.1 mm or more and 5 mm.
The semiconductor package according to claim 1, wherein: 4. The insulating layer used for the three-dimensional printed board is composed of a thermoplastic polyimide having an elongation of 30% or more and a glass transition temperature of 160 ° C. or more and 350 ° C. or less. 3. The semiconductor package according to any one of 3. 5. The semiconductor package according to claim 1, wherein a plurality of insulating layers and copper foil layers used for the three-dimensional printed circuit board are alternately laminated and a plurality of semiconductor integrated circuit elements can be mounted. 6. A metal base substrate, which can be suitably used for the semiconductor package according to claim 1, and in which a semiconductor element can be directly bonded onto the exposed insulating layer. 7. The metal base substrate according to claim 6, wherein a semiconductor element is directly bonded on the exposed insulating layer under the condition of claim 2. 8. The semiconductor package according to claim 1, wherein at least the surface of the insulating layer is formed of a thermoplastic polyimide resin. 9. The metal base substrate according to claim 6, wherein at least the surface of the insulating layer is formed of a thermoplastic polyimide resin.