JPH08116467A - Synchronizing signal processing circuit - Google Patents

Abstract

PURPOSE: To reduce disturbance of synchronization in the synchronizing signal processing circuit in an on-vehicle television receiver in which interruption of a radio wave frequently takes place. CONSTITUTION: A reset signal generating circuit 42 generates a reset signal in response to a horizontal synchronizing signal and a vertical synchronizing signal separated by a synchronizing separator circuit 41 depending on the trailing timing of the horizontal synchronizing signal and the vertical synchronizing signal and gives it to a gate circuit 43. An IFAGC signal to increase a gain of an intermediate frequency amplifier circuit at a weak electric field strength is given to the gate circuit 43 corresponding to the electric field strength level, and in the case of a medium or strong electric field strength, the reset signal is given to an internal synchronizing signal generating circuit 44, which is reset. An oscillation signal from an oscillation circuit 62 oscillated by a color burst frequency is given to the internal synchronizing signal generating circuit 44 and the circuit 62 is run in itself for each vertical scanning period or each horizontal scanning period from the timing when the reset signal is received to provide the internal horizontal synchronizing signal and the internal vertical synchronizing signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing signal processing circuit in a television receiver, and more particularly, it is preferably implemented in an on-vehicle television receiver in which a weak electric field and radio wave interruption frequently occur. And a synchronous signal processing circuit.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing an electrical configuration of a sync signal processing circuit 1 in a typical conventional vehicle-mounted television receiver. The horizontal and vertical sync signals separated by the sync separation circuit from the composite video signal demodulated by the detection circuit are respectively connected to terminals P1 and P2.
Input from.

The phase difference between the input horizontal synchronizing signal input and the output horizontal synchronizing signal output from the terminal P3 to the driving circuit of the deflection coil is compared in the phase comparator 2 as described later. An error signal corresponding to the phase difference is output from the phase comparator 2, smoothed by a low pass filter (abbreviated as LPF) 3, and then input to a voltage controlled oscillator 4.

The voltage controlled oscillator 4 outputs an oscillation signal having a frequency corresponding to the input voltage. However, when the frequency of the input horizontal synchronizing signal input to the terminal P1 and the output horizontal synchronizing signal output from the terminal P3 is fo, oscillation is performed at a frequency of 2fo. The oscillation signal from the voltage controlled oscillator 4 is divided by the frequency divider 5 into 1/2, and then output to the terminal P3 and given to the phase comparator 2. Thus, a so-called phase lock loop (abbreviated as PLL) is formed, automatic frequency control (abbreviated as AFC) operation is realized, and a stable output horizontal synchronizing signal is created.

On the other hand, the vertical synchronizing signal input from the terminal P2 is input to the counter 7 via the gate circuit 6. The counter 7 resets the count value in response to the output from the gate circuit 6, that is, when the vertical synchronizing signal is input, and counts the number of pulses of the oscillation signal from the voltage controlled oscillator 4. . This counter 7
Outputs a prohibition signal to the gate circuit 6 for a predetermined period from the input timing of the vertical synchronization signal, whereby the gate circuit 6 prohibits the input of the vertical synchronization signal for the predetermined period. This function is for stabilizing the cycle of the vertical synchronizing signal by invalidating the input even if the vertical synchronizing signal input at a substantially constant cycle is input within the predetermined period due to the influence of a reflected wave or the like. It is a thing.

The gate circuit 6 activates the counter 8 via the counter 7 in response to the predetermined period and the input vertical synchronizing signal. When the counter 8 is activated, output of a vertical synchronizing signal from the counter 8 to the terminal P4 is started to the deflection coil drive circuit.
When the count value of 1 reaches a predetermined value, the output of the vertical synchronizing signal is stopped. In this way, the vertical sync signal generated based on the horizontal sync signal is suppressed even in the case of the vertical sync signal, which is less frequent than the horizontal sync signal, in order to suppress the influence of the missing vertical sync signal. The signal is configured to be output at a substantially constant period.

[0007]

In the sync signal processing circuit 1 as described above, when the composite video signal is shown in FIG.
The electric field strength level is 30 dB as shown before time α1.
Although a relatively stable horizontal synchronizing signal and vertical synchronizing signal as shown in FIG. 7 (2) can be obtained in a medium electric field to weak electric field of about μV, reference numeral α2 in FIG. In a situation where the electric wave interruption as shown in Fig. 7 is repeated frequently, the AFC operation becomes unstable, and
In (2), there is a problem that synchronization disturbance occurs as indicated by reference numeral α3 and as shown in FIG.

As another conventional technique, Japanese Patent Laid-Open No. 4-68 is known.
670 is mentioned. In this conventional technique, an input synchronizing signal is used as an external synchronizing signal, an internal synchronizing signal is always created in response to the external synchronizing signal, and when the external synchronizing signal is lost, the internal synchronizing signal is switched to. It is a thing.

However, since this prior art also uses the synchronizing signal in the received composite video signal, if this synchronizing signal is frequently lost, there is a problem that stable operation cannot be performed.

An object of the present invention is to provide a synchronization signal processing circuit capable of reducing synchronization disturbance even in a situation where a weak electric field and radio wave interruption frequently occur such that synchronization signal extraction becomes unstable. Is to provide.

[0011]

According to the present invention, there are provided horizontal and vertical reset signal generating means for generating horizontal and vertical reset signals corresponding to falling edges of an input horizontal synchronizing signal and vertical synchronizing signal, respectively, and a color. An oscillating unit that oscillates at a frequency based on a burst frequency, and the number of oscillation pulses of the oscillating unit that is reset in response to the horizontal reset signal is counted, and the count value corresponds to one horizontal scanning cycle. When you reach
An internal horizontal synchronizing signal generating means for outputting a pulse for a predetermined period as an internal horizontal synchronizing signal, resetting a count value and repeating the count operation, and an oscillation pulse of the oscillating means reset in response to the vertical reset signal. When the number of pulses is counted and when the count value reaches the count value corresponding to one vertical scanning cycle, a pulse for a predetermined period is output as an internal vertical synchronization signal, and the count value is reset and the count operation is repeated. A gate element interposed between the signal generating means, the horizontal and vertical reset signal generating means, and the corresponding internal horizontal synchronizing signal generating means and internal vertical synchronizing signal generating means, and the input horizontal synchronizing signal and Selectively outputs the vertical sync signal and the internal horizontal sync signal and internal vertical sync signal Switch means capable of switching, a detection means for detecting deterioration of an input video signal, and a horizontal and vertical reset signal by the gate element when the deterioration is detected in response to the detection result of the detection means. And a control means for causing the switching means to output the internal horizontal synchronization signal and the internal vertical synchronization signal, and a synchronization signal processing circuit. Further, the deterioration detecting means of the present invention is characterized in that deterioration detection is performed from the AGC signal for controlling the gain of the intermediate frequency amplifier circuit in accordance with the intermediate frequency signal level or the demodulated video signal level. Furthermore, the deterioration detecting means of the present invention is characterized by detecting a loss of at least one of the input horizontal synchronizing signal and vertical synchronizing signal.

[0012]

According to the present invention, during normal reception in the medium and strong electric fields, the horizontal synchronizing signal and the vertical synchronizing signal obtained by synchronously separating from the composite video signal detected by the detecting circuit are switched from the switching means to the deflection coil. When a weak electric field and radio wave interruption occur and the video signal deteriorates, an internal horizontal sync signal and an internal vertical sync signal created based on the color burst frequency are output from the switching means. To be done.

That is, the input horizontal synchronizing signal and vertical synchronizing signal are input to the horizontal reset signal generating means and the vertical reset signal generating means, respectively, and these horizontal and vertical reset signal generating means are connected to the horizontal and vertical synchronizing signals. Generate horizontal and vertical reset signals for each falling edge of. On the other hand, an oscillating means for oscillating at a frequency based on 3.579545 MHz which is the frequency fsc of the color burst signal used for creating a color subcarrier, for example, a frequency of 4 times is provided.

Correspondingly, the horizontal scanning frequency f _H = f
By using the relationship of sc × 2/455, the number of oscillation pulses of the oscillation means is counted, and when the count value reaches one horizontal scanning period, that is, 910 which is a count value corresponding to 63.556 μsec, For a predetermined period, for example, 4.7 μ, which is almost equal to the width of the horizontal sync pulse
There is provided an internal horizontal synchronizing signal generating means for outputting a pulse of sec as an internal horizontal synchronizing signal, resetting the count value and repeating the counting operation.

Similarly, the vertical scanning frequency f _V = f _H ×
The number of oscillation pulses of the oscillation means is counted using the relationship of 2/525, and the count value reaches one vertical scanning period, that is, a count value corresponding to 16.683 msec, that is, 910 × 262.5 = 20475. Then, a predetermined period, for example, 3 horizontal scanning periods 63.
A pulse corresponding to 556 × 3≈190.7 μsec is output as an internal vertical synchronizing signal, and an internal vertical synchronizing signal generating means for resetting the count value and repeating the counting operation is provided.

A gate element is interposed between the horizontal reset signal generating means and the internal horizontal synchronizing signal generating means, and between the vertical reset signal generating means and the internal vertical synchronizing signal generating means. When the gate element is cut off, the input of the horizontal and vertical reset signals to the internal horizontal synchronizing signal generating means and the internal vertical synchronizing signal generating means is blocked, and the reset operation is not performed, which corresponds to the one horizontal scanning period. When the count value and the count value corresponding to one vertical scanning period are reached, the internal horizontal synchronization signal generating means and the internal vertical synchronization signal generating means reset the count value and repeat the counting operation, and thus self-run and internal horizontal synchronization. Signal and internal vertical sync signal respectively.

The internal horizontal synchronizing signal and the internal vertical synchronizing signal thus obtained are input to the switching means together with the input horizontal synchronizing signal and vertical synchronizing signal. This switching means is realized by, for example, a switch having two individual contacts and one common contact, and one of the individual contacts is provided with the internal horizontal synchronizing signal and the internal vertical synchronizing signal,
The input horizontal synchronizing signal and vertical synchronizing signal are applied to the other individual contact. The switching means is switching-controlled by the control means in response to the degree of deterioration of the video signal detected by the detection means.

Specifically, the deterioration detecting means is configured to amplify the intermediate frequency in accordance with the level of the intermediate frequency signal in the intermediate frequency amplifier circuit or the level of the demodulated video signal from the detection circuit, that is, in response to the electric field strength level. Deterioration is detected from the AGC signal for controlling the gain of the circuit. Therefore, the lower the electric field strength level, the higher it becomes,
It is determined that the electric field strength level is lower as the level of the AGC signal for increasing the gain of the intermediate frequency amplifier circuit is higher. Further, the deterioration detecting means may be configured to detect the deterioration of the video signal by detecting the loss of at least one of the input horizontal synchronizing signal and vertical synchronizing signal.

When the deterioration of the video signal is detected in this manner, the control means responds to the detection result and shuts off the gate element to shut off the horizontal and vertical reset signals to cause the horizontal synchronizing signal generating means. The vertical synchronizing signal generating means is self-propelled, and the switching means outputs the internal horizontal synchronizing signal and the internal vertical synchronizing signal to the deflection coil and the like.

Therefore, as described above, since the relationship between the horizontal scanning frequency f _H and the vertical scanning frequency f _V is strictly defined and a color burst signal having a stable frequency is used, the weak electric field and radio wave blocking are frequently performed. In a situation where such a situation occurs, switching to the internal horizontal synchronization signal and the internal vertical synchronization signal can suppress the occurrence of synchronization disturbance.

[0021]

1 is a block diagram showing the electrical construction of a sync signal processing circuit 11 according to an embodiment of the present invention, and FIG. 2 shows an on-vehicle television receiver 12 equipped with the sync signal processing circuit 11. It is a block diagram which shows an electric constitution. The reception signal received by the antenna 13 is input from the tuning circuit 14 to the high-frequency amplifier circuit 15 and amplified, and then further passed through the tuning circuit 16 to mix the signal components near the frequency band of the broadcasting station to be received. 17 is input. The mixer 17
Further, a local oscillation signal corresponding to the reception frequency from the local oscillation circuit 18 is input to. This local oscillator circuit 1
The oscillation frequency of 8 and the tuning frequencies of the tuning circuits 14 and 16 are controlled by the control circuit 19.

When the television broadcast wave is transmitted in the upper sideband system, the intermediate frequency signal from the mixer 17 has a desired band component filtered by the filter 20 realized by a high pass filter, and the intermediate frequency signal is amplified. Circuit 2
After being amplified by 1, it is input to the video detection circuit 22. The composite video signal demodulated by the video detection circuit 22 is amplified by the video amplification circuit 23 and then input to the color demodulation circuit 24 and the sync signal processing circuit 11. by this,
Video signals of the three primary colors RGB are demodulated from the color demodulation circuit 24 and input to the cathode when the display device 25 is a cathode ray tube, for example. The synchronization signal demodulated by the synchronization signal processing circuit 11 is input to the display device 25, for example, a circuit for driving a deflection coil.

On the other hand, an audio intermediate frequency signal is also extracted from the intermediate frequency amplifier circuit 21, the audio intermediate frequency signal is amplified by the audio intermediate frequency amplifier circuit 26, and then input to the audio detection circuit 27. The audio signal demodulated by the audio detection circuit 27 is amplified by the audio amplification circuit 28 and then given to the speaker 29 to be sonicated.

The output from the video amplifier circuit 23 is also
It is supplied to the brightness level detection circuit 31, which detects the brightness level from the composite video signal and supplies the detection result to the detection circuit 32. The detection circuit 32 smoothes the output corresponding to the brightness level from the brightness level detection circuit 31 and supplies it to the intermediate frequency control circuit 33. The intermediate frequency control circuit 33 outputs an IFAGC signal whose level decreases as the brightness level decreases from the input output of the detection circuit 32, and increases the gain of the intermediate frequency amplifier circuit 21 to, for example, an antenna. When the input electric field strength level to 13 becomes about 50 dBμV or less, the gain of the intermediate frequency amplifier circuit 21 is increased, and thus the IFAGC operation by weak electric field detection is performed.

The output from the detection circuit 32 is applied to the high frequency control circuit 34 via the intermediate frequency control circuit 33. The high frequency control circuit 34 uses the antenna 13
The higher the input electric field strength level is, the higher the level of the RFAGC signal is output, and the tuning degree of the high frequency amplifier circuit 15, for example, is lowered. Is detected, the RF AGC operation for suppressing the antenna input level is performed in order to suppress the distortion in the mixing circuit 17 or the like.

Referring to FIG. 1, synchronization signal processing circuit 11
Is a sync separation circuit 41 and a reset signal generation circuit 42.
A gate circuit 43, an internal synchronizing signal generating circuit 44,
And a switching circuit 45. The composite video signal from the video amplifier circuit 23 is given to a sync separation circuit 41, and in this sync separation circuit 41, a horizontal sync signal and a vertical sync signal as shown in FIG. 3 (1) are mixed. Separate the sync signal. The synchronization signal is the one-shot multivibrator 5 in the reset signal generating circuit 42.
It is input to one of the input terminals A1 and A2 of 1, 52, respectively.

In the one-shot multi-vibrator 51, a low level input is given to the other input terminal B1, and this one-shot multi-vibrator 51 receives the low-level pulse at the terminal A1. As indicated by 3 (2), a low-level horizontal reset signal is output for a predetermined time W1 from that time, for example, 40 μsec. This horizontal reset signal is
An integrating circuit 53 which is output from the output terminal Qa1 and includes a resistor R1 and a capacitor C1; an inverting buffer 54;
It is applied to a differentiating circuit 56 including a NOR gate 55.

By inputting the output shown in FIG. 3 (2) from the one-shot multivibrator 51, the integrating circuit 53 derives an output as shown in FIG. 3 (3), and this output is the inverting buffer 54. In FIG. 3 (4), it is inverted and then applied to one input of the NOR gate 55. The output from the one-shot multivibrator 51 is directly input to the other input of the NOR gate 55. Therefore, an output as shown in FIG. 3 (5) is derived from the NOR gate 55 and is given to one input of the AND gate G1 of the gate circuit 43 as a horizontal reset signal.

Similarly, the one-shot multivibrator 52 provided for the vertical synchronizing signal is supplied with the synchronizing signal at its input terminal A2 and is supplied with a low level input at its input terminal B2. Therefore, when a low level pulse is input to the input terminal A2, the one-shot multivibrator 52 outputs a low level pulse from the output terminal Qa2 for a predetermined time W2, for example, 10 μsec, as shown in FIG. 3 (6). Output. The output of the one-shot multivibrator 52 is input to the clock input terminal CK3 of the flip-flop 57. The synchronization signal is directly input to the input terminal D3 of the flip-flop 57. This flip-flop 57 is a so-called D flip-flop,
The period of the horizontal synchronizing signal indicated by reference numeral W3 in FIG. 3 (1) is 4.7 μsec as described above, while the pulse in response to the horizontal synchronizing signal from the one-shot multivibrator 52 is Time W2 10μ
Therefore, when a pulse longer than the time W2 is input from the flip-flop 57, that is, when a vertical synchronizing signal is input from the flip-flop 57, FIG.
A low level pulse as shown in (7) is output terminal Q3.
Output from

The output from the flip-flop 57 is
Like the differentiating circuit 56, the resistor R2 and the capacitor C2
And an inversion buffer 59 and an NO
3 is input to the differentiating circuit 61 including the R gate 60, and FIG.
A vertical reset signal as shown in (8) is created and given to one input of the AND gate G2 of the gate circuit 43.

IFAG from the intermediate frequency control circuit 33 is commonly applied to the other inputs of the AND gates G1 and G2.
The C signal is provided. Therefore, when the input electric field strength level is higher than 50 dBμV or a strong electric field, the other inputs of the AND gates G1 and G2 are set to the high level, whereby the horizontal reset signal and the vertical reset signal are generated respectively. It is input to the circuit 44.

The internal synchronizing signal generating circuit 44 is composed of the oscillating circuit 6
2, two counters 63 and 64, one-shot multivibrators 65 and 66, and an AND gate 67. Outputs from the AND gates G1 and G2 are input to clear terminals CL1 and CL2 of counters 63 and 64, respectively. These counters 6
Oscillation signals from the oscillation circuit 62 are input to the clock input terminals CK1 and CK2 of 3, 64. Oscillation circuit 6
2, the oscillating frequency of the color burst signal is strictly defined in response to the received color burst signal by a configuration (not shown), which is the color burst frequency fsc of 3.5795.
14.31818MH which is 4 times of 45MHz frequency fsc
Based on z, oscillation is performed at that frequency, for example.

On the other hand, the counter 63 is realized as a 910-ary counter by using the relationship of horizontal scanning frequency f _H = fsc × 2/455. Therefore, a low level pulse is output from the output terminal Ea1 every horizontal scanning period. The low-level pulse is applied to the reset terminal L
When the horizontal reset signal is input to the clear terminal CL1, the counter 63 starts the count operation after the reset operation, and the horizontal reset signal is input to the clear terminal CL1. Even if the count value reaches 910, the pulse output from the output terminal Ea1 is input to the reset terminal La1 to reset and restart the counting operation. Thus, even if the horizontal reset signal is not input, the counter 63 responds to the oscillation signal from the oscillation circuit 62,
It is self-propelled and outputs a pulse every horizontal scanning period.

The pulse is applied to one input terminal A4 of the one-shot multivibrator 65, and a low level is applied to the other terminal input B4 of the one-shot multivibrator 65. Therefore,
When a low-level pulse is derived from the output terminal Ea1 of the counter 63 from the one-shot multivibrator 65, a low-level pulse is output from the output terminal Qa4 for a predetermined time W4 as shown in FIG. 3 (9). Is output. The time W4 is selected to be 4.7 μsec which is the pulse width of the horizontal synchronizing signal.

Similarly, the clear terminal C of the counter 64 is also provided.
The vertical reset signal from the AND gate G2 is applied to L2, and the oscillation signal from the oscillation circuit 62 is applied to the clock input terminal CK2. The counter 64 is realized by a 910 × 262.5 = 20475 base counter using the relationship of the vertical scanning frequency f _V = f _H × 2/525. Therefore, a low-level pulse is output from the output terminal Ea2 of the counter 64 every one vertical scanning period, and this pulse is input to the reset terminal La2 and the one-shot multivibrator 66 is also supplied.
Is applied to one input terminal A5.

The one-shot multivibrator 66
A low level voltage is applied to the other input terminal B5. This one-shot multi-vibrator 66
When a low-level pulse is input,
As shown in, output terminal Qa5
Outputs a low level pulse. The time W5 is
63.556 × 3≈190.7μ which is 3 horizontal scanning periods
Selected for sec. In this way, the one-shot multi-vibrators 65 and 66 output the internal horizontal synchronizing signal and the internal vertical synchronizing signal, respectively, and these signals are added by the AND gate 67 as shown in FIG. 45 is applied to one input terminal A6.

The changeover circuit 45 is realized by a changeover switch having two individual contacts and one common contact.
The sync signal from the sync separation circuit 41 is directly input to the other input terminal B6 of the switching circuit 45. When a low level output by the weak electric field detection is input to the control terminal S from the intermediate frequency control circuit 33, the switching circuit 45 connects the output terminal Y connected to the display device 25 to the input terminal A6 side. The internal horizontal and vertical synchronizing signals are output to the display device 25, and when the medium and strong electric fields are present, they are conducted to the input terminal B6 side, and the horizontal and vertical synchronizing signals from the sync separation circuit 41 are directly output to the display device 25. To do.

As described above, the color burst signal having a strictly defined frequency generated based on the received color burst signal is used to reset in response to the received horizontal synchronizing signal and vertical synchronizing signal. Create internal horizontal sync signal and internal vertical sync signal respectively,
When the video signal is deteriorated due to a weak electric field, the generated internal horizontal synchronizing signal and internal vertical synchronizing signal are self-propelled and given to the display device 25. Therefore, as described in the prior art, the horizontal synchronizing signal It is possible to generate a stable synchronization signal even when there is a loss, and it is possible to suppress the occurrence of synchronization disorder.

FIG. 4 is a block diagram showing the electrical construction of the deterioration detecting circuit 71 according to another embodiment of the present invention. In the above-described embodiment, the brightness level detection circuit 31 and the detection circuit 32.
Functions as a detecting means for detecting the deterioration of the input video signal, and also the intermediate frequency control circuit 33 and the switching circuit 4.
Reference numeral 5 functions as control means for switching between the input synchronizing signal and the internal synchronizing signal. On the other hand, in this embodiment, the deterioration detection circuit 71 is used instead of the deterioration detection of the video signal by the brightness level detection circuit 31, the detection circuit 32 and the intermediate frequency control circuit 33. The inspection / deterioration detection circuit 71 is provided in the synchronization signal processing circuit 11.

The deterioration detecting circuit 71 comprises a horizontal sync detecting section 72, a vertical sync detecting section 73, and an AND gate 74. The horizontal sync detector 72 includes a free counter 75 to which the horizontal sync signal from the sync separation circuit 41 is applied, an inverting buffer 76 to which the horizontal sync signal is also applied, and a comparator to which an output from the free counter 75 is applied. 77, a flip-flop 78 to which outputs from the free counter 75 and the inverting buffer 76 are given, a comparator 79 to which outputs from the flip-flop 78 are given, and outputs from the comparators 77 and 79 are added and output. AND gate 80, setting circuit 81,
And 82.

From the sync separation circuit 41, as shown in FIG.
The horizontal synchronizing signal indicated by is input to the reset terminal R11 of the free counter 75. As a result, the free counter 75 is reset as shown in FIG. 5B to restart the counting operation. An output representing the count value of the free counter 75 is given to the input terminal A11 of the comparator 77. The other input terminal B11 of the comparator 77 is
A reference value obtained by adding N, which is a redundant value, to the count value 910 corresponding to the count value of the counter 63 is input from the setting circuit 81. Therefore, as indicated by the reference sign β1 in FIG. 5, when the horizontal synchronization signal is lost at time t1 and the count value of the free counter 75 exceeds 910 and increases by the redundancy value N, the time t2 in FIG. As shown in 3), a low level output is derived from the comparator 77 and applied to one input of the AND gate 80.

On the other hand, the horizontal sync signal from the sync separation circuit 41 is also transferred to the inverting buffer 76 shown in FIG.
The polarity is inverted as shown in (4), and then applied to the clock input terminal CK11 of the flip-flop 78. The count value from the free counter 75 is given to the input terminal D11 of the flip-flop 78. Therefore, in the flip-flop 78, the count value of the free counter 75 latched in response to the horizontal synchronizing signal is a value close to the count value 910 in the normal state, whereas it is indicated by reference numeral β2 in FIG. As described above, when the timing of the horizontal synchronizing signal is deviated due to multipath or fading, the value becomes smaller than the value 910.

This latch output is given to one input terminal A12 of the comparator 79. Further, a reference value corresponding to a value obtained by subtracting the redundant value N from the count value 910 is given from the setting circuit 82 to the other input terminal B12 of the comparator 79. 5
As shown in (5), at time t4, which is earlier by the redundant value N than the time at which the original horizontal synchronizing signal at time t3 is input.
If noise was previously input, AND from that time t5
A low level output is derived from the other input of the gate 80. Therefore, from the AND gate 80, FIG.
An output as shown by is output to the switching circuit 45. In this way, the deterioration of the video signal may be detected due to the lack of the horizontal synchronizing signal or the timing shift of the horizontal synchronizing signal.

The vertical sync detector 73 has the same structure as the horizontal sync detector 72. Corresponding parts are designated by the same reference numerals with a suffix a. However, in the comparators 77 and 79, the input terminals B11a and B12a are
The count value 2 from the setting circuits 81a and 82a, respectively.
The value obtained by adding or subtracting the redundant value is set in 0475.

Further, the flip-flops 78, 78a are
The count value latched by each of the flip-flops 78, 78a is provided only for a plurality of bits,
It is given to the comparators 79 and 79a as digital data.

In this way, the deterioration of the video signal may be detected from the output of the AND gate 74 from the missing pulse or the timing shift of the horizontal synchronizing signal or the vertical synchronizing signal. In this way, by switching to the internal horizontal synchronizing signal and the internal vertical synchronizing signal in response to a pulse loss or timing shift, switching is performed again when the input horizontal synchronizing signal returns to normal. The responsiveness can be improved.

Further, as in the above-described embodiment, the IFAGC voltage to the intermediate frequency amplifier circuit 21 and the lack of the horizontal or vertical synchronizing signal may be used together to detect the deterioration of the video signal.

[0048]

As described above, according to the present invention, at the time of normal reception in the medium and strong electric fields, the horizontal synchronizing signal and the vertical synchronizing signal obtained by synchronously separating from the composite video signal detected by the detection circuit are obtained. When a weak electric field and radio wave interruption occur and the video signal deteriorates, the relationship between the horizontal scanning frequency f _H and the vertical scanning frequency f _V is strictly defined, and the color burst signal has a stable frequency. Since the internal horizontal synchronizing signal and the internal vertical synchronizing signal generated based on the above are output, it is possible to suppress the occurrence of synchronization disturbance even in such a situation.

[Brief description of drawings]

FIG. 1 is a block diagram showing an electrical configuration of a sync signal processing circuit 11 according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an electrical configuration of a television receiver 12 in which the synchronization signal processing circuit 11 is used.

FIG. 3 is a waveform diagram for explaining an operation of generating an internal synchronization signal in the synchronization signal processing circuit 11.

FIG. 4 is a block diagram showing an electrical configuration of a deterioration detection circuit 71 according to another embodiment of the present invention.

FIG. 5 is a timing chart for explaining the operation of the deterioration detection circuit 71.

FIG. 6 is a block diagram showing an electrical configuration of a synchronization signal processing circuit 1 in a typical conventional vehicle-mounted television receiver.

FIG. 7 is a waveform diagram for explaining synchronization disorder due to a lack of a synchronization signal in the synchronization signal processing circuit 1.

FIG. 8 is a diagram showing an example of a display image when the synchronization disorder occurs.

[Explanation of symbols]

 11 sync signal processing circuit 12 television receiver 21 intermediate frequency amplification circuit 22 video detection circuit 31 luminance level detection circuit 32 detection circuit 33 intermediate frequency control circuit 34 high frequency control circuit 41 sync separation circuit 42 reset signal generation circuit 43 gate circuit 44 internal Synchronous signal generation circuit 45 Switching circuit 62 Oscillation circuit 63, 64 Counter 71 Deterioration detection circuit

Claims (3)

[Claims] 1. A horizontal and vertical reset signal generating means for generating horizontal and vertical reset signals corresponding to falling edges of an input horizontal synchronizing signal and vertical synchronizing signal, respectively, and oscillating at a frequency based on a color burst frequency. The oscillating means for performing resetting in response to the horizontal reset signal, counting the number of oscillating pulses of the oscillating means, and when the count value reaches the count value corresponding to one horizontal scanning period, the pulse for a predetermined period Is output as an internal horizontal synchronizing signal, the internal horizontal synchronizing signal generating means for resetting the count value and repeating the counting operation, and the number of oscillation pulses of the oscillating means reset in response to the vertical reset signal are counted. Then, when the count value reaches the count value corresponding to one vertical scanning cycle, An internal vertical synchronizing signal generating means for outputting a pulse of a period as an internal vertical synchronizing signal, resetting a count value and repeating a counting operation, the horizontal and vertical reset signal generating means, and an internal horizontal synchronizing signal generating means respectively corresponding thereto. And a gate element interposed between the internal vertical synchronizing signal generating means and the internal vertical synchronizing signal generating means, the input horizontal synchronizing signal and vertical synchronizing signal, and the internal horizontal synchronizing signal and internal vertical synchronizing signal. Switchable means, detecting means for detecting deterioration of the input video signal, and in response to the detection result of the detecting means, when the deterioration is detected, the horizontal and vertical reset signals are cut off by the gate element. And a control means for outputting the internal horizontal synchronizing signal and the internal vertical synchronizing signal from the switching means. Synchronizing signal processing circuit according to claim. 2. The deterioration detecting means detects deterioration from the AGC signal for controlling the gain of the intermediate frequency amplifier circuit in accordance with the intermediate frequency signal level or the demodulated video signal level. 1. The synchronization signal processing circuit according to 1. 3. The synchronizing signal processing circuit according to claim 1, wherein the deterioration detecting unit detects a loss of at least one of the input horizontal synchronizing signal and vertical synchronizing signal.