JPH08115251A - Computer system - Google Patents

Abstract

PURPOSE: To allow a CPU to maintain high performance even when access is given from another bus master to a main memory while the CPU has access to the main memory. CONSTITUTION: As the main memory 13 of the CPU 11, a multi-port memory provided with a serial access port in addition to a random access port is used and the access of the main memory (MPM) 13 by the bus masters (a DMA controller 14 and a refresh controller 15) other than the CPU 11 is performed through the random access port. The CPU 11 performs control so as to transfer a group of data and instructions from the main memory 13 to a cache system 12 through the serial access port of the main memory 13. The control is performed by accessing the random access port of the main memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system, and more particularly to a computer system having a bus master other than the CPU for accessing the main memory of the CPU.

[0002]

2. Description of the Related Art Generally, when constructing a computer system, some measures are taken to improve the performance of the entire system. For example, the processing of the CPU (Central Processing Unit) is accelerated by using a cache system, or the data transfer between the main memory and the external storage device is performed by the DMA without the control of the CPU.
A typical example is to use a controller (direct memory access controller). An outline of a conventional general computer system whose performance is improved by using such a method will be described below with reference to the drawings.

FIG. 6 is a block diagram showing a hardware configuration of a conventional general computer system. As shown in the figure, this conventional computer system comprises a CPU 1, a cache system 2, a main memory 3, a DMA controller 4, and a refresh controller 5. The individual blocks 2 to 5 are connected to the main memory 3 via the bus 6, and the cache system 2 is
The CPU 1 is directly connected to the CPU 1 without going through the bus 6 so that the CPU 1 can access at high speed.

Here, the cache system 2 is a CP
U1 has a built-in cache memory (not shown) and a cache controller (not shown) that can be accessed at high speed, and this cache memory stores a series of programs stored in the main memory 3. Among the data and instructions (instructions), the data frequently accessed by the CPU 1, the instruction executed next by the CPU 1 and the instruction subsequent thereto, and the like follow the main memory 3 in units of one line of the cache memory via the bus 6. Read from and written to. Then, the CPU 1 normally executes a program efficiently and at high speed by accessing a group of data or a copy of an instruction in the main memory 3 written in the cache memory. Then, when the data to be accessed or the instruction to be executed next does not exist in the cache memory, the CPU 1 newly reads the above-mentioned one-line data including the data and the instruction from the main memory 3. And stores it in the cache memory in the cache system 2. That is, in this computer system, the data frequently accessed by the CPU 1 stored in the main memory 3 and the instruction that is likely to be executed next are sequentially transferred from the main memory 3 to the cache memory by the CPU 1. The data is transferred and held, and the CPU 1 can execute a program at high speed by accessing the cache memory. Thus, in this system, the cache
By providing the system 2, the performance of the entire system is improved.

On the other hand, the DMA controller 4 is
When it is necessary to transfer data between the memory 3 and an external storage device (not shown) such as an HDD (hard disk drive), the data transfer is executed independently of the CPU 1. That is, the DMA controller 4
The right to use the bus 6 is acquired from the CPU 1, and data is burst-transferred between the main memory 3 and the external storage device. As described above, in this system, the performance of the entire system is improved by providing the DMA controller 4.

The refresh controller 5 is a DRA.
The contents of the individual memory cells of the main memory 3 composed of M (dynamic random access memory) are rewritten periodically to retain the data in the main memory 3.

[0007]

In the above computer system, in addition to the CPU 1, the DMA controller 4
Then, the refresh controller 5 also accesses the main memory 3 via the bus 6. That is, CPU
1, the DMA controller 4, and the refresh controller 5 are bus masters, and when the CPU 1 needs to transfer one line of data or instructions from the main memory 3 to the cache system 2, the main Access the memory 3. Also,
The DMA controller 4 accesses the main memory 3 when it is necessary to transfer data between the main memory 3 and an external storage device. Also, refresh
The controller 5 accesses the main memory 3 to periodically refresh the main memory 3.

Here, the conditions under which the CPU 1, the DMA controller 4, and the refresh controller 5 access the main memory 3 have no correlation with each other,
Each access occurs irregularly. Therefore,
There may be a case where the bus masters compete for access to the main memory 3. Therefore, for example, a bus arbitration circuit (not shown) is provided, and the CPU 1, the DMA controller 4, and the refresh controller 5 are assigned a priority order to access the main memory 3. Then, the bus arbitration circuit monitors all access requests to the main memory 3, arbitrates the access conflicts when they conflict, and permits the bus master with the highest priority to access the memory 3. . When the above-mentioned access conflict occurs, the bus arbitration circuit normally prioritizes the access from the refresh controller 5 and then the access from the DMA controller 4. Therefore, the access from the CPU 1 has the lowest priority. Hereinafter, this situation will be described with reference to the drawings.

FIGS. 7A and 7B are diagrams showing two examples of access modes of the main memory 3 in the conventional computer system shown in FIG. However, FIG. 7A is a diagram showing a case where only the CPU 1 accesses the main memory 3, and FIG. 7B is a diagram showing that the DMA controller 4 and the refresh controller while the CPU 1 is accessing the main memory 3. 5 interrupts and main
It is a figure which shows the case where the memory 3 is accessed. In the figure, “* CPUREQ” indicates a request for access from the CPU 1 to the main memory 3 by “* DMARK”.
EQ ”is from the DMA controller 4 to the main memory 3
, “* REFREQ” represents an access request from the refresh controller 5 to the main memory 3, and “BUS” represents a bus master using the bus 6. Also,"*"
Is a code indicating that "L" is active.

First, as a situation in which the CPU 1 accesses the main memory 3, the cache memory of the cache system 2 does not contain the data and instructions necessary for the CPU 1 to execute the program. Consider a case where the CPU 1 newly transfers one line of data or instruction including an instruction from the main memory 3 to the cache system 2. And
At this time, if the memory cycle of the main memory 3 is set to 1 cycle in order to transfer the above-mentioned 1-line data or instruction from the main memory 3 to the cache system 2 via the bus 6, 8 cycles are required. I shall.

When the CPU 1 makes an access to the main memory 3 for the above eight cycles, as shown in FIG. Access is necessarily completed in eight consecutive cycles (see the contents of "BUS"). The performance of the CPU 1 in this case is defined as 8 cycles / 8 cycles × 100 = 100 (%).

Next, as shown in FIG.
While the main memory 3 is being accessed in the same manner as above, the DMA controller 4 requests access to the main memory 3 for four cycles, and the DMA controller 4 performs access. Consider the case where the refresh controller 5 requests access to the main memory 3 for one cycle during the operation (see the level changes of "* DMAREQ" and "* REFREQ"). In this case, the access priority of each buster to the main memory 3 is set as * CPUREQ <* DMAREQ <* REFREQ by the bus arbitration circuit as described above, and therefore the access is requested from the DMA controller 4. At that time, the CPU 1 accesses the DMA controller, the access right is transferred from the refresh controller 5, and the access right is transferred from the DMA controller 4 to the refresh controller 5.

As a result of the above, in this case, by the time all the accesses to the CPUGA main memory 3 are completed,
During the access, four cycles of access by the DMA controller 4 and one cycle of access by the refresh controller 5 are interrupted, so that 13 cycles are required as a whole (see the contents of "BUS"). Therefore, the performance of the CPU 1 in this case is 8 cycles / 13 cycles × 100≈62 (%), which is about 38% compared with the case shown in FIG.
Also decreases.

As described above, in the conventional computer system, while the CPU 1 is accessing the main memory 3, the main memory 3 is accessed by another bus master having a higher priority. Then CP
There was a drawback that the performance of U1 would decrease.

It is an object of the present invention that, while the CPU is accessing the main memory, even if an access factor from another bus master having a higher priority occurs in the main memory, the CPU still has to access the main memory. Is to provide a computer system capable of maintaining high performance.

[0016]

According to the first and second aspects of the present invention, a CPU, a main memory of the CPU, and a CPU other than the CPU for accessing the main memory are all provided. Computers with other bus masters
Assuming a system.

A first invention is a main memory comprising a multiport memory having a random access port and at least one serial access port,
It has a device connected to the serial access port of the main memory. Then, the CPU accesses the main memory via the random access port, and controls so that data transfer from the main memory to the device is performed via the serial access port. .

A second invention according to claim 2 has a main memory provided with a random access port and a serial access port, as in the first invention, and as the bus master. , A DMA controller connected with a random access port and a serial access port of the main memory.
All the controllers that support DMA transfer correspond to the DMA controller, for example, SCSI (Sma
ll Computer System Interface) controller etc. are also included.

The DMA controller controls access to the main memory through the random access port, and transfers data to and from the main memory by serial access of the main memory. -Do it through the port.

[0020]

According to the first aspect of the invention, the CPU can burst transfer data from the main memory to the device via the serial access port of the main memory. In the C
Even if the bus master having a higher priority than the PU accesses the random access port of the main memory, the data transfer can be executed without interruption. Therefore, the performance of the CPU can be improved.

Further, in the second invention, since the DMA controller transfers data to and from the main memory via the serial access port of the main memory, it is higher than itself such as a refresh controller. Even if the bus master having the priority order accesses the random access port of the main memory, the situation in which the data transfer is interrupted can be avoided. Therefore, the device connected to the DMA controller can perform the data transfer at high speed through the DMA controller by, for example, the synchronous transfer method, and the system performance is improved.

[0022]

Embodiments of the present invention will now be described in detail with reference to the drawings. 1 is a block diagram showing a hardware configuration of a computer system according to a first embodiment of the present invention.

As shown in the figure, the computer system according to the first embodiment has a CP
U11, cache system 12, main memory 1
3, a DMA controller 14, and a refresh controller 15. However, as the main memory 13 among them, a multi-port memory having one serial access port in addition to a normal random access port is used (hereinafter,
This is referred to as "main memory [MPM] 13" in order to clarify its function as a multi-port memory and to distinguish it from the conventional main memory 3 having only a random access port).

This computer system is
Of the series of data and instructions required for the CPU 11 to execute the program stored in the memory [MPM] 13, valid data and instructions that are likely to be accessed by the CPU 11 are stored in an internal cache memory (not shown). No.), and has a cache system 12 that speeds up the processing of the CPU 11. The cache memory manages data and instructions in units of a predetermined bit length (line), and data transfer from the main memory [MPM] 13 to the cache memory is performed in units of one line (line). fill). Since this one line is a predetermined multiple of the data bus width of the bus 16, the data transfer requires a plurality of cycles. Further, this computer system, as a bus master for accessing the main memory [MPM] 13, a DM for controlling data transfer with an external storage device (not shown) in addition to the CPU 11.
A controller 14, further main memory [MP
M] 13 has a refresh controller 15 for periodically refreshing.

Of the above blocks, the CPU 11 except the cache system 12, the DMA controller 14, and the refresh controller 15 are the bus 1
Random main memory [MPM] 13 via 6
Connected to access port. Furthermore, CPU1
1 is connected to the cache system 12 by a dedicated bus 17. Also, the cash system 12
The serial ports of the main memory [MPM] 13 are connected to each other by a serial data input / output line 18.

That is, in this computer system, three CPUs 11, the DMA controller 14, and the refresh controller 15 are bus masters due to the above-described connection form, and these bus masters access the main memory [MPM] 13. Control of
Through its random access port. By the access control, the CPU 11 transfers the group of data and instructions from the main memory [MPM] 13 to the cache system 12 in the unit of one line, and connects the serial access ports to each other. This is performed via the serial data input / output line 18.

Subsequently, the operation and CPU of the computer system according to the first embodiment configured as described above
Consider 11 performances. 2A and 2B are diagrams showing two examples of access modes of the main memory 13 in the computer system shown in FIG. FIG. 7A is a diagram showing a case where only the CPU 11 accesses the main memory [MPM] 13, and FIG.
It is a figure which shows the case where the controller 14 and the refresh controller 15 interrupt and accessed the main memory [MPM] 13. In the figure, "* C
"PUREQ" is from the CPU 11 to the main memory [MP
M] 13 request for access to "* D MARE
Q ”is from the DMA controller 14 to the main memory [M
PM] 13 requesting access to "* REFRE
“Q” indicates a request for access to the main memory [MPM] 13 from the refresh controller 15 and “BU”.
“S” is the type of bus master that uses the bus 16 to access the random access port of the main memory [MPM] 13, and “SOUT” is the serial access of the main memory [MPM] 13. -Indicates the usage status of each port.

First, as in the case of FIG. 7A described above, the CPU 11 causes the main memory [MPM] 13 to the cache system 12 to collect a group of data and instructions (line) including target data and instructions. Data) is newly transferred. That is, at this time, the main memory [MPM] 1
The total amount of a group of data and instructions transferred from the serial access port 3 of the third embodiment to the cache system 12 through the serial data input / output line 18 is the time based on the memory cycle of the main memory [MPM] 13. It is equivalent to 8 cycles when converted into quantity.

As shown in FIG. 2A, the CPU 11 is
When transferring a group of data or instructions for the above eight cycles, first, in order to cause the main memory [MPM] 13 to perform the above transfer via the serial data input / output line 18, the main memory [MPM] 13 is transferred via the bus 16. Memory [MP
[M] 13 random access ports 1 are accessed for one cycle (see the level change of “* CPUREQ” and the content of “BUS”). And the CPU 11
After that, the random access port 16 is not used at all, and the serial data input / output line 18 is used to transfer a group of data or instructions for 8 cycles from the main memory [MPM] 13 to the cache system 12. Done through. Then, during this period, if there is no access to the main memory [MPM] 13 from other bus masters, the entire access is equivalent to one cycle to the random access port of the main memory [MPM] 13. Add the access time and 8 cycles in which the serial access port of the main memory [MPM] 13 is used to transfer a group of data and instructions from the main memory [MPM] 13 to the cache system 12. Completed in 9 cycles (Contents of "BUS" and "SOUT"
See state). In this embodiment, the performance of the CPU 11 in this case is defined as 9 cycles / 9 cycles × 100 = 100 (%).

When the performance of this computer system is compared with that of the conventional computer system, in the conventional computer system, access to the entire CPU 11NO is completed in 8 cycles. This computer system requires 9 cycles, which is one cycle longer than that. Thus, the performance of this computer system appears to be lower than that of conventional computer systems, but this idea does not hold at all. This is because in the main memory [MPM] 13, the serial access port can be operated asynchronously with the random access port, and in general, data transfer using the serial access port is random. This is because it can be performed at a much higher speed than when the access port 16 is used. Therefore, one cycle of the serial access port of the main memory [MPM] 13 in this embodiment is shorter than one cycle of the main memory 3 in the conventional computer system described above. Therefore, the data transfer that requires 9 cycles in the present embodiment is more than the data transfer of 8 cycles when the random access port 16 is used in the conventional computer system shown in FIG. Actually, it can be performed in a short time, and the performance of the CPU 11 in the computer system of the first embodiment is similar to that of the CPU of the conventional computer system.
Substantially higher than 1.

Next, as shown in FIG. 2B, consider a case where the same operation as that shown in FIG. 7B is performed in this embodiment. In this case, the CPU 11 first makes an access for one cycle to the random access port 16 of the main memory [MPM] 13 via the bus 16, and the main memory [MPM] 13 to the cache system 12 is accessed. While transferring a group of data and instructions to the DMA controller 14 through the serial access port for up to 3 cycles,
Requests the main memory [MPM] 13 to transfer data for 4 cycles via the bus 16.
While the DMA controller 14 is performing the data transfer, when the refresh controller 15 issues a refresh access request for one cycle to the main memory [MPM] 13 via the bus 16 ( (See the level changes of “* DMAREQ” and “* REFREQ”). In this case, the DMA controller 14 and the refresh
Main memory [MPM] 13 by controller 15
The priority of access to the bus master is set by the bus arbitration circuit (not shown) as * CPUREQ <* DMAREQ <* REFREQ.
The access to the main memory [MPM] 13 by 4, 15 is completed in a time of 5 cycles including a time of 4 cycles by the DMA controller 14 and a time of 1 cycle by the refresh controller 15 ( See the contents of "BUS").

In this case, the access to the main memory [MPM] 13 corresponding to the time for the above five cycles is performed through the random access port as before,
During this time, a group of data or instructions for 8 cycles from the main memory [MPM] 13 to the cache system 12 is transferred to the main memory [MPM] 1
Through the serial access port of 3 and the random access port of the main memory [MPM] 13, the access of the CPU 11 is 9 cycles, just like the previous case. (See the contents of "BUS" and the state of "SOUT"). Therefore, the performance of the CPU 11 in this case is also 9 cycles / 9 cycles × 100 = 100 (%). In this way, the CPU 11 causes the main memory [M
PM] While controlling the data transfer from 13 to the cache system 12, another higher priority bus
From the mask to the main memory [MP
M] 13 random access, even if an access to a port occurs, only the CPU 11 can access the main memory [M
The same performance is maintained as when the PM] 13 is exclusively used.

In this computer system, when the CPU 11 performs IPL (Initial Program Loading), I / O access, exception processing, etc., the main memory [MPM] is used instead of the cache system 12. ] Since 13 is randomly accessed, the required performance is temporarily not maintained. However, the IPL is performed only at power-on, and the frequency of I / O access and exception handling during system operation is extremely low, and they do not contribute to the overall performance of this computer system. It doesn't really matter.

Next, FIG. 3 is a block diagram showing the hardware configuration of the computer system of the second embodiment of the present invention. As shown in the figure, the computer system according to the second embodiment has a CPU 21, a cache system 22, a main system, as in the first embodiment.
The multi-port comprises a memory 23, a DMA controller 24, and a refresh controller 25, and the main memory 23 has one serial access port in addition to a normal random access port.・ Memory is used (hereinafter, the first
In the same manner as in the embodiment of
M] 23 ”).

The blocks 21 to 25 are connected to each other via a bus 26 and a random access port of the main memory [MPM] 23. That is, in this second embodiment, the cache system 22
Are connected to the random access port of the main memory [MPM] 23 via the bus 26. on the other hand,
Serial access of main memory [MPM] 23
The port and the DMA controller 24 are connected by a serial data input / output line 27. That is, in this computer system, the CPU 21 and the refresh controller 25 are connected to each other by the above bus connection form.
Access to the main memory [MPM] 23 by one bus master is performed via the bus 26 via its random access port as in the conventional case. On the other hand, the DMA controller 24 is
Data transfer between the memory [MPM] 23 and an external storage device (not shown) is performed via the serial data input / output line 27.

Subsequently, the operation and CPU of the computer system according to the second embodiment configured as described above
21 performances will be described. FIGS. 4A and 4B are diagrams showing two examples of access modes of the main memory 23 in the computer system of the second embodiment shown in FIG. Then, FIG. 4A is an access mode corresponding to FIG. 2A and FIG. 4B is an access mode corresponding to FIG. In the figure, "* CPU
REQ ”is the main memory [MPM] from the CPU 21.
23, the access request for "23
DMA controller 24 to main memory [MPM]
The access request for 23 is "* REFREQ"
A request for access from the refresh controller 25 to the main memory [MPM] 23 is issued by "BUS".
Specifies the type of bus master that uses the random access port of the main memory [MPM] 23 as "SOU.
“T” represents the usage status of the serial access port 27 of the main memory [MPM] 23.

As shown in FIG. 4A, the CPU 21 is
When transferring a group of data or instructions for 8 cycles from the main memory [MPM] 23 to the cache system 22, the main memory [MPM] 23 is accessed for 8 cycles through a random access port. Perform (see "* CPUREQ" level change). At this time, if no access to the main memory [MPM] 23 from another bus master occurs, the entire access is completed in a time of 8 cycles (refer to the content of "BUS"). ). Therefore, the performance of the CPU 21 in this case is defined as 8 cycles / 8 cycles × 100 = 100 (%).

Next, while the CPU 21 is performing 8-cycle access to the main memory [MPM] 23 as in the case of FIG. 4A, the DMA controller 24 causes the main memory [MPM] 23 to access. Consider a case where data transfer for 4 cycles is performed between the memory 23 and the external storage device. Also, while the DMA controller 24 is performing the above access, the refresh controller 2
It is assumed that one cycle requires access from 5 to the main memory [MPM] 23.

In this case, as shown in FIG.
When the data transfer for the above four cycles is performed, the A controller 24 first requests the main memory [MPM] 23 for data transfer using the serial access port. For one cycle (see the level change of “* DMAREQ” and the content of “BUS”). And DM
After that, the A controller 24 transfers data for four cycles between the main memory [MPM] 23 and the external storage device to the serial memory instead of the random access port of the main memory [MPM] 23. -Perform through the access port (see "SOUT" state). Then, during this data transfer, the refresh controller 25 requests the bus arbitration circuit for the right to use the bus 36.

In such a case, the access priority of each bus master to the main memory [MPM] 23 is
Since * CPUREQ <* DMAREQ <* REFREQ is set by the bus arbitration circuit, when the DMA controller 24 requests the bus arbitration circuit to use the bus 36, the access of the CPU 21 is immediately prohibited. Then, the random access port of the main memory [MPM] 23 is accessed by the DMA controller 24, and data transfer via the serial access port is started. Subsequently, when the refresh controller 25 makes a request for use of the bus 36 to the bus arbitration circuit, the use request is immediately granted, and the refresh controller 25 allows a random access of the main memory [MPM] 23. The access port is accessed for one cycle.

In this example, at the time of this access, C
The access of the PU 21 to the main memory [MPM] 23 is completed, and the DMA controller 24 has already started the data transfer via the serial access port of the main memory [MPM]. Therefore, CP
By the time U21 completes all accesses to the main memory [MPM] 23, the main memory [MPM] 23
M] D for 23 random access ports
One cycle of access by the MA controller 24 for data transfer between the external storage devices and main memory [MP by the refresh controller 25
Access for one cycle for refreshing M] 23 is interrupted, and the CPU 21 requires 10 cycles as a whole to transfer the above data from the main memory [MPM] 23 to the cache system 22. (See the contents of "BUS"). Therefore, the performance of the CPU 21 in this case is 8 cycles / 10 cycles × 100 = 80 (%), and as shown in FIG. 4A, only the CPU 21 exclusively accesses the main memory [MPM] 23. The performance is reduced by 20% as compared with the case of performing.
However, the rate of performance degradation in this case is
It is smaller than the degradation rate (about 38%) in the conventional computer system described above.

In the computer system of the second embodiment, the CPU 21 executes the main memory [MPM] 23 instead of the cache system 22 in order to perform IPL, I / O access, exception handling, and the like. With random access, there is almost no concern that the required performance will not be maintained temporarily.
This is because the DMA controller 24 transfers data between the main memory [MPM] 23 and the external storage device by serial access of the main memory [MPM] 23.
This is because it can be performed only by serial access via the port. Therefore, according to this computer system, access from the CPU 21 or the refresh controller 25 causes the main memory [MP
M] Even if the random access port of 23 is occupied, the serial access port constantly secures the data transfer path to and from the external storage device.
For example, as the DMA controller 24, a SCSI controller (Small Computer Systems Interface Control) is used.
ller) is used, the main memory [M
The data transfer between the PM] 23 and the external storage device can be performed by a high-speed synchronous transfer method.

FIG. 5 is a block diagram showing the hardware configuration of a computer system according to the third embodiment of the present invention. As shown in the figure, the computer system according to the third embodiment includes a first CPU 31a and a second CPU 31a.
CPU 31b, first cache system 32a,
The second cache system 32b, main memory [MPM] 33, first DMA controller 34a, second DMA controller 34b, and refresh
It is composed of a controller 35. Unlike the first and second embodiments, the main memory 33 has four serial ports in addition to the normal random access port.
Multiport memory with access ports is used. Then, each of the above blocks is connected to the random access port or serial access port of the main memory [MPM] 33 in the same manner as in the first and second embodiments.

In other words, this computer system has the first and second cache systems 32a and 32b for the four individual serial access ports provided in the main memory [MPM] 33, respectively.
And the first and second DMA controllers 34a, 34
b is connected by an individual serial data input / output line 37. The main memory [M] for performing serial data transfer between the first and second cache systems 32a and 32b and the main memory [MPM] 33.
The access control for the PM] 33 is performed by the first and second CPUs 31a and 31b via the bus 36 to the random access port of the main memory [MPM] 33. Then, it is not always necessary to randomly access the main memory [MPM] 33 in blocks (first and second cache systems 32a, 32b, first and second DMAs).
The controllers 34a, 34b) are connected to the main memory [M
PM] 33, the bus masters of the first and second CPUs 31a and 31b and the first and second DMA controllers 34a and 34b are connected to the individual serial access ports of the bus 36. ,Maine·
The frequency of competing the use of the random access port of the memory [MPM] 33 can be significantly reduced.
Not only the CPUs 31a and 31b, but also the performance of the entire system can be significantly improved.

Although the embodiments of the present invention have been described in detail above, the present invention is not limitedly applied to the computer system requiring the refresh controller as shown in each embodiment. , Of course, the main
The same can be applied to a computer system using a static RAM as a memory [MPM] (no refresh controller is required).
Further, the bus master is not limited to the device shown in the above embodiment.

[0046]

As described above in detail, according to the present invention, the multi-port memory having the serial access port in addition to the random access port is used as the main memory of the CPU, In addition, a device capable of performing data transfer with the main memory through the serial access port under the control of the CPU is configured to be connected to the serial access port. , The contention of the CPU and other bus masters on the random access port of the main memory is eliminated or reduced. As a result, the performance of the CPU is improved and the performance of the entire system is also improved.

Since the DMA controller can transfer data via the serial port of the main memory, the DMA controller can transfer data without being disturbed by the access to the main memory such as the refresh controller. It becomes possible to easily construct a computer system capable of performing high-speed synchronous transfer.

[Brief description of drawings]

FIG. 1 is a block diagram showing a hardware configuration of a computer system according to a first embodiment of the present invention.

2A and 2B are diagrams showing two forms of access to the main memory in the computer system according to the first embodiment shown in FIG. 1, and FIG. 2A is a diagram in which only the CPU accesses the main memory. Figure showing the case, (b) is CP
While accessing U, refresh the DMA controller and
It is a figure which shows the case where a controller interrupts and accesses the main memory.

FIG. 3 is a block diagram showing a hardware configuration of a computer system according to a second embodiment of the present invention.

4A and 4B are diagrams showing two forms of access to the main memory in the computer system according to the second embodiment shown in FIG. 3, in which FIG. 4A shows only the CPU accessing the main memory. Figure showing the case, (b) is CP
While accessing U, refresh the DMA controller and
It is a figure which shows the case where a controller interrupts and accesses the main memory.

FIG. 5 is a block diagram showing a hardware configuration of a computer system according to a third embodiment of the present invention.

FIG. 6 is a block diagram showing a hardware configuration of a conventional general computer system.

FIG. 7 is a diagram showing two forms of access to the main memory in the conventional computer system shown in FIG. 6, and FIG. 7A is a diagram showing a case where only the CPU accesses the main memory; (B) is a diagram showing a case where the DMA controller and the refresh controller interrupt the CPU while accessing the main memory.

[Explanation of symbols]

11, 21, 31a, 31b CPU 12, 22, 32a, 32b Cache system 13, 23, 33 Main memory [MPM] (multi-port memory) 14, 24, 34a, 34b DMA controller 15, 25, 35 Refresh・ Controller 16, 26, 36 bus 17, 27, 37 data input / output line

Claims (2)

[Claims] 1. A computer system having a CPU, a main memory of the CPU, and a bus master other than the CPU for accessing the main memory, wherein a random access port and at least one serial access port are provided. A main memory comprising a multi-port memory having a port, and a device connected to a serial access port of the main memory, wherein the CPU has the main memory via the random access port. And controlling the transfer of data from the main memory to the device via the serial access port. 2. A computer system having a CPU, a main memory of the CPU, and a bus master other than the CPU for accessing the main memory, wherein a random access port and at least one serial access port are provided. A main memory comprising a multi-port memory having a port, and a DMA controller connected as a bus master together with a random access port and a serial access port of the main memory, wherein the DMA controller is Access control to the main memory is performed via the random access port, and data transfer to and from the main memory is performed via a serial access port of the main memory. Computer system to do.