JP2003263363A - Memory control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-performance inexpensive memory control circuit capable of surely improving the memory band width without reducing the effective band width and without increasing a data buffer inside the memory control circuit. <P>SOLUTION: A demand signal for memory access is inputted from each DMA master 1a-1e, and a master for performing memory access corresponding to the present order of priority at timing when the memory is not accessed (not in the busy state) is selected, and an enabling signal is outputted. A demand address of the selected master is outputted to a subsequent SDRAM control circuit. In addition, the demand address of the selected master is outputted to the subsequent SDRAM control circuit, and an access start signal for showing the occurrence of the memory access is outputted. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control circuit, and more particularly to a memory control circuit for general memory storage devices, digital copiers, scanners, printers, and devices that use memories in FAX.

[0002]

2. Description of the Related Art There is a term "memory bandwidth" as a term indicating performance during memory access. Generally, the bandwidth is a synchronous semiconductor memory such as SDRA.
In M, it is expressed as operating frequency × data bus width, assuming that data is exchanged once in one clock. For example, the operating frequency is 100MHz and the bus width is 8
With bits, the bandwidth is 100 MB / sec.
However, access to the SDRAM needs to be performed in accordance with a fixed procedure, such as issuing an active command designating a row address, then issuing a read or write command designating a column address, and securing a precharge time. There is a time (hereinafter, referred to as a lost clock) during which the input / output of is not performed, and the actual effective bandwidth becomes a smaller value.

In addition, SDRAM has an access method called burst access in which data input / output is continued for each clock, and one access to the same row address is performed.
A method that is realized by a combination of issuing an active command once (hereinafter referred to as transaction) and issuing a read or write command multiple times, and by setting in an SDRAM internal register called a mode register at the time of initialization, at the time of one access There is a method of using the default function of the SDRAM that uniquely determines the number of data to be handled. The longer the burst access in one transaction, the better the effective bandwidth. However, in order to continuously input and output such a large amount of data, a data buffer for temporarily storing that much data is required on the memory control side, and the circuit scale becomes large and expensive.

As a simple method of increasing the bandwidth, there is a method of increasing the operating frequency or increasing the data bus width. Raising the operating frequency is general purpose SDR
Although AM has a limit in specifications, increasing the data bus width is relatively easy except for the problem of the number of terminals. For example, if you want to simply double the bandwidth, set the data bus width to 8
By changing from 16 bits to 16 bits, numerically 200MB
/ Sec. However, when the data buffer for burst access is the same amount on the memory control side, the length of burst access can only be halved, and the proportion of lost clocks in one transaction increases by that amount, resulting in an increase in execution bandwidth. Cannot simply be doubled.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the problems of the prior art. In a multi-master system, the number of memory access requests is large, so a configuration having a plurality of ports is effective, and a simple bus is used. Compared with the method of widening the width,
An object of the present invention is to provide a memory control circuit which has a high performance and a low cost, which surely improves the memory bandwidth without reducing the effective bandwidth and without increasing the data buffer inside the memory control circuit.

Further, it becomes possible to alternately allocate to different ports by burst access, the master side does not need to be aware of the memory address for the request, and the waiting time of the memory request is short, so that the memory band can be surely secured. An object of the present invention is to provide a high performance memory control circuit capable of improving the width.

Furthermore, it is possible to provide a high-quality memory control circuit capable of varying the number of ports according to the amount of memory used and the number of masters, and capable of adapting a flexible configuration to various systems. To aim.

[0008]

To achieve the above object, a memory control circuit according to the present invention arbitrates memory access requests from a plurality of masters and controls access to a connected memory. Multiple ports connected to multiple independently accessible memories, selectors for allocating the ports to be accessed by distribution bits that are predetermined bits of each memory access request address from multiple masters, and connected for each port Arbitration means for arbitrating memory access requests from a plurality of masters distributed by the selector, and a signal for accessing the memory according to the contents of the memory access request of the master determined by the arbitration means connected for each port. And a memory access control means for controlling.

Further, the distribution bit is a bit located at a higher position than a few lower bits of an address for memory access used for burst access.

Further, it is characterized in that a port to be used can be arbitrarily selected from a plurality of ports, and the selector is configured to distribute the memory access request according to the setting.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of a memory control circuit according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a block diagram showing a configuration example of a memory control circuit of the present invention. The memory control circuit of the present invention includes a DMA master 1
a to 1e, selectors 2a to 2e, arbitration circuits 3a, 3
b, SDRAM control circuits 4a, 4b, and SDRAM 5.

The DMA masters 1a to 1e output the requested address in order to request the address. Selector 2a
To 2e are request addresses from the DMA master 2
Lower 3 bits [2: of 9-bit bus [28: 0]
0] is used for burst access of the SDRAM, and the lower 4th bit [3] is connected to the port designating circuit as a distribution bit for determining to which port the memory request is distributed.

The arbitration circuits 3a and 3b are equivalent circuits, and are circuits that perform round-robin arbitration. The master to access the memory is selected and the permission signal is output.

The SDRAM control circuits 4a and 4b are equivalent circuits, and divide the request address input from the arbitration circuit into a row address, a column address, and a bank address corresponding to the SDRAM, which is a semiconductor memory, and output it to the SDRAM address. Furthermore, S connected by two ports
The DRAM 5 inputs / outputs data.

Next, the operation of the configuration example will be described with reference to the block diagram of FIG. In FIG. 1, a request signal for memory access is input from each DMA master,
On the other hand, at a timing when the memory is not being accessed (not in a busy state), the master to access the memory is selected according to the current priority order and the permission signal is output. Further, the request address of the selected master is output to the SDRAM control circuit in the subsequent stage. Furthermore, the latter SD
The request address of the selected master is output to the RAM control circuit, and the access start signal indicating the occurrence of memory access is output.

According to the access start signal from the arbitration circuit,
SDRAM control signals (/ RAS, / CAS, / WE, etc.)
Is output. The amount of connected memory is 256MB each, and S
2 address lines are input to the DRAM control circuit.
It consists of 8 bits.

2 which is the request address from the DMA master
Lower 3 bits [2: of 9-bit bus [28: 0]
0] is used for the burst access of the SDRAM, and is connected to the port designation circuit as a distribution bit for deciding to which port the memory request of [3] of the fourth bit from the lower order should be distributed. Intentionally the highest [28]
However, in this case, the request address of the DMA master needs to be distributed in consideration of the port, otherwise the bandwidth cannot be improved.

FIG. 2 is a diagram showing a timing chart of control signals input to and output from the SDRAM control circuit. In the present embodiment, the SDRAM is used with the burst length set to 2 in the mode register having the default function. The SDRAM control circuit issues a maximum read / write command for every two clocks in response to one active command, thereby realizing a maximum of eight consecutive burst accesses.

The timing chart of FIG. 2 is a diagram of 8 consecutive burst writes, but the data bus (DATA
[7: 0]) period when no data enters (loss clock)
There are 6 clocks, and the total number of clocks required for access is 14 clocks in addition to 8 clocks during the period when data is present. Calculating the effective bandwidth, operating frequency 100 MHz × data bus width 1 byte ×
It becomes about 57 MB / sec at (8 clocks / 14 clocks).

In order to increase the bandwidth, an SDRAM control circuit having a double data bus width of 16 bits is prepared. In that case, the data buffer for temporarily storing data on the control circuit side or the master side is 8 bits long. With the same amount, the amount of data input / output to / from the SDRAM at the same time is the same as that at 8 bits, so the number of bursts must be halved, and the number of clocks used can be changed from the timing chart of FIG. 2 to two write commands. The required 4 clocks are subtracted from the number of clocks required for the entire access. In that case, the effective bandwidth is 100 MHz operating frequency.
z × data bus width 2 bytes × (4 clocks / 10 clocks), which is about 80 MB / sec, and the ratio of lost clocks increases, and it does not simply double. In the embodiment of the present invention,
Since it has two independently controllable SDRAM ports, the ratio of lost clocks is the same as in FIG. 2, and the effective bandwidth is doubled to 114 MB / sec.

The timing chart of FIG. 2 is a diagram of a burst write of eight consecutive bursts.
7: 0]), there are 6 clocks (loss clock) during which no data is input, and the total number of clocks required for access is 1 including 8 clocks during which data is present.
It takes 4 clocks. When we calculate the effective bandwidth,
Operating frequency of 100 MHz × data bus width of 1 byte (8 clocks / 14 clocks) gives about 57 MB / sec.

In order to increase the bandwidth, an SDRAM control circuit having a double data bus width of 16 bits is prepared. In that case, the data buffer for temporarily storing data on the control circuit side or the master side is 8 bits long. With the same amount, the amount of data input / output to / from the SDRAM at the same time is the same as that at 8 bits, so the number of bursts must be halved, and the number of clocks used can be changed from the timing chart of FIG. 2 to two write commands. The required 4 clocks are subtracted from the number of clocks required for the entire access. In that case, the effective bandwidth is 100 MHz operating frequency.
z × data bus width 2 bytes × (4 clocks / 10 clocks), which is about 80 MB / sec, and the ratio of lost clocks increases, and it does not simply double. Since the embodiment of the present invention has two independently controllable SDRAM ports, the ratio of lost clocks is the same as in FIG. 2, and the effective bandwidth is doubled to 114 MB / sec. Further, in the present embodiment, the number of memory ports is two, but it is 4, 8
There is also an example in which the memory is set to multiple ports, and distributed bits and multiple bits are used.

FIG. 3 is a diagram showing the internal structure of each selector. The selectors are the request mask circuits 10a, 10b,
It is composed of a port designating circuit 11 and a request address resizing circuit 12.

The request masks 10a and 10b are equivalent circuits, and mask the memory request signal from the DMA master according to the mask designating signal from the port designating circuit and output it to the arbitration circuit 1a or 1b.

The port designating circuit 20 outputs a mask designating signal to the request masking circuit in accordance with the distribution bit and the state of the single port designating signal.

The request address resizing circuit 13 outputs D when the through instruction signal from the port designating circuit is active.
Request address [27: from the MA masters 1a and 1b]
28 bits of 0] are output to the arbitration circuits 3a and 3b. When the through instruction signal is inactive, [28: 4], [2:
0] and output in 28 bits.

The operation of the configuration example will be described with reference to the block diagram of FIG. When the single port instruction signal is inactive, the request mask circuit 10 is activated according to the state of the distribution bit.
Either one of the mask support signals output to a and 10b is actively output. In this case, the DMA masters 1a-1
When the memory request signal from b becomes active, the output of either of the request mask circuits 10a and 10b becomes active. Further, when the single port instruction signal is active, the mask instruction is always output to the request mask circuit 10b, and the request mask circuit 10a always outputs a signal that makes the mask state unmasked. In that case, the through address signal is output to the request address resizing circuit 12 so that the request address from the DMA master is output to the arbitration circuits 3a and 3b as it is. As a result, it is possible to flexibly support a system that requires a small amount of connection memory and a small bandwidth.

When the through instruction signal from the port designation circuit is active, 28 bits of [27: 0] of the request address from the DMA master are output to the arbitration circuits 3a and 3b. When the through instruction signal is inactive, [28:
4] and [2: 0] are continuously output in 28 bits.

[0029]

Since the number of memory access requests is large in the multi-master system, the configuration having multiple ports is effective.
Compared with the method of simply increasing the bus width, the memory bandwidth is surely improved without lowering the effective bandwidth and without increasing the data buffer inside the memory control circuit. It becomes possible to provide a control circuit.

By burst access, it is possible to alternately allocate to different ports, the master side does not need to be aware of the memory address and make a request, and the waiting time of the memory request is short, so that the memory bandwidth can be reliably ensured. It is possible to provide a high performance memory control circuit that can be improved.

The number of ports can be made variable according to the amount of memory used and the number of masters, and it is possible to provide a high quality memory control circuit capable of flexibly adapting the configuration to various systems. Become.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an example of an embodiment of a memory control circuit according to the present invention.

FIG. 2 is a diagram showing a timing chart of control signals input to and output from an SDRAM control circuit according to the present invention.

FIG. 3 is a configuration diagram showing an internal configuration of each selector according to the present invention.

[Explanation of symbols]

1a to 1e DMA master 2a-2e selector 3a, 3b Arbitration circuit 4a-4b SDRAM control circuit 5 SDRAM

Claims (3)

[Claims] 1. A memory control circuit for arbitrating memory access requests from a plurality of masters and controlling access to a connected memory, a plurality of ports connected to a plurality of independently accessible memories, and a plurality of masters. A selector for allocating a port to be accessed according to a distribution bit which is a predetermined bit of each memory access request address from the above, and an arbitration means for arbitrating memory access requests from a plurality of masters distributed by the selector connected to each port. A memory access control means for controlling a signal for accessing the memory according to the content of the memory access request from the master connected to each port and determined by the arbitration means. 2. The memory control circuit according to claim 1, wherein the distribution bit is a bit located at an upper position of a few lower bits of an address for memory access used for burst access. 3. The memory according to claim 1, wherein a port to be used can be arbitrarily selected from the plurality of ports, and the selector is configured to distribute the memory access request according to the setting. Control circuit.