JP2002169721A - Information processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide technology for deterring a free cycle from being generated when data of at least two or more memories are accessed. SOLUTION: A data strobe signal controller 2 is connected to a storage controller 1 by a common DQS signal line L1 and also connected to memories 3a, 3b, and 3c by DQS signal lines L2a, L2b, and L2c individually. The data strobe signal controller 2 receives from the common DQS signal line L1 the data strobe signal sent from the storage controller 1 and sends it to one of the DQS signal lines L2a, L2b, and L2c connected to a memory to be accessed among the memories 3a, 3b, and 3c. The data strobe signal sent from the memory among the memories 3a, 3b and 3c to be accessed is received from one of the DQS signal lines L2a, L2b, and L2c and sent to the common DQS signal line L1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a technique for controlling reading and writing to and from a memory, and more particularly to a technique for controlling the input and output of a data strobe signal to and from a memory when a DDR SDRAM is used as a memory element.

[0002]

2. Description of the Related Art With the rapid increase in the speed of microprocessors in recent years, the speed of memory elements used as memories of computer products or information processing products has been increasing. For example, there is a memory element called a DDR SDRAM. Whereas conventional SDRAM inputs and outputs data once per cycle, DDR S
In a DRAM, data transfer rate is doubled by inputting and outputting data twice in one cycle. DDR
In the SDRAM, a control signal called a data strobe signal (DQS signal) is newly provided to input and output data twice in one cycle. For example, when data is written to the memory, the storage controller inputs the DQS signal to the memory together with the two data to be written, so that the memory receives data at the rising edge and the falling edge of the DQS signal in one cycle. And writes to the specified address. Thus, the memory inputs data twice in one cycle. When data is read from the memory, the memory reads two data from the designated address and outputs a DQS signal together with the data. In this case, the read data and the DQS signal are input to the storage controller, and the storage controller receives the data at the rising and falling edges of the DQS signal in one cycle. Thus, the memory outputs data twice in one cycle.

The DQS signal is transmitted by a DQS signal line connecting the memory and the storage controller, but before the DQS signal is transmitted, that is, one time (cycle) at which data is read from the memory. It is defined that the signal level of the signal flowing through the DQS signal line is maintained at “0” during a period (a period called preamble) of one cycle before the cycle. preamble
Thereafter, the DQS signal is transmitted via the DQS signal line, the value of the data line is determined at the rise and fall of the DQS signal, and the storage controller reads data from the memory.

A plurality of memories share the same data line,
In addition, when the DQS signal line is also shared, an interval of at least one cycle is always provided when data access (read) is performed from one access request issuing device to one memory and then data access (read) is performed to another memory. There is a need. In other words, after reading data from a memory from the access request issuing device and then reading data from another memory, the preamble is read one cycle before the access to the other memory.
It is necessary to set the signal level of the DQS signal line to “0” by providing a period of “le”. During this preamble period, data cannot be accessed for any memory. Therefore, even when data is continuously read from at least two memories, it is necessary to provide a preamble period between each data access.
More than one cycle is available.

DIM equipped with a plurality of DDR SDRAMs
In a memory module called M, a plurality of memories sharing the same data line may also share the DQS signal line as described above.

[0006]

Here, as a reference example in which a plurality of memories share a DQS signal line, an information processing system in which a storage control device and three memories are connected by one DQS signal line will be described. As shown in FIG.

In FIG. 13, an information processing system includes a processor 140, a storage controller 141, a data strobe signal controller 142, and memories 143a and 143.
b, 143c, DQS signal line L141, memory select lines L143a, L143b, L143c, memory command line L144, data bus L145, and memory address signal line L146.

In the information processing system shown in FIG. 13, a storage controller 141 and memories 143a, 143
b and 143c are connected by one DQS signal line L141. The operation of reading data from the memory in such an information processing system will be described with reference to FIG. FIG. 12 is a timing chart for data reading.

In FIG. 12, first, a storage controller 141
Receives a memory access request from the processor 140 as a request issuing device. In response, at time T0, the storage controller 141 sends the memory command line L1
A signal for reading data is output to 44 (denoted by CAS in the figure), and a signal indicating that the memory 143a is to be read is output to a memory selection line L143a (denoted by CS0 in the figure). Further, a memory address signal indicating a storage position of data to be read is output to the memory address signal line L146. In FIG.
It is assumed that the data read latency is 2 cycles and the data burst length is 2. Therefore, the memory 143
“a” outputs two pieces of data to the data bus L145 (denoted as DATA in the figure) at time T2.

In this case, prior to outputting data to the data bus L145, the memory 143a sets the signal level of the signal output to the DQS signal line L141 (described as DQS in the figure) to "0" during the time T1. I do. This time T1
The state of the signal output at the signal level “0” during the period
It is called "reamble" and is defined as a standard for input and output of DDR SDRAM. After this preamble, at time T2, the memory 143a stores the DQS signal line L14
1 to output a signal of signal level “1”. As a result, D
The signal transmitted by the QS signal line L141 rises to a signal level “1”, and then falls to a signal level “0”. This signal is a data strobe signal. The storage controller 141 receives this data strobe signal via the DQS signal line L141, and reads the data output from the memory 143a from the data bus L145 at the rising and falling timings of the data strobe signal.

In this information processing system, since the storage control device and each memory are connected by one DQS signal line, when reading data from the memory 143b after reading data from the memory 143a, One cycle space is generated in L145. That is,
Since a one-cycle preamble is required before outputting a data strobe signal for reading data, the memory 143b needs to set the signal level of the output signal to “0” during the time T3 as described above. is there. Therefore, it is time T4 that the memory 143b can output the data strobe signal of the signal level "1".
Therefore, the memory 143b transfers the data to the data bus L14.
5 can be output at time T4, resulting in a one-cycle vacancy on the data bus L145.

As described above, when a plurality of memories share the same data line and also share a DQS signal line,
When reading data continuously from multiple memories,
An empty cycle in which data access cannot always be performed occurs, and as a result, the data transfer capability of the memory is reduced.

To prevent this, even when a plurality of memories share the same data line, a DQS signal line may be provided for each memory so that the memories do not share the DQS signal line. However, in this case, the total number of signal lines of the LSI constituting the storage control device for controlling the memory increases, and the total number of signal lines of the memory module mounting the memory also increases. For this reason, there is a new problem that the cost of the entire apparatus is increased.

A technique of providing a strobe signal line for each memory block composed of DRAM elements is disclosed in Japanese Patent Laid-Open No. 6-175.
No. 909. However, in this technology,
Only a plurality of column address strobe signal lines are provided for each memory block.
It does not disclose using an SDRAM or providing a data strobe signal line for each memory block.

An object of the present invention is to solve the above-mentioned problems and to provide a technique for suppressing the occurrence of empty cycles when accessing data in at least two or more memories while suppressing an increase in the number of total signal lines. Is to do.

[0016]

In the present invention, DD is used.
A data strobe signal control device is provided between a storage control device of an information processing system including at least two or more memories using an RS SDRAM as a memory element and each memory. In the related art, the storage controller and each memory are directly connected by the DQS signal line. In the present invention, however, all the DQS signal lines connected to each memory are connected to the data strobe signal controller. The data strobe signal control device transmits the DQS signal only to the memory selected by the storage control device. Further, the data strobe signal control device transmits only the DQS signal transmitted from the selected memory to the storage control device,
The signal transmitted from the memory selected during the preamble period is not transmitted.

Therefore, when data access to at least two memories is performed consecutively, the data strobe signal control device applies a signal level "0" to each of the DQS signal lines individually connected to each memory.
(Low level) signal can be transmitted to provide a preamble period. That is, even if the signal for one memory is in the preamble state, the signal level “1” (H
(high level) DQS signal. Therefore, no empty cycle occurs in the data line.

Further, since the data strobe signal control device and the storage control device need only be connected by one DQS signal line, it is possible to suppress an increase in the number of signal pins of an LSI constituting the storage control device. .

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an information processing system including a data strobe signal control device according to one embodiment of the present invention. FIG. 2 is a block diagram showing a configuration of the data strobe signal control device. FIG. 3 is a block diagram showing a configuration of the access memory selection device in the data strobe signal control device.

In FIG. 1, an information processing system includes a processor 100, a storage controller 1, a data strobe signal controller 2, memories 3a, 3b, 3c, and a common D.
QS signal line L1, DQS signal lines L2a, L2b, L2
c, memory select lines L3a, L3b, L3c, a memory command line L4, a data bus L5, and a memory address signal line L6. The processor 100 issues an access request (data read or write request) to each of the memories 3a, 3b, and 3c. The storage control device 1 receives a request from the processor 100 and controls reading or writing of data from or to each of the memories 3a, 3b, and 3c. The processor 100 and the storage controller 1 are connected by signal lines or buses for transmitting address signals, data, and control signals. In FIG. 2, the data strobe signal control device includes:
Data strobe signal driver 10a, 10b, 10c
, An access memory selecting device 11, tri-state buffers 12, 13, 14, 15, and signal lines L10a, L10a.
10b, L10c, signal lines L11a, L11b, L11
c, signal lines L12a, L12b, L12c, signal line L1
3 is comprised. Each data strobe signal driving device 10a, 10b, 10c is connected to each memory 3a, 3b, 3c
, And the common DQS signal lines L1 and D1
The QS signal lines L2a, L2b, and L2c each transmit and receive a data strobe signal and the like. The access memory selection device 11 includes memory selection lines L3a, L3b, L3
In order to enable communication such as a data strobe signal between the memory designated by the memory designation signal from 3c and the storage control device, the data strobe signal driving devices 10a, 10b, and 10c corresponding to the designated memory are used. Controls signal transmission and reception operations.

In FIG. 3, an access memory selecting device includes a data strobe signal timing control device 20a,
20b, 20c, decoder 21, NOT circuit 22
, AND circuits 23, 24, and latches 25, 26, 27
, NOR circuits 28 and 29, and signal lines L20 and L21.

In FIG. 1, a storage control device 1 receives a memory access request from a processor 100 which is a request issuing device. Here, only one processor is shown, but a plurality of processors may be used. The storage control device 1 may receive a memory access request from a control device that mediates a memory access request from the processor instead of the processor. Further, the processor may be an input / output control device or a device that controls communication with another system. The processor may be any device that issues any other type of memory access request. Although only one storage control device 1 is provided in FIG. 1, a configuration in which a plurality of storage control devices are used in the entire information processing system may be employed. Further, in FIG. 1, the storage control device 1 has only one data bus L5, but may have a configuration in which a plurality of data buses L5 are held.

According to the type of the memory access request received from the processor 100, the storage control device 1
A memory access request is issued to the memories 3a, 3b, 3c. Here, in FIG. 1, the information processing system includes three memories, but may include any number of memories.
The data width of the data accessed by the storage controller 1 may be any number of bits. In order to make the data width serving as an access unit larger than the physical data width of the memory, the storage control device 1 may access a plurality of memories simultaneously.

The storage control device 1 has memories 3a, 3b, 3c
When a memory access request is issued to the device, the memory to be accessed is specified using the memory selection lines L3a, L3b, and L3c. In one access, the storage control device 1 selects only one of the memory selection lines L3a, L3b, and L3c to designate one memory.
Specifically, the storage control device 1 controls the memory selection lines L3a, L3
3b and L3c are selected, and a memory designation signal indicating that the memory is to be accessed is transmitted to the memory selection line. The storage control device 1 transmits a memory command signal indicating whether the memory access is data reading or writing to the memory command line L4 in response to the transmission of the memory designating signal. A signal indicating the memory address of the access destination is transmitted to L6. When the memory access is a data write to the memory, the storage controller 1 outputs data to be written to the data bus L5. When the memory access is a data read from the memory, the memory 3a,
3b and 3c output the data stored at the designated address to the data bus L5. In this case, the storage control device 1 receives data from the data bus L5.

At the time of the data transfer, a data strobe signal indicating the data output timing is output from the data strobe signal control device 2 or the memories 3a, 3b, 3c to the DQS signal lines L2a, L2b, L2c.
When data is read from any of the memories 3a, 3b, and 3c, the designated memory among the memories 3a, 3b, and 3c is connected to the memory when outputting the data to the data bus L5. The data strobe signal is output to the DQS signal line. Also, the memories 3a, 3b, 3c
When data is written to any of the above, the data strobe signal control device 2 outputs a data strobe signal to the DQS signal line connected to the specified memory. In this case, the designated memory receives a data strobe signal from the DQS signal line connected to the memory, and receives data from the data bus L5 using the data strobe signal as a timing signal.

In the following, a description will be given of the fact that the information processing system according to the present embodiment can read and write data without generating an empty space for one cycle.

First, data is read from the memory 3a,
Subsequently, an operation when data is read from the memory 3b will be described with reference to FIGS. 1, 2, 3, and 5. FIG.

FIG. 5 is a timing chart for data reading in this embodiment. First, the storage control device 1
Receives an access request to the memory 3a and the memory 3b from the processor 100. In response to this, in FIG. 5, at time T0, the storage controller 1 outputs a memory command signal instructing data reading to a memory command line L4 (denoted by CAS in the figure), and a memory selection line L3
The memory designation signal (signal level “0” in FIG. 5) indicating that the memory 3a is a target to be read is output to a (described as CS0 in the figure). Further, a memory address signal indicating a storage position of data to be read is output to the memory address signal line L6. The memory address signal line L6 connects the storage control device 1 and each of the memories 3a, 3b, 3c. In FIG. 5, it is assumed that the data read latency is 2 cycles and the data burst length is 2. Therefore, the memory 3a outputs two pieces of data read from the address specified at the time T2 to the data bus L5 (described as DATA in the figure).

Prior to outputting data to the data bus L5, the memory 3a outputs the DQS signal line L2 during the period of time T1.
a (described as DQS (L2a) in the figure), the signal level is set to “0” (Low level). This p
After the reamble, at time T2, the memory 3a
A signal of signal level "1" (High level) is output to signal line L2a.

In FIG. 2, the DQS signal line L2a is connected to a data strobe signal driving device 10a included in the data strobe signal control device 2. DQS signal line L2
The data strobe signal transmitted by a is input to the tri-state buffer 12 in the data strobe signal driving device 10a. The tri-state buffer 12 is connected to the access memory selection device 11 by a signal line L10a. The tri-state buffer 12 is controlled by a signal output from the access memory selection device 11 to the signal line L10a. When the signal input from the signal line L10a is at the signal level "1", the tri-state buffer 12 outputs the input signal as it is. When the signal level is "0", the output is in a high impedance state.

The signal output from the storage control device 1 to the memory command line L4 and the memory selection line L3a at time T0 is input to the access memory selection device 11 included in the data strobe signal control device 2. In FIG. 3, the memory command line L4 is connected to the decoder 21. When the storage controller 1 outputs a memory command signal instructing data reading to the memory command line L4, the decoder 21 receives the signal, sets the signal level of the signal output to the signal line L20 to “1”, and sets the signal level to “1”. The signal level of the signal output to L21 is set to “0”. When the storage control device 1 outputs a memory command signal instructing data writing to the memory command line L4, the decoder 21 receives the signal and sets the signal level of the signal output to the signal line L20 to “0”. The signal level of the signal output to the signal line L21 is set to “1”. The signal lines L20 and L21 are connected to AND circuits 23 and 24 included in the data strobe signal timing control device 20a, respectively. A signal obtained by taking the NOT of the memory selection line L3a by the NOT circuit 22 is input to the AND circuits 23 and 24. As a result, the AND circuit 23 operates in the storage controller 1
Outputs a signal of signal level "1" when instructing to read the memory 3a, and outputs a signal of signal level "0" otherwise. The AND circuit 24 outputs a signal of signal level "1" when the storage control device 1 instructs writing to the memory 3a, and outputs a signal of signal level "0" otherwise. The output signal of the AND circuit 23 is input to the latch 25. Therefore, the output signal of latch 25 indicates the same signal level as the output signal of AND circuit 23 one cycle before. And the latch 25
Is input to the latch 27. Therefore, the output signal of latch 27 output to signal line L10a indicates the same signal level as the output signal of AND circuit 23 two cycles before. The output signal of the AND circuit 24 is input to the latch 26. Therefore, the output signal of the latch 26 output to the signal line L11a indicates the same signal level as the output signal of the AND circuit 24 one cycle before.

Thus, when the storage controller 1 instructs reading of the memory 3a at time T0, two cycles after that, that is, at time T2 in FIG.
The signal level of the signal output to “a” is “1”, and at other times, the signal level is “0”. As described above, the tri-state buffer 12 is controlled by the signal input from the signal line L10a. Therefore, at time T2 when the signal level of the signal transmitted through the signal line L10a is “1”, the tristate buffer 12 outputs the data strobe signal input from the DQS signal line L2a as it is. At other times, the signal level of the signal input from the signal line L10a is “0”, so that the output of the tristate buffer 12 is in a high impedance state. That is, the tri-state buffer 12 outputs only the data strobe signal output from the memory 3a at time T2 to the common DQS signal line L1, and does not output the signal in the preamble state at time T1.

The AND circuit 24 always outputs a signal of signal level "0" in the read operation of the memory 3a. Therefore, the signal level of the signal output from the latch 26 to the signal line L11a is always “0”. Signal line L11
a is connected to the tri-state buffer 13. The tristate buffer 13 is controlled by a signal input from the signal line L11a. When the signal input from the signal line L11a is at the signal level “1”, the tristate buffer 13 outputs the input signal as it is, and outputs the signal level “0”. In this case, the output goes into a high impedance state. Therefore, the output of the tri-state buffer 13 is always in a high impedance state in the read operation of the memory 3a and does not participate in the operation.

The NOR circuit 28 which takes the negation of the logical sum of the output signals of the latches 25, 26 and 27 outputs the signal of the signal level "0" to the signal line L12a at times T1 and T2, and outputs the signal at other times. The signal of level "1" is transmitted to the signal line L1.
2a. The signal line L12a is connected to the tri-state buffer 14. Tri-state buffer 1
4 is controlled by a signal input from the signal line L12a. When the signal input from the signal line L12a is at the signal level "1", the input signal is output as it is, and when the signal is "0", The output goes into a high impedance state. Therefore, the memory 3a is connected to the DQS signal line L2
The output of the tri-state buffer 14 is in a high impedance state at a time T1 when a signal in the preamble state is output to a and at a time T2 when a data strobe signal of the signal level “1” is output. Since the input of the tri-state buffer 14 is connected to GND having the signal level "0", the signal of the signal level "0" is output at other times.

In the same manner as described above, when the storage controller 1 instructs reading of the memory 3b at time T1, two cycles after that, that is, at time T3 in FIG. 5, the signal of the signal output to the signal line L10b is output. The level becomes “1”, and at other times, the signal level becomes “0”. In the read operation of the memory 3b, the signal line L1
The signal level of the signal output to 1b is always "0". The signal output to the signal line L12b is at time T
At 2, T3, the signal level becomes "0", and at other times, it becomes "1".

In FIG. 3, signal lines L10a, L11a, L10b, L11b, L10 connected to data strobe signal timing controllers 20a, 20b, 20c
c and L11c are connected to the NOR circuit 29. The NOR circuit 29 is connected to the tri-state buffer 15 by a signal line L13. Tri-state buffer 15
Is controlled by a signal input from the signal line L13. When the signal input from the signal line L13 is at the signal level “1”, the input signal is output as it is, and when the signal is “0”, The output goes into a high impedance state. The input of the tri-state buffer 15 is connected to GND at the signal level “0”. The output of the tri-state buffer 15 is supplied from one of the data strobe signal drivers 10a, 10b, and 10c to the DQS signal line L2.
a, L2b, and L2c, when a signal is output to the common DQS signal line L1, or when the storage controller 1 writes data to any of the memories 3a, 3b, and 3c, the high impedance state is set. Become. In other cases, that is, which data strobe signal driving device 1
0a, 10b and 10c are also signal lines L2a, L2b and L2c.
Is not output to the common DQS signal line L1, and the storage control device 1
When data is not written to any of 3b and 3c, tristate buffer 15 outputs a signal of signal level “0” to common DQS signal line L1. As a result, as shown in FIG. 5, at time T2, the data strobe signal output from the memory 3a to the DQS signal line L2a is output from the data strobe signal driving device 10a.
Is output to the common DQS signal line L1. Time T
3, the data strobe signal output from the memory 3b to the DQS signal line L2b is output from the data strobe signal driver 10b to the common DQS signal line L1. At other times, a signal of signal level “0” is output from tristate buffer 15 to common DQS signal line L1.

As will be easily understood from the above description,
When the storage control device 1 instructs reading of any of the memories 3a, 3b, 3c, the data strobe signal control device 2 outputs the data strobe of the signal level "1" output from any of the memories 3a, 3b, 3c. Signal D
The signal is output to the QS signal line L1, and at other times, the signal of the signal level “0” is output to the common DQS signal line L1. Thus, even when one of the memories 3a, 3b, and 3c outputs a signal in the preamble state, the other memories can issue the data strobe signal of the signal level "1". Therefore, as shown in FIG.
Immediately after the memory 3a outputs data to the data bus L5, the memory 3b can output data to the data bus L5.

Next, the operation when writing data to the memory 3a and subsequently writing data to the memory 3b will be described with reference to FIG.
This will be described with reference to FIGS.

FIG. 6 is a timing chart for data writing in this embodiment. The storage controller 1 receives an access request to the memories 3a and 3b from the processor 100. Accordingly, in FIG.
At time T0, the storage controller 1 sends the memory command line L4
A memory command signal instructing data writing is output to the memory selection line L3a (indicated as CS0 in the figure), and a memory designation signal (indicated as CS0 in the figure) indicating that the memory 3a is to be written. 6, the signal level "0") is output. Further, a memory address signal indicating a position where data is to be written is output to memory address signal line L6. In FIG. 6, it is assumed that the data write latency is one cycle and the data burst length is two. Therefore, the storage control device 1 transfers the data to be written at the time T1 to the data bus L5 (described as DATA in the figure).
Output two.

Data is sent from the storage controller 1 to the data bus L
Prior to being output to S5, the signal level of the signal output to the DQS signal line L2a (described as DQS (L2a) in the drawing) during the time T0 needs to be set to "0" (Low level). is there. Further, after the preamble, at time T1, the signal level “1” (H
(high level) signal needs to be output. In the present embodiment, the storage control device 1 outputs a data strobe signal of a signal level “1” (High level) to a common DQS signal line L1 (described as DQS (L1) in the figure) at time T1. However, the storage control device 1 operates at time T0.
The signal level of the signal output to the common DQS signal line L1 during the period is not set to “0” (Low level). In the present embodiment, as described below, the data strobe signal control device 2 sets the signal level of the signal output to the DQS signal line L2a to “0” (Low level) during the time T0.

As described above, when there is no request for the memory, the AND circuits 23 and 24 in the data strobe signal timing control device 20a output a value "0". It becomes "0", and the value "1" is output to the output of the NOR circuit 28, that is, the signal line L12a. Therefore, when there is no request for the memory, the tri-state buffer 14 sets the value “0” to the DQS signal line L2a.
Output to Similarly, the tri-state buffer 15 outputs the value “0” to the common DQS signal line L1.

In this state, when the storage controller 1 issues a signal instructing writing to the memory 3a to the memory command line L4 and the memory selection line L3a at time T0, the data strobe signal timing controller 20a Of the AND circuit 24 changes to the value “1”. Therefore, at time T1 after one cycle, the output of the latch 26 has the value “1”, and therefore, the signal line L11a has the value “1”.
And the signal line L12a changes to the value “0”. At this time, since the output of the AND circuit 23 remains at the value “0”, the signal line L10a holds the value “0”. Then, as a result of the signal line L11a having the value “1”, the signal line L
13 has the value "0".

As a result, the tri-state buffer 14 outputs the value "0" to the DQS signal line L2a at time T0, but at time T1, the tri-state buffer 14 enters the high impedance state. Although the tri-state buffer 15 outputs the value “0” to the common DQS signal line L1 at T0, the tri-state buffer 15 enters a high impedance state at time T1. Further, the tri-state buffer 12 maintains the high impedance state during the period of FIG. Then, at time T1, the storage control device 1 outputs a signal for data strobe to the common DQS signal line L1, and this signal is transmitted to the DQS signal line L2a by the tristate buffer 13.

As described above, before the data strobe signal for writing data is transmitted to the DQS signal line L2a, the value "0" is maintained on the DQS signal line L2a.
This is equivalent to preamble for the memory 3a.

By the same operation as described above, at time T2, at time T1, the storage controller 1 sets the memory command line L
4. As a result of issuing a signal instructing writing to the memory 3b to the memory selection line L3b, the data strobe signal driver transmits the signal of the common DQS signal line L1 to the DQS signal line L2b. Thereby, for the memory 3b,
A preamble and a data strobe signal for writing data are supplied in the same manner as in the case of the memory 3a.

As will be easily understood from the above description,
When the storage controller 1 instructs writing to any of the memories 3a, 3b, and 3c, the data strobe signal controller 2 outputs the data to the memories 3a, 3b, and 3c issued by the storage controller 1 to the common DQS signal line L1. Only the signal for the strobe is supplied to the DQS signal lines L2a, L2b, L2c. Before the data strobe signal is supplied,
Since the value “0” is held in any of the DQS signal lines L2a, L2b, and L2c, it is preamble.
Are also correctly supplied to the memories 3a, 3b and 3c.
As a result, even while the data strobe signal preamble is being supplied to a certain memory, the data strobe signal can be issued to the other memory. Therefore, as shown in FIG. 3b can be written.

In the above description, the burst length of the memory is 2. However, the present embodiment is applicable even if the burst length is 4. When the burst length is 4, the data strobe signal timing control device 20a,
By using the data strobe signal timing control device 30a shown in FIG. 4 instead of 20b and 20c, the memory can be read without an empty cycle as in the case where the burst length is 2. Hereinafter, the case where the burst length is 4 will be described with reference to FIGS. FIG. 4 is a diagram showing the configuration of the data strobe signal timing control device 30a, and FIG. 7 is a timing chart for data reading when the burst length is 4. In FIG. 4, 3
1 and 32 are latches, and 33 and 34 are OR circuits.
The components having the same reference numerals as those in FIG. 3 have the same functions as those in FIG.

When the burst length is 4, when the storage controller 1 instructs the memory 3a to read, the memory 3a outputs data for two cycles, and therefore also outputs a data strobe signal for two cycles. In other words, compared to the case of FIG.
The data strobe signal is sent from the DQS signal line L2a to the common D
It is necessary to transmit the signal to the QS signal line L1.

In FIG. 4, the AND circuits 23 and 24 are used when the storage controller 1 instructs the memory command line L4 and the memory selection line L3a to read and write to the memory 3a in the same manner as described with reference to FIG. Take the value "1". Therefore, the latch 27 takes the value "1" two cycles after the storage controller 1 instructs the memory 3a to read, as in the case of FIG. 3, and the latch 31 instructs the storage controller 1 to read the memory 3a. The value "1" is taken after three cycles. The OR circuit 33 outputs the logical sum of the outputs of the latches 27 and 31 to the signal line L10a, which means that the value "1" is held by one extra cycle compared to the case of FIG. Thus, data strobe signal timing control device 30a transmits the data strobe signal from DQS signal line L2a to common DQS signal line L1.

FIG. 7 shows an example of the above operation. When the storage control device 1 instructs the memory 3a to read at time T0,
Memory 3a outputs data for two cycles from time T2 to T3, and therefore, the data strobe signal is also output for two cycles from time T2 to T3.
As described above, the data strobe signal timing control device 30a outputs the data strobe signal to the DQS signal line L2a.
5 transmits to the common DQS signal line L1 one cycle longer than in the case of FIG. 5, and otherwise operates exactly the same as in FIG. Therefore, at time T2, the storage control device 1 can instruct the memory 3b to read data, and data can be transmitted without an idle cycle.

In the case of writing to the memory, similarly to the case of reading, it is necessary to transmit the data strobe signal from the common DQS signal line L1 to the DQS signal line L2a, which is longer by one cycle than in the case of FIG. As in the case of the read operation, the information of the write instruction is held by one extra cycle using the latch 32 and is input to the OR circuit 34, so that the signal line L11a has one signal as compared with the case of FIG.
The value "1" can be held extra for the number of cycles, and a write operation with no empty cycle at a burst length of 4 can be performed.

In some DDR SDRAMs, the latency from the issuance of a memory read command to the issuance of data is 2.5 cycles instead of 2 cycles. In such a case, the latch 25, 27, 31 Can be dealt with by changing the clock supplied to the memory to a clock shifted by a half phase from the clock supplied to the memory.

Next, another embodiment of the present invention will be described. This embodiment is a modification of the above-described embodiment. According to the present embodiment, similar data transmission control can be realized even when the conditions of the electrical characteristics of the device are stricter than in the above-described embodiments.

FIG. 8 is a block diagram showing the configuration of an information processing system including the data strobe signal control device according to this embodiment. FIG. 9 is a block diagram showing a configuration of the data strobe signal control device. FIG. 10 is a block diagram showing a configuration of the access memory selection device in the data strobe signal control device.

In FIG. 8, components having the same functions as the components shown in FIG. 1 are denoted by the same reference numerals. 9, components having the same functions as the components shown in FIG. 2 are denoted by the same reference numerals. Also in FIG. 10, components having the same functions as the components shown in FIG. 3 are denoted by the same reference numerals. In the following description, components that are different from the above-described embodiment will be mainly described.

The information processing system shown in FIG. 8 includes a data strobe signal control device 40 instead of the data strobe signal control device 2, and a common read DQS signal line instead of the common DQS signal line L1. It is different from the information processing system shown in FIG. 1 in that it has L1r and a DQS signal line L1w for common writing.

The data strobe signal control device 40 shown in FIG. 9 differs from the data strobe signal control device 2 shown in FIG. 2 in that an access memory selection device 51 is provided instead of the access memory selection device 11. ing.

The access memory selection device 51 shown in FIG. 10 includes a NOR circuit 52 instead of the NOR circuit 29 in that the access memory selection device 51 shown in FIG.
Different from 1.

In the information processing system shown in FIG. 8, there is one common DQ in the information processing system of FIG.
The S signal line L1 is separated into a common read DQS signal line L1r for transmitting a data strobe signal at the time of data reading and a common write DQS signal line L1w for transmitting a data strobe signal at the time of data writing. Since the data strobe signal is a signal for high-speed transmission of data, it may be difficult to transmit a bidirectional signal as shown in FIG. In this embodiment, the signal line for transmitting the data strobe signal is connected to the one-way signal line 2 for such a case.
Separated into books.

In the case of data reading, the DQS signal line L
Since the signal flowing through any one of 2a, L2b, and L2c may be transmitted to the common read DQS signal line L1r, the output of the tristate buffer 12 is connected to the common read DQS signal line L1r. In the case of data writing, the signal of the common writing DQS signal line L1w is changed to the DQS signal line L2.
a, L2b, or L2c.
The common write DQS signal line L1w is input to the tristate buffer 13. Thus, unlike FIG. 2, the output of the tri-state buffer 12 and the input of the tri-state buffer 13 are not connected in FIG.

In FIG. 10, unlike FIG.
Connected to the OR circuit 52 are the signal lines L10a, L11
a and L12a only. In FIG. 3, the signal lines L10b, L11b, and L12b are set to NOR in order to set the tristate buffer 15 to a high impedance state when transmitting a strobe signal for writing data.
It had to be connected to the circuit 29. However, in this embodiment, since the common read DQS signal line L1r and the common write DQS signal line L1w are separated, it is not necessary to put the tristate buffer 15 into a high impedance state when writing data. Therefore, the signal lines L10b, L11b, and L12b are not connected to the NOR circuit 52. Even if the tri-state buffer 15 is set to the high impedance state at the time of data writing, there is no logical problem. However, in this case, since the potential of the common readout DQS signal line L1r is in an unstable state, it is desirable to configure as described above.

By adopting the above configuration, also in this embodiment, it is possible to transmit data without an idle cycle, as in the above-described embodiment.

Further, another embodiment of the present invention will be described. In this embodiment, the storage is constituted by an aggregate of memories called a memory module.

FIG. 11 is a block diagram showing the configuration of an information processing system including the data strobe signal control device according to this embodiment. 11, components having the same functions as those shown in FIG. 1 are denoted by the same reference numerals. In the following description, components that are different from the above-described embodiment will be mainly described.

In FIG. 11, the information processing system includes a processor 100, a storage controller 1, memory modules 4a, 4b, 4c, and common DQS signal lines L1a, L1.
b, L1c and memory select lines L8a, L8b, L8c,
L8d, L8e, L8f, a memory command line L4,
It comprises a data bus L5 and a memory address signal line L6. In the memory module 4a, a data strobe signal control device 7, memories 8a and 8b,
DQS signal lines L7a and L7b are provided. still,
FIG. 11 shows only the data strobe signal control device, the memory, and the DQS signal line provided in the memory module 4a, but the other memory modules 4b, 4c also include the memory module 4a. Similarly, data strobe signal control device, memory, DQ
Each of the S signal lines is provided.

In this embodiment, the memory module 4
A data strobe signal control device is provided for each of a, b, and c. Each memory module 4a, 4b, 4
The data strobe signal control device provided in c has the same configuration as the data strobe signal control device 2 shown in FIG. 1 and operates similarly.

In this embodiment, the common DQS signal line L1
a, L1b, L1c are the memory modules 4a, 4b, 4
It is provided for each c. Therefore, when transmitting and receiving the data strobe signal, the storage control device 1 selects one of the common DQS signal lines L1a, L1b, and L1c corresponding to one of the memory modules 4a, 4b, and 4c to be accessed.

For example, the operation when the storage controller 1 reads data from the memory 8a in the memory module 4a and subsequently reads data from the memory 8b will be described.

At time T0, the storage controller 1 outputs a memory command signal instructing data read to the memory command line L4, and outputs a memory designation signal indicating that the memory 8a is to be read to the memory select line L8a. You. Further, a memory address signal indicating a storage position of data to be read is output to the memory address signal line L6. Further, at time T1, a memory command signal for instructing data reading is output from the storage control device 1 to the memory command line L4, and a memory designation signal indicating that the memory 8b is to be read is output to the memory selection line L8b. . Further, a memory address signal indicating a storage position of data to be read is output to the memory address signal line L6. The signal output at time T0 is received by memory 8a and data strobe signal control device 7. In response to these signals, a signal of signal level “0” is output from memory 8a to DQS signal line L7a at time T1. After the preamble state, at time T2, the memory 8a
Outputs a signal of signal level "1" to DQS signal line L7a, and outputs data to data bus L5.
On the other hand, the signal output at time T1 is received by memory 8b and data strobe signal control device 7. In response to these signals, a signal of signal level "0" is output from memory 8b to DQS signal line L7b at time T2. After the preamble state, at time T3, the memory 8
b, a signal of signal level “1” is output to the DQS signal line L7b, and data is output to the data bus L5. The data strobe signal control device 7 is shown in FIGS.
By performing the same operation as data strobe signal control device 2 described with reference to FIG. 3, at time T2, DQS signal line L7
a, and outputs the signal of the signal level “1” to the common DQS signal line L1a.
7b receives the signal of signal level "1" from the common DQS
Output to the signal line L1a. At other times, the data strobe signal control device 7 outputs a signal of signal level “0” to the common DQS signal line L1a. Storage control device 1
Selects the common DQS signal line L1a connected to the accessed memory module 4a, receives a signal of signal level "1" at time T2 from the common DQS signal line L1a, and reads the data read from the memory 8a. From the data bus L5. At time T3, a signal of signal level "1" is received from the common DQS signal line L1a, and data read from the memory 8b is transmitted to the data bus L.
5 to receive.

As described above, the data reading operation of the information processing system according to the present embodiment is performed by connecting one of the common DQS signal lines provided for each memory module to the storage controller 1.
Is substantially the same as the data read operation by the information processing system of the above-described embodiment except that is selected. Similarly, the data write operation by the information processing system of the present embodiment is also performed except that the storage control device 1 selects one of the common DQS signal lines provided for each memory module and outputs a data strobe signal. Thus, the operation is almost the same as the data write operation by the information processing system of the above-described embodiment.

Therefore, similarly to the above-described embodiment, in the information processing system according to the present embodiment, data can be transmitted between the storage control device and the memory without an empty cycle.

In this embodiment, as in the other embodiments described above, the common DQS signal lines L1a, L1b, L1
c and the common read DQS signal line and the common write DQS
It may be separated into QS signal lines.

The present invention is not limited to the above-described embodiments, and various possible changes and additions to the configuration of each embodiment are included in the scope of the present invention.
For example, in each of the embodiments described above, the data strobe signal control device is configured independently of the storage control device,
Alternatively, it is provided in the memory module. But,
The data strobe signal control device may be configured integrally with the storage control device. In that case, the data strobe signal control device may be incorporated as one function in one LSI configuring the storage control device.
Alternatively, when the storage control device is configured as a chipset including a plurality of LSIs, the data strobe signal control device may configure a part of the chipset. Further, each of the memory selection line, the memory command line, and the memory address signal line is described as one or more signal lines, but these signal lines may be configured as a control bus or an address bus. . In addition, the processor and the storage controller are directly connected by signal lines for transmitting address signals, data, and control signals, but this signal line may include a plurality of signal lines for transmitting each signal. good. Alternatively, this signal line may be a bus that includes a wiring for transmitting each of the above-mentioned signals, and directly or indirectly connects the processor and the storage controller.

[0075]

As described above, according to the present invention,
In the case of accessing a memory sharing a data bus, it is possible to perform data access to each memory without causing an empty cycle when reading is continuously performed to one or more memories. Memory access performance can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an information processing system according to an embodiment.

FIG. 2 is a block diagram showing a configuration of a data strobe signal control device according to one embodiment.

FIG. 3 is a block diagram illustrating a configuration of an access memory selection device according to an embodiment;

FIG. 4 is a block diagram showing a configuration of a data strobe signal timing control device according to one embodiment;

FIG. 5 is a diagram showing a timing chart of data reading by the information processing system in one embodiment;

FIG. 6 is a diagram showing a timing chart of data writing by the information processing system in one embodiment;

FIG. 7 is a diagram showing a timing chart of data reading in the case of a burst length of 4 by the information processing system in one embodiment.

FIG. 8 is a block diagram illustrating a configuration of an information processing system according to another embodiment.

FIG. 9 is a block diagram showing a configuration of a data strobe signal control device according to another embodiment.

FIG. 10 is a block diagram illustrating a configuration of an access memory selection device according to another embodiment.

FIG. 11 is a block diagram illustrating a configuration of an information processing system according to another embodiment.

FIG. 12 is a timing chart of data reading in the information processing system of the reference example;

FIG. 13 is a block diagram illustrating a configuration of an information processing system according to a reference example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Storage controller 2 Data strobe signal controller 3a, 3b, 3c, 8a, 8b Memory 4a, 4b, 4c Memory module L1, L1a, L1b, L1c Common DQS signal line L2a, L2b, L2c, L7a, L7b DQS signal line L3a, L3b, L3c Memory selection line L8a, L8b, L8c, L8d, L8e, L8f Memory selection line L4 Memory command line L5 Data bus L6 Memory address signal line 10a, 10b, 10c Data strobe signal drive device 11 Access memory selection device 20a , 20b, 20c Data strobe signal timing control device 30a Data strobe signal timing control device 40 Data strobe signal control device 51 Access memory selection device 7 Data strobe signal control device 100 Processor

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yasuaki Yamashita 1 Horiyamashita, Hadano-shi, Kanagawa F-term in the Enterprise Server Division, Hitachi, Ltd. 5B060 CC03 CC05 MM15

Claims (18)

[Claims] A request issuing device for requesting data reading or writing to each of the at least two memories; receiving a request from the request issuing device to read or read data from the at least two or more memories; An information processing system comprising: a storage controller that executes writing; wherein the storage controller is connected to a first data strobe signal line and separated by a second data strobe signal line different from each of the at least two or more memories. Connected to the second data strobe signal line connected to one of the at least two or more memories, receiving the data strobe signal transmitted from the storage control device from the first data strobe signal line. Transmit and also what the at least two or more memories An information processing system comprising: a data strobe signal control device that receives a data strobe signal transmitted from the data strobe signal line from the second data strobe signal line and transmits the data strobe signal to the first data strobe signal line. 2. The information processing system according to claim 1, wherein each of said at least two or more memories before transmitting said data strobe signal to any of said at least two or more second data strobe signal lines. In one cycle period, a low-level signal is transmitted to any of the at least two or more second data strobe signal lines, and the data strobe signal control device is transmitted from any of the at least two or more memories. Receiving the low-level signal and the data strobe signal from any of the at least two or more second data strobe signal lines;
An information processing system, wherein only the data strobe signal is transmitted to the first data strobe signal line. 3. The information processing system according to claim 2, wherein said data strobe signal control device receives said data strobe signal from said first data strobe signal line and sends said data strobe signal to said first data strobe signal line. Transmitting a data strobe signal, receiving the data strobe signal or the low-level signal from any of the second data strobe signal lines, and transmitting the data strobe signal to any of the second data strobe signal lines. A signal drive unit for transmitting, the signal drive unit, when receiving the data strobe signal from the first data strobe signal line and when transmitting the data strobe signal to the first data strobe signal line Except for transmitting a low level signal to the first data strobe signal line And the data strobe signal or the Lo signal from any one of the second data strobe signal lines.
transmitting a low-level signal to the second data strobe signal line, except when receiving a w-level signal and transmitting the data strobe signal to any of the second data strobe signal lines; An information processing system characterized by the following. 4. The information processing system according to claim 3, wherein the data strobe signal control device is configured to control the data strobe from the signal driver to the first data strobe signal line or the second data strobe signal line. An information processing system further comprising a signal control unit that controls transmission of a signal or the Low-level signal. 5. The information processing system according to claim 4, wherein the signal control unit is connected to each of the storage control device and the at least two or more memories by a memory selection signal line and a memory command signal line, and A memory designation signal and a memory command signal transmitted from a control device are received from the memory selection signal line and the memory command signal line, and the memory designation among the at least two or more memories according to the content of the memory command signal. Receiving the low-level signal or the data strobe signal from the second data strobe signal line connected to the memory specified by the signal, or the second data strobe signal connected to the specified memory Transmission of the data strobe signal to the line, and Therefore, the Low to the second data strobe signal line connected to the unspecified memory
An information processing system, wherein the signal driver is configured to transmit a level signal. 6. The information processing system according to claim 3, wherein the signal driver is provided corresponding to each of the at least two memories, and each of the signal drivers is different from the second data strobe signal. A line connected to a corresponding memory of the at least two or more memories, all the signal drivers are connected to the storage controller by the first data strobe signal, and the data strobe signal controller is Signal control for controlling transmission of the data strobe signal or the Low level signal from each of the signal driving units to the first data strobe signal line or the second data strobe signal line for each of the signal driving units. An information processing system further comprising a unit. 7. The information processing system according to claim 6, wherein the signal control unit is connected to each of the storage control device and the at least two or more memories by a memory selection signal line and a memory command signal line, and A memory designation signal and a memory command signal transmitted from a controller are received from the plurality of memory selection signal lines and the memory command signal line, and the memory command signal and the memory command signal are transmitted from the at least two or more memories according to the content of the memory command signal. Receiving the Low-level signal or the data strobe signal from the second data strobe signal line connected to the memory specified by the memory specifying signal, or the second data connected to the specified memory The transmission of the data strobe signal to the strobe signal line is performed by the designated method. The signal drive unit corresponding to the memory, and transmitting the low-level signal to the second data strobe signal line connected to the memory not specified by the memory specification signal. An information processing system characterized by causing the signal drive unit corresponding to (1) to perform the operation. 8. The information processing system according to claim 1, wherein the first data strobe signal line transmits the data strobe signal transmitted from the storage control device to the data strobe signal control device. An information processing system comprising: a data strobe signal line; and a fourth data strobe signal line for transmitting the data strobe signal transmitted from the data strobe signal control device to the storage control device. 9. The information processing system according to claim 8, wherein the data strobe signal control device transmits a low level signal to the fourth data strobe signal line except when transmitting the data strobe signal. Except when receiving a signal including the data strobe signal from any of the second data strobe signal lines and transmitting the data strobe signal to any of the second data strobe signal lines, An information processing system, comprising: a signal driver for transmitting a low-level signal to a second data strobe signal line. 10. A request issuing device for requesting data reading or writing to at least two or more memories, a request issuing device for requesting data reading or writing to each memory, and reading or writing data to or from the at least two or more memories upon receiving a request from the request issuing device. A storage control device for controlling writing, connected to the storage control device of the information processing system by a first data strobe signal line, and separately connected by a second data strobe signal line different from each of the at least two or more memories. A connected data strobe signal control device, wherein the data strobe signal transmitted from the storage control device is received from the first data strobe signal line and connected to any of the at least two or more memories. Transmit to the second data strobe signal line, and A signal driver for receiving a data strobe signal transmitted from any of at least two or more memories from the second data strobe signal line and transmitting the data strobe signal to the first data strobe signal line. Data strobe signal control device. 11. The data strobe signal control device according to claim 10, wherein said signal drive section receives said data strobe signal from said first data strobe signal line and said first data strobe signal. Means for transmitting a low-level signal to the first data strobe signal line, except for transmitting the data strobe signal to a line, and transmitting the data strobe signal from any of the second data strobe signal lines. Means for transmitting a low-level signal to the second data strobe signal line, except when receiving and transmitting the data strobe signal to any of the second data strobe signal lines. Characteristic data strobe signal control device. 12. The data strobe signal control device according to claim 11, wherein the data strobe signal or the low signal from the signal driver to the first data strobe signal line or the second data strobe signal line. A data strobe signal control device further comprising a signal control unit for controlling transmission of a level signal. 13. The data strobe signal control device according to claim 12, wherein the signal control unit is connected to each of the storage control device and the at least two or more memories by a memory selection signal line and a memory command signal line. Receiving the memory designation signal and the memory command signal transmitted from the storage control device from the memory selection signal line and the memory command signal line, and among the at least two or more memories according to the content of the memory command signal. Receiving the data strobe signal from the second data strobe signal line connected to the memory designated by the memory designation signal or to the second data strobe signal line connected to the commanded memory Transmission of the data strobe signal, designated by the memory designation signal A data strobe signal control device, wherein the signal driver controls the signal driver to transmit the low-level signal to the second data strobe signal line connected to the memory that did not exist. 14. The data strobe signal control device according to claim 11, wherein said signal driver is provided corresponding to each of said at least two or more memories, and each said signal driver is different from said second data. A strobe signal line is connected to a corresponding memory among the at least two or more memories, all the signal drivers are connected to the storage controller by the first data strobe signal, and the data strobe signal controller is Signal control for controlling transmission of the data strobe signal or the Low level signal from each of the signal driving units to the first data strobe signal line or the second data strobe signal line for each of the signal driving units. A data strobe signal control device, further comprising a unit. 15. The data strobe signal control device according to claim 14, wherein the signal control unit is connected to each of the storage control device and the at least two or more memories by a memory selection signal line and a memory command signal line. A memory designation signal and a memory command signal transmitted from the storage control device are received from the plurality of memory selection signal lines and the memory command signal line, and among the at least two or more memories according to the content of the memory command signal. Receiving the low-level signal or the data strobe signal from the second data strobe signal line connected to the memory specified by the memory specifying signal, or the second data strobe signal connected to the specified memory. Transmission of the data strobe signal to the data strobe signal line of The signal drive unit corresponding to the specified memory is performed, and the transmission of the Low level signal to the second data strobe signal line connected to the memory not specified by the memory specification signal is performed by the specification. A data strobe signal control device, wherein the control is performed by the signal driver corresponding to a memory that has not been processed. 16. A chip set including a storage control device that controls a data read or a write to at least two or more memories in response to a request from a request issuing device that requests a data read or a write to a memory. A data strobe signal connected to the storage controller by a first data strobe signal line, separately connected to each of the at least two or more memories by a second data strobe signal line, and transmitted from the storage controller. Is transmitted from the first data strobe signal line to the second data strobe signal line connected to any of the at least two or more memories, and is transmitted from any of the at least two or more memories. Transmitting the transmitted data strobe signal to the second data strobe signal Chipset and having a data strobe signal control device for transmitting and receiving the first data strobe signal line from. 17. At least two or more memory modules each including at least two or more memories, a request issuing device for requesting to read or write data to each of the memories included in each of the memory modules, and The information processing system includes a storage control device that reads or writes data to each of the memories included in each of the memory modules in response to the request. And each of the memories included in each of the memory modules is separately connected to each of the memories by a second data strobe signal line, and receives a data strobe signal transmitted from the storage control device from the first data strobe signal line. Each memory module And transmits the data strobe signal transmitted from any of the memories included in the memory modules to the second data strobe signal line connected to any of the memories included in the memory module. An information processing system comprising: a data strobe signal control device that receives data from two data strobe signal lines and transmits the data strobe signal to the first data strobe signal line. 18. The information processing system according to claim 17, wherein said data strobe signal control device is provided in each of said memory modules, and each said data strobe signal control device is different from said first data strobe signal line. Are respectively connected to the storage controller,
Further, each of the data strobe signal control devices is connected only to each of the memories included in each of the provided memory modules by the second data strobe signal line.