JPH08102916A - Write clock generator ic tbc system - Google Patents

Abstract

PURPOSE: To improve time axis compensation performance of a TBC by generating a write clock of TBC high precisely synchronized with a reproduction signal. CONSTITUTION: A trapezoidal wave generating circuit 22 generates a trapezoidal wave having a slope with a prescribed phase relation to a horizontal synchronizing signal. Horizontal synchronizing signals of two consecutive lines are sampled respectively by using a sampling pulse generated from a WCLK by using a 1H delay circuit 26 and a sub error is generated by subtracting sampled values. The trapezoidal wave and the sub error are fed to a comparator 23, from which a horizontal timing signal subjected to phase control is generated to correct a phase shift by the sub error. The horizontal timing signal and a window from a timing generator 11 are fed to a phase comparator 13, in which an error signal is generated. The error signal is fed to a VCO 15 as a control signal via a loop filter 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a write clock generation device in a TBC system which can be applied to a player of an optical disc on which a MUSE signal of a high definition signal which is one of high definition television signals is recorded.

[0002]

2. Description of the Related Art Recording high-definition signals,
As a band compression method for transmission, MUSE (m
The ultiple sub-Nyquist sampling encoding) method has been proposed. The high-definition baseband signal bandwidth is 22 MHz for the luminance signal and 7 MHz for each of the two color difference signals. MUSE can compress this baseband signal to a bandwidth of about 8 MHz.

MU formed by MUSE encoder
The transmission format of the SE signal is shown in FIG. The MUSE signal is
It is a kind of pulse amplitude modulation signal, line number [1-1
125] and the sample numbers [1 to 480] in each line define the signal allocation. The sampling frequency is 16.2 MHz.

As shown in FIG. 13, the sample numbers [1 to 12] of each line are the horizontal synchronization (HD) period. The horizontal synchronizing signal has a waveform as shown in FIG. That is, the waveform has a level of (64 to 192) at an 8-bit quantization level, and the first and 2n-th lines (n ≧ 2) and the second and 2n + 1-th lines (however, With n ≧ 1), the waveform is inverted. Sample number [6] is the horizontal reference phase point. This horizontal reference phase point is a point at which the sampling phase is detected when resampling is performed.

A VIT (vertical interval test) signal and a frame pulse for vertical synchronization are inserted in the first and second lines of the MUSE signal. The VIT signal is a reference signal for equalizing the transmission path. further,
The edge of 473 samples of the second line is set as the frame reference phase point.

Details of allocation of C signal, Y signal, and voice / data are not particularly related to the present invention.
The allocation format is shown in and the description is omitted. However, regarding the level of the Y signal, as shown in FIG. 15, the black level is defined as (16) and the white level is defined as (239). The line number [564] is an empty area according to the standard, but in the example in which the MUSE signal is recorded on the optical disc, the control address signal is inserted in this line. The control address signal is a code signal that the player can use to control special functions and display time information.

The above-mentioned MUSE signal is FM-modulated and recorded on the optical disc. FIG. 16 is a frequency spectrum diagram of a signal recorded on the optical disc. S _M is the FM-modulated MUSE signal. The 8-bit quantization level 16 of the MUSE signal has a frequency f ₁ (= 10.6 MHz), and the 8-bit quantization level 128 has a frequency f ₂ (= 1
The MUSE signal is FM-modulated so that the frequency becomes 4.4 MHz. Further, the digital signal S _EFM and the pilot signal S _P are frequency-multiplexed on the low frequency side of the FM modulated signal S _M.

The digital signal S _EFM has a signal form similar to that of a compact disc and is an EFM-modulated digital audio or video signal. The pilot signal S _P has a frequency f _P and is a time base reference signal. The pilot signal S _P is continuously recorded on the optical disc. The frequency f _P is the horizontal frequency f
It has been selected for the following relationship with _H. f _P = 135/2 x f _H (= 2278125Hz)

A player that reproduces an optical disc on which a MUSE signal is recorded as described above is equipped with a TBC system that removes a time-axis fluctuation component of the reproduced MUSE signal. This TBC system generally generates a write clock that is synchronized with the replay MUSE signal, which writes the replay MUSE signal to the memory, while a stable reference read clock regenerates the memory from the memory.
The USE signal is read out. The write clock is generated by the PLL so as to synchronize with the pilot signal S _P in the reproduced MUSE signal or the horizontal synchronizing signal HD.

[0010]

The performance of the TBC system affects the quality of reproduced images and reproduced sounds. Especially MU
When the signal (luminance signal, color signal, audio signal, control information, etc.) is defined by the line number and the sample number like the SE signal, the signal reproduced from the recording medium such as a disc. , Which includes the time-axis fluctuation, the MUSE decoder reproduces the MUSE
An error occurs in the process of decomposing the signal into each signal component, and the quality of the reproduced image and reproduced sound is impaired.

Therefore, an object of the present invention is to provide a write clock generation device in a TBC system capable of sufficiently removing the fluctuation of the time axis and improving the quality of reproduced images and reproduced voices. It is in.

[0012]

SUMMARY OF THE INVENTION The present invention is a write clock generator in a TBC system for removing a time-axis fluctuation component of an input signal including a synchronizing signal whose amplitude is regulated and which is periodically inserted. Then, the error signal from the phase comparator is supplied to the VCO through the loop filter,
A PLL that generates a write clock for writing an input signal to the memory based on the output signal of the VCO, and a phase shift between the synchronization signal and the signal generated based on the write clock are detected for each cycle of the synchronization signal. Then, a means for generating a sub error signal that indicates a phase shift and a horizontal timing signal generation that generates a horizontal timing signal in which the phase of the synchronization signal extracted from the input signal is controlled by the sub error signal so as to correct the phase shift And a means for comparing the horizontal timing signal with a write clock or a signal generated from the write clock by a phase comparator.

[0013]

By comparing the phase of the sync signal in the input signal with the phase of the signal generated from the write clock for each cycle, the phase shift between the sync signal and the write clock generated in this one cycle can be detected. . A horizontal timing signal is generated in which the phase of the synchronization signal extracted by the sub error is changed so as to correct this phase shift. This horizontal timing signal and the write clock, or the timing signal generated from the write clock are phase-compared,
An error is formed, which controls the oscillation frequency of the VCO. With this configuration, the time base compensation performance of TBC is improved.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the entire configuration of this embodiment, and 1 is an optical disc. In this optical disc 1,
As described above, a signal in which the FM-modulated MUSE signal S _M , the digital signal S _EFM, and the pilot signal S _P are frequency-multiplexed is recorded. The optical disk 1 is rotationally driven by a spindle motor 2 in a CAV (constant angular velocity) or CLV (constant linear velocity) method. Three
Is a spindle control circuit for controlling the rotation speed and rotation phase of the spindle motor 2.

The recording signal of the optical disk 1 is read by the optical pickup 4. Although not shown, a feed mechanism for moving the pickup 4 in the radial direction of the disc 1 is provided. As the rotational drive of the optical disc 1, the structure of the pickup 4, the feed mechanism of the pickup 4, and the like, conventionally known ones can be adopted.

The reproduction signal read by the pickup 4 is supplied to the bandpass filters 6 and 7 through the reproduction amplifier 5, respectively. By the bandpass filter 6,
The FM modulated MUSE signal S _M is separated, and the bandpass filter 7 separates the pilot signal S _P. The signal S _M is FM demodulated by the FM demodulation circuit 8, and the reproduced MUSE signal generated at its output is supplied to the A / D converter 9, the sync separation circuit 10 and the TBC (time base corrector) signal generator 12, respectively. . The pilot signal S _P from the bandpass filter 7 is supplied to the TBC signal generator 12. The TBC signal generator 12 supplies a signal for phase servo and a signal for speed servo to the spindle control circuit 3. For these circuits, VCO1
The write clock WCLK is supplied from 5.

The TBC in this embodiment is a reproduction MU.
The horizontal sync signal in the SE signal is used. in this case,
You may make it use TBC together which used the pilot signal. The TBC signal generator 12 generates a signal for the spindle control circuit 3 and extracts the horizontal sync signal from the reproduced MUSE signal, as described later, so as to correct the time axis fluctuation in one line period. A timing signal (hereinafter referred to as a horizontal timing signal) RFZ in which the phase of the synchronization signal is changed is generated. The horizontal timing signal RFZ from the TBC signal generator 12 is supplied to the phase comparator 13 as one input signal.

The A / D converter 9 has a write clock WCL.
Using K, the reproduced MUSE signal is sampled at a frequency of 16.2 MHz or an integral multiple thereof, and one sample outputs a digital MUSE signal of 8 bits. The sync separation circuit 10 detects the frame pulse inserted in the line numbers [1] and [2] in the MUSE signal,
As described later, the load signal LD as a timing reference
Generate S. The load signal LDS and the write clock WCLK are supplied to the timing generator 11, and the timing generator 11 generates various timing signals necessary for reproduction processing.

As the other input signal of the phase comparator 13,
In the timing generator 11, the write clock WCL
A window formed from K is provided. The horizontal timing signal RFZ and a comparison output (error) corresponding to the phase difference of the window are generated from the phase comparator 13, and this comparison output is transmitted via the loop filter 14 to the VCO (voltage contr).
olled oscillator) 15 is supplied as a control voltage. The VCO 15 changes the oscillation frequency according to the control voltage, and the write clock WCLK is generated at its output.

A PLL is constituted by the phase comparator 13, the loop filter 14 and the VCO 15, and a write clock WCLK synchronized with the horizontal timing signal RFZ from the TBC signal generator 12, that is, synchronized with the reproduced MUSE signal is generated. It This write clock WCL
K is supplied to the memory 16 for TBC, and the digital signal from the A / D converter 9 is used as the write clock WCLK.
Is written in the memory 16. The memory 16 is R
It is composed of AM, FIFO and the like.

On the other hand, according to the read clock RCLK,
Data is read from the memory 16. The read clock RCLK is formed by dividing the master clock generated by the crystal oscillator and is a stable clock. Therefore, the time axis fluctuation included in the reproduced MUSE signal is removed by the TBC including the memory 16, and the read data of the memory 16 does not include the time axis fluctuation. Although not shown, the signal read from the memory 16 is converted back into an analog MUSE signal by the D / A converter and further supplied to the MUSE decoder.
The reproduced color video signal is obtained by the MUSE decoder.

Further, in FIG. 1, reference numeral 17 denotes a control address signal decoder. This decoder 17
On the other hand, the digital MUSE signal from the A / D converter 9, the timing signal from the timing generator 11, and the write clock WCLK from the VCO 15 are supplied. In this decoder 12, the control address signal inserted in the line number [564] of the MUSE signal is read and decoded. The decoder 17 and the microcomputer 18 are combined, and the control information and the address information obtained by the decoder 17 are used for controlling the disc reproducing operation and displaying the address.

Next, an example of the configuration of the timing generator 11 will be described. The timing generator 11 is a two-stage counter that operates by the write clock WCLK. The write clock WCLK is supplied from the VCO 15 as described above. The structure of the timing generator 11 is shown in FIG. Reference numeral 31 is a first counter, which is called a sample counter here. Three
2 is a load signal input terminal of the sample counter 31. Reference numeral 33 is a clock signal input terminal of the sample counter 31. 34 is a carry signal output end of the sample counter 31. Reference numeral 35 is a second counter, which is called a line counter here. 36 is a load signal input terminal of the line counter 35. 37 is
It is a clock signal input terminal of the line counter 35. Further, 40 is an output end of the sample counter 31, which is 4
1 is an output end of the line counter 35.

The load signal LDS from the outside is supplied to the load signal input terminal 32 of the sample counter 31 and the load signal LDS input terminal 36 of the line counter 35, respectively. The carry signal output end 34 of the sample counter 31 is connected to the enable terminal E of the line counter 35.
It is connected to T.

When the load signal LDS is input to the load signal input terminal 32 and the load signal input terminal 36 of the sample counter 31 and the line counter 35, the load data is loaded into the counter 31 and the counter 35, respectively. Further, the sample counter 31 increments by the write clock WCLK supplied to the clock input terminal 33. When the count value reaches the maximum value preset in the sample counter 31,
Carry signal CA is output from carry signal output terminal 34, and the count value returns to [1]. This carry signal CA
Is supplied to the clock signal input terminal 37 of the line counter 35. Thereby, the line counter 35 increments. The count value is the sample counter 35.
When the maximum value set in advance is reached, the count value returns to [1].

The load signal LDS input to the load signal input terminal 32 and the load signal input terminal 36 described above is as shown in FIG.
It is generated from the frame pulse in the MUSE signal separated by the sync separation circuit 10 of FIG. That is, as shown in FIG. 3, the sync separation circuit 10 extracts the frame pulse of the line number [1] and the line number [2] from the signal supplied from the A / D converter 9. However, in FIG. 3, only the waveform of the line number [2] is shown. Then, the frame reference phase point included in the frame pulse of the line number [2] is detected, and the load signal LDS having this point as the trailing edge of the pulse is generated.

Here, an example of the operation of the timing generator 11 will be described with reference to the timing chart of FIG. FIG. 4A shows the write clock WCLK supplied to the clock signal input terminal 33 of the sample counter 31. FIG. 4B shows the load signal LDS described above,
It is supplied from the sync separation circuit 10. Sample counter 3
1 and the line counter 35, when the load signal LDS of FIG. 4B is supplied from the sync separation circuit 10, the preset load data 38 and load data 39 are set, respectively.
Is loaded. In this example, in response to the load signal LDS occurring at the frame reference phase point in the reproduction MUSE signal, the load data 38 represents the value [473], and the load data 39 represents the value [2]. Has been done.

By loading these load data, the sample counter 31 and the line counter 3
5 outputs the same value as the load data from the respective data output terminals 40 and 41, as shown in FIGS. 4C and 4D. The count timing after loading the load data is, as described above, the sample counter 31
Represents the timing of the write clock WCLK, and the line counter 35 represents the timing of the carry signal CA supplied from the sample counter 31.

From the outputs of the sample counter 31 and the line counter 35, for example, a window pulse for timing extraction can be generated. As an example, FIG.
As shown in E, a window can be generated at the position of the sample number [473 to 475] of the line number [2] in the reproduced MUSE signal. The timing of the window generated in this way is such that the load signal LDS is MU.
Synchronous separation circuit 1 from frame pulse included in SE signal
0, and write clock WCL
Since K is formed so as to be synchronized with the reproduced MUSE signal, it is synchronized with the reproduced MUSE video signal.

FIG. 5 shows an example of the configuration of the TBC signal generator 12. However, the configuration of signal generation for the spindle control circuit 3 is omitted. In FIG.
21 is a reproduced MUSE signal ADVI from the FM demodulator 8.
It is a horizontal synchronization extracting circuit for extracting the horizontal synchronization signal HD during DEO. FIG. 6A shows the horizontal synchronizing signals of the N line and the N + 1 line. The timing signal XAHDEDG (FIG. 6) having a falling edge from the horizontal synchronization sampling circuit 21 to a predetermined position of the horizontal synchronization signal, for example, a position of a predetermined delay amount DL from the horizontal phase reference point (sample number [6]).
B) occurs.

This timing signal XAHDEDG is supplied to the trapezoidal wave generating circuit 22 and has a trapezoidal wave TR having a constant positive slope portion starting from the falling edge thereof.
APE is formed. The trapezoidal wave TRAPE is supplied to the comparator 23. The TBC sub error is supplied to the other input of the comparator 23. As shown in FIG. 6C, the sub-error is a DC component, and for example, when the central level of the inclined portion of the trapezoidal wave TRAPE and the sub-error match, the lock center of the PLL is set.
As shown in FIG. 6D, the comparator 23 outputs a horizontal timing signal RFZ which rises at the timing when the sub error and the level of the inclined portion of the trapezoidal wave TRAPE match.

To generate a TBC sub-error, A /
The digital MUSE signal (1 sample is 8 bits) from the D converter 9 is supplied to the sampling / holding circuit 24. The output of the sampling / hold circuit 24 is supplied to the adder 25 and the 1-line (1H) delay circuit 26. The output of the 1-line delay circuit 26 is inverted and supplied to the adder 25. As shown in FIG. 7, the one-line delay circuit 26 includes a delay circuit 26a and a sampling / hold circuit 26b on the output side thereof.

In the case of the MUSE signal, one line is 48
Since it is specified as 0 sample, the write clock WC
A delay of one line period can be performed using LK as a clock. Further, the timing generator 11 generates the sampling pulse Ph having the sampling phase corresponding to the horizontal reference phase point (sample number [6] of each line) in one line period. At the output of the 1H delay circuit 26, as shown in FIG. 8A, the level of the horizontal reference phase point of the Nth line is generated, while at the output of the sampling / holding circuit 24, as shown in FIG. 8B, The level of the horizontal reference phase point of the (N + 1) th line occurs.

The adder 25 produces an output obtained by subtracting the sampling value of the line N from the sampling value of the line [N + 1]. This subtraction output is a code signal, and this subtraction output is supplied to the conversion circuit 27 and converted into a DC signal. As the conversion circuit 27, for example, a pulse width modulation (PWM) circuit and an integration circuit that integrates the pulse width modulation signal can be used. This produces a pulse with a pulse width that is weighted corresponding to each bit of the subtraction output, and outputs a '0' and
Corresponding to `1 ', pulse width modulation is performed by selectively generating pulses.

If the write clock WCLK is the reproduction MU
If completely synchronized with the SE signal, the sampling / hold value of the line [N] and the sampling / hold value of the line [N + 1] are at the same level, and the subtraction output is
0. If not, these two sampling / hold values are not equal, and a subtraction output of the polarity and level corresponding to the phase shift of one line period is generated. By converting the subtraction output into a DC signal, a TBC sub error is obtained. By supplying this TBC sub error to the comparator 23, the phase of the horizontal timing signal RFZ is changed as described above. This phase change is set so as to control the oscillation frequency of the VCO 15 in the direction in which the subtraction output is set to 0.

In this way, after the phase control using the TBC sub error is performed, the phase comparator 13 compares the phase of the horizontal timing signal RFZ with the window from the timing generator 11. AHDWIN, VCOL, and VCOR shown in FIGS. 6E, 6F, and 6G, respectively
Is an example of a window. And shown in FIG.
Regarding the phase relationship between these windows and the horizontal timing signal RFZ, the error (comparison output) shown in FIG. 6H is generated from the phase comparator 13. This error is supplied to the VCO 15 via the loop filter 14.

FIG. 9 shows an example of the configuration of the phase comparator 13. This includes NAND gates 51 and 52, OR gates 53 and 54, and tristate circuits 55 and 5.
6, a resistor 57, 58 and a buffer 59. The window VCOFL (FIG. 10A) is supplied to one input terminal of the NAND gate 51, and the window VCOFR is supplied to one input terminal of the NAND gate 52.
(FIG. 10B). These windows are pulses having a predetermined width before and after the phase reference of the write clock WCLK indicated by the arrow.

As the other input of the NAND gate 51,
Timing signal REFF having a rising edge that matches the phase reference of horizontal timing signal RFZ (see FIG. 10).
E) is provided and the other input of the NAND gate 52 is provided with the timing signal REFFI (FIG. 10D) having a falling edge that matches the phase reference of the horizontal timing signal RFZ. The outputs of these NAND gates 51 and 52 are supplied to one input terminals of OR gates 53 and 54. The TBC hold signal HLD is supplied to the other input terminals of the OR gates 53 and 54.

The TBC hold signal HLD is a control for holding the error signal in the previous state in order to prevent an abnormal error signal from being generated when the horizontal synchronizing signal cannot be extracted due to dropout or the like. Signal (active at'H '). That is, in the steady operation, the hold signal HLD is'L '.

The OR gates 53 and 54 output the output PCO.
H and PCOL are set to tristate circuits 55 and 56.
Supply to each control terminal of. Tristate 55
Is'H '(eg + 5V) when PCOH is'L'
The tri-state 56 outputs “L” (for example, 0V) when PCOL is “L”. The output signals of the two tri-state circuits 55 and 56 are resistors 57 and 5,
8 and the buffer 59. Buffer 5
An error occurs from 9.

In the configuration of FIG. 9, in the phase relationship shown by the solid line in FIG. 10, output PCOH is generated as shown in FIG. 10F, and PCOH is generated as shown in FIG. 10H.
An error of + 5V occurs in the period of “L”. on the other hand,
In the case of the phase relationship shown by the broken line, as shown in FIG. 10G, an error of 0V occurs during the period when PCOL is'L '. The output of the tri-state circuit 55 is open during the period when PCOH is “H”, and the output of the tri-state circuit 56 is open during the period when PCOL is “H”.

FIG. 11 shows another structural example of the phase comparator 13. Similar to the example of FIG. 9, NAND gates 61 and 6
2, OR gates 63 and 64, tristate circuit 5
5 and 56, resistors 57 and 58, and a buffer 59. The window VCOF (FIG. 12A) is commonly supplied to one input terminal of each of the NAND gates 61 and 62. The window VCOF is a pulse whose center position corresponds to the phase reference of the write clock WCLK and which has a predetermined width in the front and rear around this center.

Similar to the configuration of FIG. 9, NAND gate 61
As the other input of the timing signal REFF (FIG.
D) is supplied, and the timing signal REFFI (FIG. 12C) is supplied to the other input of the NAND gate 62. The outputs of these NAND gates 61 and 62 are O
It is supplied to one input terminal of the R gates 63 and 64. To the other input terminals of the OR gates 63 and 64, T
The BC hold signal HLD is supplied as in FIG. 9.

The phase comparator having the configuration shown in FIG.
In the phase relationship between the window VCOF and the horizontal timing signal RFZ as shown in FIG. 2, the tri-state circuits 55 and 56 are controlled by the pulses PCOH and PCOL shown in FIGS. 12E and 12F, and the error shown in FIG. 12G occurs.

A phase comparator other than the above-mentioned configuration may be used. Further, the present invention can be applied not only to the MUSE signal but also to a TBC system of a reproducing device of a video signal such as an NTSC signal or an audio signal. Furthermore, the present invention can be applied to a TBC for a reproduction signal of a recording medium such as a magneto-optical disc, a magnetic disc, a magnetic tape other than the optical disc.

[0046]

According to the present invention, in forming the phase error signal for the VCO of the PLL, the phase comparison for detecting the phase shift for each cycle of the sync signal, the phase of the sync signal and the write clock, or the combination thereof is formed. Since the phase comparison with the window is doubled, the reproduction signal and the write clock can be synchronized with each other with high accuracy. Therefore, T
The time axis variation due to BC can be removed well, and the quality of reproduced signals such as reproduced images and reproduced sounds can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention.

FIG. 2 is a block diagram of an example of a timing generator according to an embodiment of the present invention.

FIG. 3 is a timing chart for explaining generation of a load signal in a timing generator.

FIG. 4 is a timing chart for explaining a timing generator.

FIG. 5 is a block diagram for explaining a configuration for generating a TBC write clock according to an embodiment of the present invention.

FIG. 6 is a timing chart schematically illustrating a write clock generation operation in one embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration for generating a TBC sub-error in one embodiment of the present invention.

FIG. 8 is a partial waveform chart for explaining a TBC sub-error generation operation in the embodiment of the present invention.

FIG. 9 is a block diagram of an example of a phase comparator.

FIG. 10 is a timing chart of the operation of an example of a phase comparator.

FIG. 11 is a block diagram of another example of the phase comparator.

FIG. 12 is a timing chart of the operation of another example of the phase comparator.

FIG. 13 is a schematic diagram showing a signal format of a MUSE signal.

FIG. 14 is a waveform diagram for explaining a horizontal synchronizing signal in a MUSE signal.

FIG. 15 is a schematic diagram for explaining the level of a horizontal synchronizing signal.

FIG. 16 is a frequency spectrum diagram for explaining a recording signal of an optical disc to which the present invention can be applied.

[Explanation of symbols]

 1 Optical Disc 4 Pickup 8 FM Demodulator 11 Timing Generator 12 TBC Signal Generator 13 Phase Comparator 15 VCO 21 Horizontal Sync Extraction Circuit 22 Trapezoidal Wave Generation Circuit

Claims (3)

[Claims] 1. A write clock generator in a TBC system for removing a time-axis fluctuation component of an input signal including a synchronizing signal whose amplitude is specified, which is periodically inserted, wherein an error from a phase comparator is provided. A signal is supplied to the VCO through a loop filter, and a PLL that generates a write clock for writing the input signal in the memory based on the output signal of the VCO, the synchronization signal, and the PLL based on the write clock Means for detecting a phase shift from the synchronized signal for each cycle of the synchronizing signal and generating a sub error signal for instructing the phase shift; and the above-mentioned extracted from the input signal so as to correct the phase shift. A horizontal timing signal generating means for generating a horizontal timing signal whose phase of the synchronization signal is controlled by the sub-error signal; And timing signal, the write clock or the write clock generator in TBC systems, characterized by phase comparing the signal generated from the write clock by said phase comparator. 2. The write clock generation device according to claim 1, wherein the sub-error signal has a level according to a phase shift, and the horizontal timing signal generation means has a constant phase with the phase of the extracted synchronization signal. An apparatus configured to generate a horizontal timing signal by performing a level comparison between the slope waveform and the sub-error signal with a means for generating a slope waveform having a phase relationship of. 3. The write clock generator according to claim 1 or 2, wherein the input signal is a MUSE signal reproduced from a recording medium.