JPH08102488A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH08102488A
JPH08102488A JP19463195A JP19463195A JPH08102488A JP H08102488 A JPH08102488 A JP H08102488A JP 19463195 A JP19463195 A JP 19463195A JP 19463195 A JP19463195 A JP 19463195A JP H08102488 A JPH08102488 A JP H08102488A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor device
mirror
semiconductor
polished
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19463195A
Other languages
Japanese (ja)
Other versions
JP2581531B2 (en
Inventor
Masaru Shinpo
優 新保
Kazuyoshi Furukawa
和由 古川
Hiromichi Ohashi
弘通 大橋
Junichi Oura
純一 大浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP7194631A priority Critical patent/JP2581531B2/en
Publication of JPH08102488A publication Critical patent/JPH08102488A/en
Application granted granted Critical
Publication of JP2581531B2 publication Critical patent/JP2581531B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE: To manufacture a semiconductor device of dielectric isolation structure, with a very simple process, and obtain excellent element characteristics. CONSTITUTION: In the manufacturing method of a semiconductor device of dielectric isolation structure, a mirror-finished Si substrate 11 on which surface an N<+> type layer 12 is formed and a mirror-finished Si substrate 13 on which surface an oxide film 14 is formed are bonded to each other by mutually sticking the polised surfaces whose roughness is 50nm or less, in a clean atmosphere in which foreign matters are not contained practically. Then the bonded compound body is heated at a temperature of 200 deg.C or higher, thereby improving the bonding strength. A plurality of desired elements are formed on the Si substrate 11 side of the bonded substrates which have been obtained. The elements are dielectrically isolated in the horizontal direction, by element isolation trenches 16 and passivation glass 17 buried in the trenches 16.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、誘電体分離された
半導体装置の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a dielectric isolation.

【0002】[0002]

【従来の技術】各種光センスやディスプレイ用として、
半導体素子の一次元及び二次元マトリクスの用途は多
い。このような素子のマトリクスにおいては、各素子が
電気的に完全に分離されていることが必須であり、特に
高耐圧素子や光センサなどにおいては誘電体分離が必須
のものとなる。
2. Description of the Related Art For various light senses and displays,
There are many uses for one-dimensional and two-dimensional matrices of semiconductor devices. In such a matrix of elements, it is essential that the elements are completely electrically separated from each other. In particular, dielectric isolation is essential for a high breakdown voltage element, an optical sensor, and the like.

【0003】従来、誘電体分離された素子マトリクスを
形成する方法としては、例えば絶縁基板上にエピタキシ
ャル法や各種蒸着法により形成された半導体薄膜を用い
ることが行われている。しかし、これらの方法では、 (1) 半導体薄膜を十分厚く形成することができないた
め、高耐圧,大電流の素子が作れない。
Conventionally, as a method of forming a device matrix in which dielectrics are separated, for example, a semiconductor thin film formed on an insulating substrate by an epitaxial method or various vapor deposition methods is used. However, according to these methods, (1) a semiconductor thin film cannot be formed sufficiently thick, so that a device with a high breakdown voltage and a large current cannot be produced.

【0004】(2) 良質の半導体膜が得られないため、素
子特性に限度がある。 (3) 不純物濃度や分布等の制御が難しく、素子構造に制
限がある。等の問題があった。
(2) Since a high-quality semiconductor film cannot be obtained, there is a limit to element characteristics. (3) It is difficult to control the impurity concentration and distribution, and the element structure is limited. There was a problem such as.

【0005】一方集積回路では、単結晶基板上にエピタ
キシャル法により半導体膜を形成してこれに素子を形成
し、その後に基板をラッピングして除去してから裏面に
酸化膜等の絶縁膜を形成し素子分離する方法が知られて
いる。しかしこの方法は、非常に複雑な工程を必要とす
る欠点がある。
On the other hand, in an integrated circuit, a semiconductor film is formed on a single crystal substrate by an epitaxial method, elements are formed thereon, and then the substrate is wrapped and removed, and then an insulating film such as an oxide film is formed on the back surface. There is known a method for element isolation. However, this method has the drawback of requiring very complicated steps.

【0006】さらに、絶縁基板上に堆積した多結晶半導
体膜を、レーザや電子ビームなどで熱処理して単結晶化
して素子を形成する技術が、最近注目されている。しか
しこの方法も、結晶の完全性や膜厚,形状の制御などの
点で未だ解決すべき問題が多い。
Further, a technique of forming a device by subjecting a polycrystalline semiconductor film deposited on an insulating substrate to heat treatment with a laser, an electron beam, or the like to form a single crystal has recently been receiving attention. However, this method still has many problems to be solved in terms of control of crystal perfection, film thickness and shape.

【0007】[0007]

【発明が解決しようとする課題】このように従来、誘電
体分離された素子マトリクスを形成するには各種の方法
があるが、簡便な工程でしかも優れた素子特性を得るこ
とはできないのが現状であった。
As described above, conventionally, there are various methods for forming a device matrix separated from a dielectric material. However, excellent device characteristics cannot be obtained by simple steps. Met.

【0008】本発明は、上記した点に鑑みて成されたも
ので、極めて簡便な工程でしかも優れた素子特性を得る
ことのできる、誘電体分離構造の半導体装置を製造する
方法を提供することを目的とする。
The present invention has been made in view of the above points, and provides a method of manufacturing a semiconductor device having a dielectric isolation structure, which is capable of obtaining excellent device characteristics in a very simple process. With the goal.

【0009】[0009]

【課題を解決するための手段】本発明においては、誘電
体分離基板を得るため、それぞれ鏡面研磨された半導体
基板と絶縁性基板とを研磨面同士を直接接着して一体化
する技術を用いる。即ち、表面荒さ50nm以下に鏡面
研磨された基板同士を実質的に異物を含まない清浄な雰
囲気中で密着させ、200℃以上の温度で熱処理すると
強固な接着基板が得られる。絶縁性基板は半導体基板表
面に絶縁膜を形成したもの、或いは全体が誘電体からな
るもの、いずれでもよい。
In the present invention, in order to obtain a dielectric isolation substrate, a technique is used in which a mirror-polished semiconductor substrate and an insulating substrate are integrated by directly bonding their polished surfaces to each other. That is, when substrates mirror-polished to a surface roughness of 50 nm or less are brought into close contact with each other in a clean atmosphere substantially free from foreign matter, and heat-treated at a temperature of 200 ° C. or more, a strong bonded substrate is obtained. The insulating substrate may be either a semiconductor substrate having an insulating film formed on its surface, or a substrate entirely made of a dielectric material.

【0010】このようにして縦方向に分離された基板に
所望の素子を形成し、また素子の横方向分離を行うため
に半導体基板側に溝を形成してこの溝に非晶質材料を充
填する。高耐圧,大電流の素子群を形成するためには、
どうしても各素子の厚さを大きくすることが必要であ
る。例えば、1000V以上の耐圧を実現するためには
100μm以上の厚さを必要とする。このような素子を
横方向に溝で分離する場合、この溝を横切って配線する
ことは難しいため、溝を誘電体で埋め込むことが必要に
なる。
A desired element is formed on the substrate thus separated in the vertical direction, and a groove is formed on the semiconductor substrate side for separating the element in the horizontal direction, and the groove is filled with an amorphous material. I do. In order to form a device group with high withstand voltage and large current,
It is absolutely necessary to increase the thickness of each element. For example, a thickness of 100 μm or more is required to realize a breakdown voltage of 1000 V or more. When such an element is separated by a groove in the lateral direction, it is difficult to wire across the groove, and it is necessary to fill the groove with a dielectric.

【0011】本発明において基板を直接接着するには、
基板の平滑度が重要であり、表面荒さ50nm以下の鏡
面に仕上げることが望ましい。このような鏡面では、密
着により両基板が自力的に接合することになる。そして
この場合、自力的な接合であることから、加熱的に外圧
を加える必要がない。従って、圧力による歪みなどが殆
ど残留しない良好な基板が得られる。なお、接着すべき
基板表面が汚染されている場合には、トリクレンなどの
溶剤により脱脂、中性洗剤によるこすり洗い、H22
/H2 SO4 混合液浸漬等の手法で清浄化する。その後
水洗し、スピンナなどを用いて脱水する。
In the present invention, in order to directly adhere a substrate,
The smoothness of the substrate is important, and it is desirable to finish the substrate with a mirror surface having a surface roughness of 50 nm or less. With such a mirror surface, the two substrates will be joined together by close contact. In this case, since the joining is performed by itself, there is no need to apply an external pressure for heating. Therefore, a good substrate in which distortion due to pressure and the like hardly remains can be obtained. If the surface of the substrate to be bonded is contaminated, the surface is degreased with a solvent such as trichlene, rubbed with a neutral detergent, H 2 O 2
/ H 2 SO 4 mixed solution is used for cleaning. After that, it is washed with water and dehydrated using a spinner or the like.

【0012】これらの処理を経た半導体基板と絶縁性基
板を、例えばクラス1以下の清浄な雰囲気下で密着させ
200℃以上に加熱して強固な接合体基板を得る。得ら
れた接合体基板の半導体基板側に通常の拡散法等により
所望の素子を形成する。そして、絶縁性基板に達する深
さに素子分離溝を形成する。この素子分離溝は、ダイヤ
モンド・ソウによる方法、エッチング方法等を用いて形
成する。素子分離溝には、各種半導体素子のパシベーシ
ョンに用いられているガラス,非晶質半導体等の非晶質
材料を充填する。例えば、パシベーション・ガラスの粉
末を電着法やスクリーン印刷法,沈降法等で被覆し、ガ
ラスが軟化流動するまで昇温して緻密化する。
The semiconductor substrate and the insulating substrate that have undergone these treatments are brought into close contact with each other in a clean atmosphere of class 1 or lower, and heated to 200 ° C. or higher to obtain a strong bonded substrate. A desired element is formed on the semiconductor substrate side of the obtained bonded substrate by a usual diffusion method or the like. Then, an element isolation groove is formed at a depth reaching the insulating substrate. This element isolation groove is formed by using a diamond-saw method, an etching method, or the like. The element isolation groove is filled with an amorphous material such as glass or an amorphous semiconductor used for passivation of various semiconductor elements. For example, passivation glass powder is coated by an electrodeposition method, a screen printing method, a sedimentation method, or the like, and the temperature is increased until the glass softens and flows, thereby densifying the glass.

【0013】そして、被覆した非晶質材料膜をラッピン
グして素子分離溝部にのみ非晶質材料を残す。これによ
り、半導体素子面と非晶質材料面が同じ高さになるか
ら、この後所望の素子配線を容易に形成することができ
る。
Then, the coated amorphous material film is wrapped to leave the amorphous material only in the element isolation trench. As a result, the semiconductor element surface and the amorphous material surface have the same height, and thereafter, a desired element wiring can be easily formed.

【0014】[0014]

【発明の実施の形態】以下、本発明の実施形態を図面を
参照して説明する。 (実施形態1)図1及び図2は、本発明の第1の実施形
態に係わる半導体装置の製造工程を示す断面図である。
まず、図1(a)に示すように、厚さ400μm,不純
物濃度1014cm-3程度の鏡面研磨された二枚の(11
1)n- 型Si基板を用意する。そして、一方の基板1
1の研磨面にはリンを拡散して表面濃度1013cm-3
度のn+ 型層12を形成し、他方の基板13の研磨面に
は1200℃,6時間のウェット酸化により酸化膜14
を形成した。両基板は中性洗剤でこすり洗いしてゴミを
除いた後、H22 :H2 SO4 =1:4の液に浸漬し
て30分煮沸し、水洗した。表面状態によっては更に、
HFによる前処理,稀HFによる前処理を行う。
Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIGS. 1 and 2 are cross-sectional views showing steps of manufacturing a semiconductor device according to a first embodiment of the present invention.
First, as shown in FIG. 1 (a), two mirror-polished (11) layers having a thickness of 400 μm and an impurity concentration of about 10 14 cm −3 were used.
1) An n - type Si substrate is prepared. And one of the substrates 1
Phosphorus is diffused on the polished surface of No. 1 to form an n + -type layer 12 having a surface concentration of about 10 13 cm −3 , and the oxide film 14 is formed on the polished surface of the other substrate 13 by wet oxidation at 1200 ° C. for 6 hours.
Was formed. Both substrates were scrubbed with a neutral detergent to remove dust, immersed in a solution of H 2 O 2 : H 2 SO 4 = 1: 4, boiled for 30 minutes, and washed with water. Depending on the surface condition,
Pre-processing by HF and pre-processing by rare HF are performed.

【0015】その後、両基板をスピンナで脱水処理し、
クラス1の清浄な雰囲気下で研磨面同士を、図1(b)
に示すように直接接着し、窒素雰囲気下で1000〜1
200℃、2時間の熱処理をして接着力を強くした。ス
ピンナでの脱水処理は鏡面研磨面の過剰な水分を除去す
るためで、この吸着水分が殆ど蒸発する100℃以上の
乾燥は避ける。こうして得られた接着基板のn+ 型層1
2を形成した側の基板11をラッピングして、接着面か
らの厚みを100μm程度にし、その後で硼素を拡散し
て、図1(c)に示すように厚さ20μm程度のp+
層15を形成した。
Thereafter, both substrates are dehydrated with a spinner,
The polished surfaces are put together in a clean atmosphere of class 1 as shown in FIG.
As shown in FIG.
Heat treatment was performed at 200 ° C. for 2 hours to increase the adhesive strength. The spinner is used to remove excess water from the mirror-polished surface, and avoid drying at 100 ° C. or higher where most of the absorbed water evaporates. N + -type layer 1 of adhesive substrate thus obtained
2 is formed by lapping the substrate 11 so that the thickness from the bonding surface is about 100 μm, and then boron is diffused to form ap + type layer 15 having a thickness of about 20 μm as shown in FIG. Was formed.

【0016】次いで、全面を酸化膜18で覆い、40μ
m幅のダイヤモンド・ソウを用いて深さ70μm,幅1
00μmの素子分離溝16を3mmピッチで形成し、破
砕層を除去した。この状態が図2(a)である。この
後、図2(b)に示すように、電気泳導法により鉛系パ
シベーション・ガラス17(IP−760,イノチック社商
品名)を溝16に充填し、焼成した。この後は図示しな
いが、コンタクトホールを開けてAl配線を施してダイ
オードアレイを作った。
Next, the entire surface is covered with an oxide
Depth 70 μm, width 1 using m-width diamond saw
Element isolation grooves 16 of 00 μm were formed at a pitch of 3 mm, and the crushed layer was removed. This state is shown in FIG. After that, as shown in FIG. 2 (b), lead-based passivation glass 17 (IP-760, trade name of Inotic Co.) was filled in the groove 16 by an electroconduction method and baked. Thereafter, although not shown, a contact hole was opened and Al wiring was provided to form a diode array.

【0017】得られたダイオードアレイは、各素子とも
耐圧1200Vを示し、素子間絶縁も十分であった。こ
のように本実施形態によれば、簡便な方法で誘電体分離
された半導体素子群を得ることができる。特に、基板の
縦方向の分離は半導体基板と絶縁性基板の直接接着法を
利用するため、素子の厚みを自由に選択することがで
き、高耐圧,大電流のダイオードやトランジスタのマト
リクスなどを形成する場合に有効であり、また各種光セ
ンサや電力用集積回路等に適用して有用である。また、
深さ横方向の素子分離溝は非晶質材料で充填することに
より、素子配線の形成も容易である。 (実施形態2)次に、本発明の第2の実施形態を図3及
び図4を参照して説明する。
The obtained diode array showed a withstand voltage of 1200 V for each element, and the insulation between the elements was sufficient. As described above, according to the present embodiment, it is possible to obtain a semiconductor element group that is dielectrically separated by a simple method. In particular, since the vertical separation of the substrate uses a direct bonding method between the semiconductor substrate and the insulating substrate, the thickness of the element can be freely selected, and a high voltage, large current diode or transistor matrix is formed. It is effective in the case where it is performed, and is useful when applied to various optical sensors, power integrated circuits, and the like. Also,
By filling the element isolation groove in the lateral direction with an amorphous material, the element wiring can be easily formed. (Embodiment 2) Next, a second embodiment of the present invention will be described with reference to FIGS.

【0018】図3(a)に示すように、不純物濃度10
15cm-3程度の鏡面研磨された(100)n- 型Si基
板21と、同じく鏡面研磨された無アルカリガラス基板
24(NA−40,保谷ガラス社商品名)を用意した。n
- 型Si基板21の研磨面には、弗酸−硝酸混液による
化学エッチングで幅200μm,深さ100μm,ピッ
チ1mmの溝22を形成し、更にリン拡散を行って20
μmの深さのn+ 型層23を形成した。両基板は先の実
施形態と同様に研磨面を脱脂処理,清浄化処理を行い、
スピンナ乾燥した。
As shown in FIG. 3A, an impurity concentration of 10
A mirror-polished (100) n -type Si substrate 21 having a size of about 15 cm −3 and a non-alkali glass substrate 24 (NA-40, trade name of Hoya Glass Co., Ltd.) also having a mirror-polished surface were prepared. n
- The polished surface of the type Si substrate 21, hydrofluoric acid - width 200μm by chemical etching with nitric acid mixture, depth 100 [mu] m, a groove 22 of pitch 1 mm, further performing phosphorus diffusion 20
An n + -type layer 23 having a depth of μm was formed. Both substrates are degreased and cleaned on the polished surface as in the previous embodiment,
Spinner dried.

【0019】このように凹凸が形成されたSi基板21
とガラス基板24を、図3(b)に示すように、クラス
1の清浄な雰囲気中で研磨面同士を接触させ、空気中で
400℃まで加熱して一体化した。この後、図3(c)
に示すように、Si基板21側をラッピングして溝22
を露出させた。
The Si substrate 21 on which the irregularities are formed as described above
As shown in FIG. 3B, the polished surfaces were brought into contact with each other in a clean atmosphere of class 1 and heated to 400 ° C. in air to integrate the glass substrate 24 with the glass substrate 24. After this, FIG.
As shown in FIG.
Exposed.

【0020】そして、先の実施形態と同様のガラス25
を図4(a)に示すようにドクターブレード法により溝
22に充填し、焼成した。その後、更にSi基板21側
を削って60μm厚程度にし、ガラス25により囲まれ
たSiドットのマトリクスを得た。そして、図4(b)
に示すように、各ドットの中央部にイオン注入によりp
+ 型層26を形成し、600℃で熱処理した。
Then, the same glass 25 as in the previous embodiment is used.
Was filled in the groove 22 by a doctor blade method as shown in FIG. Thereafter, the Si substrate 21 side was further shaved to a thickness of about 60 μm, and a matrix of Si dots surrounded by the glass 25 was obtained. And FIG. 4 (b)
As shown in FIG.
The + type layer 26 was formed and heat-treated at 600 ° C.

【0021】この後、図では示さないが、CVD酸化膜
で全面を覆い、コンタクトホールを開けAl配線を施し
て、30×30のフォトダイオードが直列接続されたマ
トリクスを形成した。
Thereafter, although not shown, the entire surface was covered with a CVD oxide film, contact holes were opened, and Al wiring was formed to form a matrix in which 30 × 30 photodiodes were connected in series.

【0022】こうして形成されたフォトダイオードのマ
トリクスは、素子分離が完全で優れた特性を示した。な
お、本発明は上記した各実施形態に限られるものではな
く、その要旨を逸脱しない範囲で、種々変形して実施す
ることができる。
The thus-formed photodiode matrix has excellent element isolation and excellent characteristics. The present invention is not limited to the above-described embodiments, and can be implemented with various modifications without departing from the scope of the invention.

【0023】[0023]

【発明の効果】以上詳述したように本発明によれば、半
導体基板と絶縁性基板とを直接接着し、さらに200℃
以上の温度で加熱して接着強度を向上させ、かくして得
られた接着基板の半導体基板側に所望の素子を複数形成
し、これらの素子を横方向に誘電体分離することによ
り、極めて簡便な工程でしかも優れた素子特性を得るこ
とのできる、誘電体分離構造の半導体装置を製造するこ
とが可能となる。
As described above, according to the present invention, the semiconductor substrate and the insulating substrate are directly bonded to each other,
By heating at the above temperature to improve the adhesive strength, a plurality of desired elements are formed on the semiconductor substrate side of the thus obtained adhesive substrate, and these elements are separated from each other in a dielectric material in the lateral direction, thereby making the process extremely simple. In addition, it is possible to manufacture a semiconductor device having a dielectric isolation structure capable of obtaining excellent element characteristics.

【図面の簡単な説明】[Brief description of drawings]

【図1】第1の実施形態に係わる半導体装置の製造工程
の前半を示す断面図。
FIG. 1 is a sectional view showing a first half of a manufacturing process of a semiconductor device according to a first embodiment.

【図2】第1の実施形態に係わる半導体装置の製造工程
の後半を示す断面図。
FIG. 2 is a sectional view showing the latter half of the manufacturing process of the semiconductor device according to the first embodiment;

【図3】第2の実施形態に係わる半導体装置の製造工程
の前半を示す断面図。
FIG. 3 is a cross-sectional view showing the first half of the manufacturing process of the semiconductor device according to the second embodiment.

【図4】第2の実施形態に係わる半導体装置の製造工程
の後半を示す断面図。
FIG. 4 is a cross-sectional view showing the latter half of the manufacturing process of the semiconductor device according to the second embodiment.

【符号の説明】[Explanation of symbols]

11,13…n- 型Si基板 12…n+ 型層 14,18…酸化膜 15…p+ 型層 16…素子分離溝 17…パシベーション・ガラス11, 13 ... n - -type Si substrate 12 ... n + -type layers 14 and 18 ... oxide layer 15 ... p + -type layer 16 ... isolation trench 17 ... passivation glass

フロントページの続き (72)発明者 大浦 純一 神奈川県川崎市幸区小向東芝町1番地 株 式会社東芝総合研究所内Front Page Continuation (72) Inventor Junichi Oura 1 Komukai Toshiba-cho, Kawasaki-shi, Kanagawa Kanagawa Prefecture Corporate Research Institute

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】鏡面研磨された半導体基板と鏡面研磨され
た絶縁性基板とを実質的に異物の含まれない清浄な雰囲
気中で表面荒さ50nm以下の研磨面同士を密着させて
接合する工程と、この接合した複合体を200℃以上の
温度で加熱して接合強度を向上させる工程と、得られた
接着基板の半導体基板側に所望の素子を複数形成する工
程と、これらの素子を横方向に誘電体分離する工程とを
備えたことを特徴とする半導体装置の製造方法。
A step of bonding a mirror-polished semiconductor substrate and a mirror-polished insulative substrate to each other by bringing the polished surfaces having a surface roughness of 50 nm or less into close contact in a clean atmosphere substantially free of foreign matter; Heating the bonded composite at a temperature of 200 ° C. or higher to improve the bonding strength; forming a plurality of desired elements on the semiconductor substrate side of the obtained adhesive substrate; A method of manufacturing a semiconductor device.
【請求項2】前記絶縁性基板は、半導体基板表面に絶縁
膜を形成したものである請求項1記載の半導体装置の製
造方法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein said insulating substrate has an insulating film formed on a surface of a semiconductor substrate.
【請求項3】前記誘電体分離は、半導体基板に素子分離
溝を形成し、この素子分離溝の少なくとも側壁に非晶質
材料を形成するものである請求項1記載の半導体装置の
製造方法。
3. The method of manufacturing a semiconductor device according to claim 1, wherein the dielectric isolation is performed by forming an element isolation groove in a semiconductor substrate and forming an amorphous material on at least a sidewall of the element isolation groove.
【請求項4】前記非晶質材料は、前記素子分離溝に充填
されている請求項3記載の半導体装置の製造方法。
4. The method according to claim 3, wherein said amorphous material is filled in said element isolation trench.
【請求項5】前記誘電体分離する工程を、前記素子形成
の後に行う請求項1記載の半導体装置の製造方法。
5. The method according to claim 1, wherein the step of separating the dielectric is performed after the formation of the element.
JP7194631A 1995-07-31 1995-07-31 Method for manufacturing semiconductor device Expired - Lifetime JP2581531B2 (en)

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JP7194631A JP2581531B2 (en) 1995-07-31 1995-07-31 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7194631A JP2581531B2 (en) 1995-07-31 1995-07-31 Method for manufacturing semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP60022934A Division JPH0658934B2 (en) 1985-02-08 1985-02-08 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH08102488A true JPH08102488A (en) 1996-04-16
JP2581531B2 JP2581531B2 (en) 1997-02-12

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JP7194631A Expired - Lifetime JP2581531B2 (en) 1995-07-31 1995-07-31 Method for manufacturing semiconductor device

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Country Link
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005259775A (en) * 2004-03-09 2005-09-22 Oki Electric Ind Co Ltd Semiconductor device and method of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005259775A (en) * 2004-03-09 2005-09-22 Oki Electric Ind Co Ltd Semiconductor device and method of manufacturing the same
JP4657614B2 (en) * 2004-03-09 2011-03-23 Okiセミコンダクタ株式会社 Semiconductor device and manufacturing method of semiconductor device

Also Published As

Publication number Publication date
JP2581531B2 (en) 1997-02-12

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