JPH08101649A - Color display device - Google Patents

Abstract

PURPOSE: To perform a high speed switching among moving images by transmitting data to a color display device with a small number of signal lines and stopping the rotation of a color display element within a short time. CONSTITUTION: The color display device is constructed by further matrix- arranging display units 20 having color display elements arrayed in a matrix and each display unit 20 is provided with an address circuit 8b and a plurality of drive circuits 4c. The address circuit 8b performs writing, erasing, reading and driving commanding operations based on serial data signals (DATA) supplied from a signal source or divides display color data and supplies to each drive circuit 4c. The drive circuit 4c is composed of a drive pulse generator for generating drive pulse wave form used for rotating and stopping the motor for the color display element within a short time and a coil driving part for selecting the drive pulse wave form meeting a rotary condition and exciting and driving a coil.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multicolor information display device for displaying image information on a dot matrix, which is suitable for use in the fields of advertisement display devices, wall image display devices, etc.
The present invention relates to a device capable of displaying character information and a still image to a moving image in color by arranging a color display device for displaying a desired color by rotating and stopping a color display body divided into a plurality of colors by a motor.

[0002]

2. Description of the Related Art The applicant of the present invention previously filed Japanese Patent Application No. 4-12.
No. 8011 proposed a color display device. This is to divide the outer peripheral surface into four colors such as red, green, blue, white, etc., and arrange a plurality of coils and yokes in a cylindrical color display body with a permanent magnet fixed to the center of the head, The principle of the step motor is used to rotate the color display body to display a desired color. Such a color display element is arranged in a matrix of, for example, 16 rows × 16 columns to form one unit, and a plurality of these units are arranged to form a color display device.
Each unit has 16 rows of color display elements mounted on the ground plane,
This is a structure in which 16 sheets of circuit boards stacked on the ground plane are attached in a manner orthogonal to a single mother board provided in the unit. On the mother board, one address circuit and 16 drive circuits for driving 16 color display elements mounted on one row of circuit boards by one circuit are mounted in the same number as the number of circuit boards. The address circuit has a non-volatile memory that stores the address data of its own unit,
The non-volatile memory allows writing and erasing. The address data in the serial signal of the address data and the display color data transmitted from the signal source is matched with the address data stored in the non-volatile memory, and it is determined that the display color data is for the own unit. Then, the display color data is sorted and supplied to 16 driving circuits. The drive circuit compares the display color data of the 16 color display elements in charge with the current data and the previous data to determine whether to rotate, and configures the color display device for the rotating color display elements. When the discrimination of all the existing units is completed, the motors are driven all at once to display a desired color.

The applicant of the present invention has filed the above-mentioned Japanese Patent Application No. 4-12801.
Regarding the point that the address circuit and the drive circuit are mounted on the motherboard shown in No. 1, Japanese Patent Application No. 4-35985.
Improved by No. 4. When the address circuit and the drive circuit are mounted on the motherboard, data must be wired from the motherboard to supply data to the 16 circuit boards arranged in each column of one unit. Since the number of devices becomes enormous and manufacturing and maintenance become difficult, we improved by mounting the drive circuit on each row of circuit boards and realized a better configuration.

[0004]

The color display device shown in the above application is useful for displaying character information and video information as a color still image or moving image, but there is still room for improvement. In a color display device using a large number of color display elements, it is very difficult to manufacture and maintain if there are many transmission lines input from a signal source. The signal source of the color display device and the transmission line of the color display device, which have been applied for above, can still be arranged. Further, the above-mentioned application does not sufficiently show the configuration in which the color display element reaches a desired color in the shortest time and the short-time stop is realized.

Considering the above, the proposal by the applicant of the present invention has the following specific problems. (1) The data signal and the command transmitted from the signal source to the address circuit are performed by separate terminals, but this increases the number of terminals and the number of wiring lines.

(2) The reference clock for generating the operating clock in the address circuit is included in the data signal and transmitted from the signal source to the address circuit. It is desirable to simplify the structure in the data signal as much as possible.

(3) In order to sort and supply the data input to the address circuit to each drive circuit, the gate for the drive circuit is opened and closed, but there is another method.

(4) In the previous application, the display color data is compared with the previous data and the present data, and the rotating color display element is simply rotated by the drive signal which is the rotation command.
The structure suitable for displaying a desired color in the shortest time is not sufficiently shown.

(5) All color display elements of the color display device are simultaneously rotated by a drive signal which is a rotation command. In the previous application, a drive voltage is applied to the motor with a polarity for displaying a desired color. However, the drive pulse generating mechanism for performing high-speed switching of moving images by rotating and stopping the color display element in a short time is not sufficiently shown. An object of the present invention is to solve these problems and to provide a further improved color display device.

[0010]

In order to achieve the above object, the present invention uses the following means. (1) A data signal composed of address data and display color data and a command are transmitted to the address circuit through a common transmission line and terminal. An address data / command data discrimination bit is provided in the address data portion of the data signal, and one of them is discriminated by the address circuit. In the case of a command, a bit for discriminating which type of command is further provided, and four types of commands of writing, erasing, reading of address data of its own unit and driving for rotating the color display element are provided. ing.

(2) The data signal is shortened by removing the clock from the data signal transmitted from the signal source. The clock is supplied to the address circuit through a dedicated transmission line, and the address circuit divides the clock and uses it as an operation clock. The division ratio data corresponding to the input clock is stored in the non-volatile memory in the address circuit, and when changing the frequency of the clock from the signal source, rewrite the division ratio data of the non-volatile memory. As a result, a clock having a constant frequency is always obtained in the address circuit.

(3) As another method of sorting the serial data transmitted to the address circuit into each drive circuit, a clock distribution circuit is provided in the address circuit so that the drive circuit takes in each display color data. Are sequentially shifted and supplied to each drive circuit, and display color data is sorted and supplied to each drive circuit by a common transmission line.

(4) In the drive circuit, the previous display color data of the display color data and the present display color data are compared, and the color change of the color display element in which the data is changed, that is, the color display element requiring rotation is changed. Based on the conditions, select the rotation direction and rotation angle that operate in the shortest time.

(5) A drive pulse generator is provided in the drive circuit in order to generate a drive pulse waveform for stopping the color display body in a short time. The clock transmitted to the address circuit is divided into clocks of a specific frequency and transmitted to the drive pulse generator. When the drive command is detected by the command discrimination of the address circuit, a drive trigger signal is generated to each drive circuit. After being transmitted, the drive pulse generator generates several kinds of drive pulse waveforms from the above clock. These drive pulse waveforms are combined according to the rotation angle, the rotation direction, and the color change of the color display, and the color display element is rotated and stopped in a short time to further speed up the operation.

[0015]

Embodiments of the color display device will be described with reference to the drawings. FIG. 1 is an exploded perspective view showing the overall configuration of the color display device. This color display device includes a transparent case upper lid 2
And the display unit 4 arranged in the case upper lid 2 has
A large number of color display elements 4b are arranged in a matrix to form a dot matrix to display a color still image or a moving image of character information and video information. In this embodiment, 256 color display elements 4b are arranged in 16 rows. Units 20 arranged in 16 rows
Is composed. A base plate connection terminal block 4a, a drive circuit 4c for driving a motor by receiving a drive signal for rotation and stop of the color display element 4b, and a signal input terminal of the display unit 4 for each column of the color display element 4b. A 7-wire connection terminal 4d and the like are provided. Therefore, these elements are 1 per unit
Sixteen for six columns are used.

A base plate 6 for arranging 16 blocks of the display section 4 and an address circuit board 8 for forming character information and video information on the dot matrix are provided. The address circuit board 8 has a multipolar flat connector 8a for receiving a display signal from a signal source (not shown), and a drive signal and a color display element 4b at a predetermined position on the dot matrix for displaying a predetermined color. The address circuit 8b and the like for outputting the display color information of 16 to the 16 drive circuits 4c are provided.

A multi-pole flat connector 22a for connecting to the multi-pole flat connector 8a on the address circuit board 8 is provided, and a cord 22b connected to this has a drip-proof bush 22c attached to the case body 12. Through, it is connected to a signal source (not shown) by a multipolar flat connector 22d. The above-described configuration is applied to the case upper lid 2 and the case packing 1.
0, the case body 12 is completely sealed.

In order to fix the above device to the display place, a main body mounting bracket 14 is provided on the back surface of the device, and the device is fixed to the main body mounting bracket 14 by a base plate leg 16a, a flat seat 16b and a nut 16c. Although not shown, a plurality of screws, nuts, etc. are used to fix each member.

FIG. 2 is an exploded perspective view showing the detailed structure of the display section, showing the structure of one row of color display elements of the display section 4 of FIG. In the display unit 4, a base plate connection terminal block 4a, a base plate 30, and a drive circuit board 32 are arranged orthogonal to the surface of the base plate 6. The ground plate 30 includes 16 color display elements 4
b are arranged in one row, and the color display element group is connected to the main plate connection terminal block 4
The drive circuit board 32 is located above the surface m of a.
Is insulated and joined to the base plate 30, and is provided with a 7-wire connection terminal 4d.

The structure for rotating the color display element is composed of four yokes 34a, 34b, 34 which are magnetic round bars.
One end of each of c and 34d is press-fitted into the base plate 30, and the coils 36a and 36d are attached to the yokes 34a to 34d.
b, 36c and 36d are fitted and inserted. Also,
A stator receiving body 38 is provided, and a stator 40, which is an iron piece divided into four, is attached to the stator receiving body 38,
The other end of each of the yokes 34a to 34d is press-fitted into the hole of each iron piece of the stator 40. Further, the color display body 42 is rotatably supported, and the yokes 34a to 34d,
The coils 36a to 36d, the stator receiver 38, and the stator 40 are covered.

The color display 42 has an outer peripheral surface, for example, red,
It has a cylindrical shape divided into colors such as green, blue, and white, and is provided with a shaft member 42b at the center of the inside thereof.
A permanent magnet 44 is disposed in the recess 42a of the head portion of the No. 2 head. The axial position of the color display body 42 is determined by the attraction force of the stator 40 and the yokes 34a to 34d.

The color display element 4b includes yokes 34a to 34a.
A step motor is composed of a stator composed of d, coils 36a to 36d, and a stator 40, and a color display body 42 which is a rotor, and the color display body 42 is rotated by energizing the coil to display a desired color. . There are four coils, and the coils 36a, 36c and 36 face each other with the rotating shaft in between.
b and 36d are connected in series, and there are substantially two sets of coils. In addition, a plurality of blindfold portions 30a formed by punching and bending a part of the main board 30 in order to blind a portion of the main board 30 which is not displayed by the color display body 42,
30b, 30c, 30d, 30e are provided between the respective color display elements 4b.

FIG. 3 is an explanatory diagram of addresses of color display elements in the display unit. Vertical row (Y _j )
Are 16 rows of Y ₁ in the first row, Y ₂ in the second row, ..., Y _{16 in} the 16th row, and the column (X _i ) indicating the horizontal direction is the first row.
There are 16 columns, X ₁ of the column, X ₂ of the second column, ..., X ₁₆ of the 16th column. The address configuration is X ₁ Y _{1 in} the first row in the first column, X ₁ Y _{16 in} the 16th row in the first column, and the first column to the 16th row in the last column for each column. X ₁₆ Y ₁ to X ₁₆
An address of 1 unit is composed of 16 rows × 16 columns = 256 color display elements up to Y ₁₆ , and the data signal (DATA) is fetched in this order.

FIG. 4 is a schematic explanatory diagram of a circuit configuration in the display unit. The address circuit 8b controls 16 drive circuits 4c connected to the address circuit 8b. A clock (CLK), a data signal (DATA), and a data enable signal (DE), which are input signals, are transmitted from a signal source (not shown) to the address circuit 8b. In the data read (RDDATA), a part of the data signal (DATA) of the address circuit 8b is read and output to a signal source (not shown). Address circuit 8b
Is a shift clock (CK0 to CK15), a data string 56, a drive trigger signal (DR), a drive clock (C
P), reset signal (DRESET) to each drive circuit 4c
Is being transmitted to. 16 drive circuits 4c (# 0 to # 1
5) is in charge of 16 color display elements for each column, and as described above, each color display element has two sets of coils, so one drive circuit 4c drives 32 sets of coils. To do. To automatically reset the entire circuit, connect the capacitor 100 to the auto reset terminal (ARESET).
Is externally attached, and a reset signal (DRESET) is generated by the address circuit 8b when the power is turned on to initialize the entire system.

FIG. 5 is an explanatory diagram showing the structure of the data signal of the color display device. The data signal (DATA) is transmitted from a signal source (not shown) to a plurality of address circuits of the color display device including a plurality of units. The data signal (DATA) is composed of an address column 54 and a data column 56 for each unit. This is a configuration in which a drive command 122 for rotating the color display element follows after fetching a data string for one frame from one unit to the final unit. Data transmission to each unit is performed under the control of the data enable signal (DE), and the data enable signal (DE) is set to H while the data string for one unit is fetched.
To level. When the data enable signal (DE) is at L level, the standby state for receiving the next transmitted address sequence 54 and data sequence 56 is entered. After the data string for one frame is transmitted, the motors of all color display elements are driven all at once by the drive command 122 to display a desired color. Immediately after the display is changed, the next second frame data is transmitted.

FIG. 6 is an explanatory diagram showing the structure of a data string for one unit in the data signal of FIG. As described above, the data enable signal (DE) maintains the H level while the data string for one unit is fetched, and the data signal (DATA) is first addressed in synchronization with the rising edge of the clock (CLK). Column 54 is transmitted, followed by data column 56. 16 bits of the address string 54 are address data for designating its own unit,
Or, reading, erasing, writing of address data of its own unit, or driving to rotate the color display element,
This determination is made by the address circuit 8b of FIG. A case where the address string 54 in FIG. 6 represents address data will be described.
A data row 56 following the address row 54 is a signal in which display color data of 256 color display elements are arranged in series for each row of the color display element group, and the display color for one row is displayed as shown in FIG. Data X ₁ Y ₁ , ..., X ₁ Y ₁₆ are set to No. 1 data string, N
o. The display color data of up to ₁₆ columns of X ₁₆ Y ₁ , ..., X ₁₆ Y ₁₆ of 16 data columns are transmitted in order. No. 1 to N
o. The data strings up to 16 correspond to the 16 drive circuits 4c connected to the unit. The display color data can specify 4 colors with 2 bits, and 512 bits are required to represent 256 color display elements in one unit. Therefore, 16 bits of the address string 54 and 512 bits of the data string 56 make a total of 528 bits, which makes up a data string for one unit.

FIG. 7 is an explanatory diagram of drive commands. In FIG. 6, the case where the address string 54 is the address data has been described, but in FIGS. 7, 8, 9, and 10, the case where the address string 54 is the command data will be described. Command data must be in the upper 2 of the address sequence 54
The bit is "11". The distinction between the four types of commands is
It is performed by the lower 4 bits. Other bits may be any data. When it is a drive command 122, the lower 4
The bit is set to “1111”. Drive command 122
Is supplied in synchronism with the rising edge of the first clock (CLK) to the 16th clock (CLK) of the data enable signal (DE) at the H level, and the address described later in FIG. Lower 4 by circuit 8b
When the bit is determined to be the drive command 122, the drive trigger signal (DR) of FIG. 7 is generated. The pulse width of the drive trigger signal (DR) is the 17th clock (CL
K) to the 32nd clock (CLK) period.

FIG. 8 is an explanatory diagram of a read command. In the case of the read command 116, the lower 4 bits are set to “0111”. The read command 116 is
The data enable signal (DE) is at the H level and is supplied in synchronization with the rising edges of the first clock (CLK) to the 16th clock (CLK), and the address circuit 8b described later in FIG. When it is determined that the lower 4 bits are the read command 116, the data read (RDDATA) of FIG. 8 is taken out. The pulse width of the data read (RDDATA) is the period from the 17th clock (CLK) to the 32nd clock (CLK).

FIG. 9 is an explanatory diagram of a write command. In the case of the write command 120, the lower 4 bits are set to “0011”. The write command 120 is
The data enable signal (DE) is at the H level and is supplied in synchronization with the rising edges of the first clock (CLK) to the 16th clock (CLK), and the address circuit 8b described later in FIG. When the lower 4 bits are determined to be the write command 120 by the, the write data 121 of FIG. 9 is fetched. The pulse width of the write data 121 is 32 from the 17th clock (CLK).
This is the period of the second clock (CLK).

FIG. 10 is an explanatory diagram of the erase command.
For the erase command 118, the lower 4 bits are set to “000
The erase command 118 is supplied in synchronization with the rising of the first clock (CLK) to the 16th clock (CLK) of the data enable signal (DE) at the H level. If the lower 4 bits are determined to be the erase command 118 by the address circuit 8b, which will be described later with reference to FIG. 11, during the erase period 119 of FIG. 10, that is, from the 17th clock (CLK) to the 32nd clock (CLK). Erase in the period of.

FIG. 11 is a block diagram showing the structure of the address circuit 8b. The address circuit 8b, as described above,
One unit is provided for each unit and mounted on the address circuit board 8 in FIG. The address circuit 8b of FIG. 11 has a non-volatile memory 106 that stores address data of its own unit and frequency division ratio data described later.
The inside is composed of an address section 106a and a division ratio section 106b. The working buffer memory 108 is
An address memory unit 108a and a division ratio memory unit 108b are internally provided, and the data of the address unit 106a and the division ratio unit 106b are transmitted. Data reading from the non-volatile memory 106 is performed via the buffer memory 108.

The data control circuit 102 receives a data signal (DAT) which is an input signal from a signal source (not shown).
A), data enable signal (DE), clock (CL
K) is transmitted. In addition, the data control circuit 102
The capacitor 100 connected to the auto reset terminal (ARESET) initializes the circuit when the power is turned on, and at the same time outputs a reset signal (DRESET). The data signal (D
As shown in FIG. 6, one unit of ATA) is synchronized with the clock (CLK), and is composed of a 16-bit address sequence 54 and a 512-bit data sequence 56, and is composed of a data enable signal (DE). The starting point of the address sequence 54 is determined. The data control circuit 102 has a function of dividing the address sequence 54 and the data sequence 56 by an internal 16-bit counter, and 16 bits of the address sequence 54 are
It is transmitted to the shift register 104 and latched. The data string 56 is transmitted to the output control unit 114 described later.

The command data discrimination circuit 115 determines whether the data of the address sequence 54 latched in the shift register 104 is address data or command data.
Is determined by. As described above, the command data discriminating circuit 11 is used to discriminate the address data and the command data.
5, the data of the address sequence 54 is fetched, and it is discriminated whether it is command data or address data by the higher 2 bits of the fetched 16 bits, and FIG. 7, FIG. 9, FIG.
As shown by 0, the lower 4 bits determine which type of command is read, erase, write of the address data of its own unit, or drive for rotating the color display element.

If the command data discrimination circuit 115 discriminates the write command 120, the command data discrimination circuit 115 writes to the non-volatile memory 106. As shown in FIG. 9, the write data 121 is transmitted following the write command 120, and is composed of address data and frequency division ratio data. The write data 121 is temporarily
Writing is completed by being latched in the shift register 104 and then transmitted to the nonvolatile memory 106. In this case, when the write / erase power supply (Vpp) is applied to the nonvolatile memory 106, the shift register 10
4 data is supplied to and stored in the non-volatile memory 106, and when the application of the write / erase power supply (Vpp) is stopped, the data in the non-volatile memory 106 is transmitted to and stored in the buffer memory 108, and is read by a read command 116 described later. , Data can be read.

When the command data discrimination circuit 115 discriminates the read command 116, the data in the buffer memory 108 is read at the timing shown in FIG. That is, the contents of the non-volatile memory 106 are transmitted to the buffer memory 108, and the buffer memory 10
The data of No. 8 is output to a signal source (not shown) as data read (RDDATA).

When the command data discrimination circuit 115 discriminates the erase command 118, the nonvolatile memory 106 is erased at the timing shown in FIG. When the write / erase power supply (Vpp) is applied to the nonvolatile memory 106, “1” is stored in all bits of the nonvolatile memory 106 during the erase period 119 following the erase command 118. When the application of the read / erase power supply (Vpp) is stopped, the data in the non-volatile memory 106 is transmitted to and stored in the buffer memory 108, and the data can be read. As described above, the data can be read by the read command 116. Becomes

When the command data discrimination circuit 115 discriminates the drive command 120, the drive trigger signal (DR) for driving the motor is generated at the timing shown in FIG. The drive command 122 transmits the drive signal to the drive trigger signal generator 124 and outputs the drive trigger signal (D
R) is generated and transmitted to the drive circuit 4c shown in FIG. The drive trigger signal generator 124 generates 16 clocks of the clock (CLK) as shown in FIG.

The address match determination circuit 110 determines whether the address sequence 54 latched in the shift register 104 is address data or command data. The discrimination is performed by using the upper 2 bits of 16 bits of the address sequence 54 as a discrimination code. When it is determined to be address data, the upper 2 bits of the discrimination code are cut off and set to 1
It becomes 4-bit address data. This 14-bit address data is compared with the address data of its own unit previously written in the address memory unit 108a of the buffer memory 108 by the write command 120 in the address match determination circuit 110, and if they match, the address data shown in FIG. Since the data string 56 is for its own unit, a match signal is transmitted from the address match determination circuit 110 to the clock distribution circuit 112. The clock distribution circuit 112 supplies, to each of the 16 drive circuits 4c connected to the address circuit 8b shown in FIG. 4, display color data of the 16 color display elements that each drive circuit is responsible for. The clock (CLK) is divided to generate shift clocks (CK0 to CK15), which are distributed to each drive circuit 4c. The coincidence signal is also transmitted to the output control unit 114. The output control unit 114 receives from the data control circuit 102,
As shown in FIG. 6, the data string 56 following the address string 54
Is transmitted, the data string 56 is temporarily taken in, and the display color data of the data string 56 is converted to the above-mentioned 1 by the coincidence signal output.
It is supplied to the six drive circuits 4c.

The address circuit 8b is the drive circuit 4c shown in FIG.
A drive clock (CP) having a constant frequency, which is a reference for generating a drive pulse, is generated and transmitted to each drive circuit. Therefore, the input clock (CLK) is input to the drive clock frequency dividing circuit 128 to perform frequency division. The frequency division ratio decoder 126 is provided with frequency division output gates of several types of frequencies (four types in this embodiment), and divides the frequency division ratio data of the frequency division ratio memory unit 108b of the buffer memory 108 into the frequency division ratio decoder 126. The frequency division ratio decoder 126 controls the gate based on the frequency division ratio data to select the frequency division output of a specific frequency to obtain the drive clock (CP) of a constant frequency. By making it possible to select from a plurality of frequency division outputs having different frequency division ratio data, it is possible to use several frequencies of the input clock (CLK), and which clock (C
Even when LK is used, the drive clock (C
P) is obtained. Therefore, the clock (C
The frequency of LK) is changed by rewriting the division ratio unit 106b and the division ratio memory unit 108b.

FIG. 12 is an explanatory diagram showing a method for causing the drive circuit to latch the data string from the address circuit. The output of the clock distribution circuit 112 of the address circuit 8b of FIG. 11 is the shift clock (CK0 to CK15) of FIG.
, Each consists of 32 clocks, and each is shifted by 32 clocks, and each drive circuit 4 of FIG.
transmit to c. On the other hand, the data sequence 56 is transmitted from the output control unit 114 of the address circuit 8b in FIG. 11 and is output in synchronization with the shift clock (CK0 to CK15). Therefore, the data string 56 shown in FIG. 12 is sorted from # 0 to # 15 of the drive circuit 4c of FIG. 4 and 32 bits of display color data can be supplied.

FIG. 13 is a block diagram showing the structure of the drive circuit. Although not shown, the drive circuit 4c is mounted on the drive circuit board 32 in FIG. The drive circuit 4c shown in FIG. 13 is roughly composed of a shift register 200, coil drive units 1 to 16, and a drive pulse generator 216. As shown in FIG. 12, each drive circuit 4c loads the shift register 200 with 32 bits of display color data of 16 color display elements in synchronization with the shift clock (CK0 to CK15).

The drive circuit 4c includes coil drive units 1 to 16 for driving the motors of the 16 color display elements, respectively.
It has. Hereinafter, one of the coil drive units 1 will be taken up and described. As shown in FIG. 2, the coil driving unit 1 refers to the coil driving unit of the first color display element among the color display elements arranged in a line, and one color display element is one of the four coils 36a to 36d. Driven by. Two opposing coils (36a and 36c, 36b and 36d) are connected in series, connected on is constituted by two sets of coils, these are the coil 1 ₀ and the coil 2 _0. Of the 32 bits of display color data of the 16 color display elements fetched in the shift register 200, the display color data of the first color display element is 2 bits A ₀ and B ₀ . When a drive trigger signal (DR) generated by the address circuit 8b of FIG. 11 receiving a drive command from a signal source (not shown) is transmitted to the drive circuit 4c of FIG. 13, the display color captured in the shift register 200 is displayed. Data A ₀ is A ₀ new data latch 20
2, B ₀ is latched by B ₀ new data latch 205. Also, before the drive trigger signal (DR) is transmitted, the A ₀ new data latch 202 and the B ₀ new data latch 205 are transmitted.
The display color data latched in is the previous data, and A ₀ moves to the A ₀ old data latch 203 and B ₀ moves to the B ₀ old data latch 206. The old and new data A ₀ and B ₀ are transmitted to the rotation condition determination circuit 208.

In the rotation condition discrimination circuit 208, A ₀ and B ₀
A ₀ new data latch 202 and A _{0 for each of}
The rotation angle, rotation direction, and color change of the motor are determined from the results of the data comparison of the old data latch 203 and the data comparison of the B ₀ new data latch 205 and the B ₀ old data latch 206 and transmitted to the drive control circuit 210. . If the new data and the old data are the same for both A ₀ and B ₀ data, it is judged as non-rotation and is not transmitted to the drive control circuit 210. That is, when the new data and the old data match for both A ₀ and B ₀ data, there is no change in the display color and there is no need to drive the motor.

Various drive pulse waveforms generated by the drive pulse generator 216 described later are also included in the drive control circuit 210.
Be transmitted to. The drive control circuit 210 assembles drive pulses based on the rotation angle, rotation direction, and color change input from the rotation condition determination circuit 208. The assembled drive pulse is transmitted to the coil 1 ₀ drive output circuit 214 and the coil 2 ₀ drive output circuit 215 via the penetration prevention circuit 212, and is applied to each terminal of the coil 1 ₀ and the coil 2 ₀ , and the motor is driven. Rotate to desired position. Coil 1 ₀ drive output circuit 214, the coil 2 ₀ drive output circuit 215, since the power supply to the coil by turning on and off of the transistor,
A through current may flow through the transistor during switching, and a through prevention circuit 212 is provided to prevent this. Hereinafter, similar processing is performed for all of the remaining 15 sets of coil driving units 2 to 16.

Drive pulse generator 2 of drive circuit 4c
16 will be described. Drive pulse generator 216
When the drive trigger signal (DR) is transmitted to, the drive clock (CP) having a constant frequency transmitted from the address circuit 8b of FIG. 11 is further converted to a specific clock by the frequency dividing circuit 218 to generate a drive pulse. Divide. The frequency dividing circuit 2
In 18, the drive clock (CP) having a constant frequency is divided into a specific clock, so that the division ratio is constant. The specific clock divided by the divider circuit 218 is supplied to the counter 22.
The counting is started at 0, the count value is selected by the decoder 222, the time for determining the pulse width and the phase of several kinds of pulse waveforms is assembled, and the drive pulse waveform generator 224 makes the decoder 2
It receives the output of 22 and generates timing pulses of various waveforms. The drive pulse waveform is synthesized using these timing pulses. The combined drive pulse waveform is transmitted to the drive control circuit 210 of the coil drive units 1 to 16 described above. The pulse reset circuit 226 resets the counter 220 after the drive pulse waveform generator 224 completes one operation, and the drive pulse generator 216 prepares for the next operation. Further, the reset signal (DRESET) from the address circuit 8b of FIG.
26, the drive pulse waveform generator 224 and the data of both A ₀ and B ₀ are transmitted to the new data latches 202 and 205 and the old data latches 203 and 206, and the entire initialization is performed.

FIG. 14 shows a drive pulse waveform generated by the drive pulse generator. In the color display device of the present invention, when the display color is switched, the motor may be rotated by 90 ° or may be rotated by 180 ° depending on the relationship of the colors before and after the switching. In the present embodiment, four drive pulse waveforms, that is, waveforms 250 and 252 for 90 ° rotation and waveforms 254 and 256 for 180 ° rotation, are illustrated.

FIG. 15 shows a drive pulse applied to the coil. As described above, the drive control circuit 210 of FIG.
Rotation angle, rotation direction, the driving pulse assembled from the drive pulse waveform in accordance with the color change, are transmitted to the coil 1 ₀ drive output circuit 214 and the coil 2 ₀ drive output circuit 215. As a result, the coil 1 ₀ and the coil 2 ₀ driving pulses as shown in FIG. 15 is applied. FIG. 15 shows the height relationship with the voltage at the other end, focusing on one end of the coil. There are 90 ° drive pulse 270 and 180 ° drive pulse 280 for each rotation angle, and two drive pulses (a ), (B) are one set. Taking the 90 ° driving pulses 270 as an example, the terminals of the two sets of coils, for example, A ₁ of the coil 1 _0, when the pulsing of A ₃ to the terminal 270 (a), A ₂ of the coil 2 _0, A 270 for ₄ terminals
The pulse of (b) is applied, and when either one of the pulses is applied to one coil, the other pulse is always applied to the other coil. Also,
Depending on the color change and the rotation direction, the drive pulse may have the same waveform configuration, but the H level and the L level may be opposite to those in FIG.

[0048]

According to the structure of the present invention, the drive clock (CP), the shift clock (CK0 to CK15), the drive trigger signal (DR), which are generated in the address circuit,
The number of input / output terminals and the number of connection lines are reduced by the configuration of command data, frequency division ratio data, etc., and at the same time the clock frequency can be selected. Further, the configuration of the drive pulse generator generated in the drive circuit, the rotation condition determination circuit, the drive control circuit, and the like makes it possible to set the optimum drive pulse for the motor, thereby enabling low power consumption and high speed operation. With the above two configurations, the number of connection lines between the signal source and the color display device is greatly reduced, and there is a great effect in terms of improvement of reliability, ease of manufacture, and cost reduction.

[Brief description of drawings]

FIG. 1 is an exploded perspective view showing an overall configuration of a color display device.

FIG. 2 is an exploded perspective view showing a detailed configuration of a display unit.

FIG. 3 is an explanatory diagram of addresses of color display elements in the display unit.

FIG. 4 is a schematic explanatory diagram of a circuit configuration in the display unit of the present invention.

FIG. 5 is an explanatory diagram showing a configuration of a data signal of the color display device of the present invention.

6 is an explanatory diagram showing a configuration of a data string for one unit in the data signal of FIG.

FIG. 7 is an explanatory diagram of drive commands of the present invention.

FIG. 8 is an explanatory diagram of a read command according to the present invention.

FIG. 9 is an explanatory diagram of a write command according to the present invention.

FIG. 10 is an explanatory diagram of an erase command of the present invention.

FIG. 11 is a block diagram showing a configuration of an address circuit of the present invention.

FIG. 12 is an explanatory diagram showing a method of causing a drive circuit to latch a data string from an address circuit of the present invention.

FIG. 13 is a block diagram showing a configuration of a drive circuit of the present invention.

FIG. 14 is a drive pulse waveform generated by the drive pulse generator of the present invention.

FIG. 15 is a drive pulse applied to the coil of the present invention.

[Explanation of symbols]

4c Drive circuit 8b Address circuit 20 Unit 42 Color display 44 Permanent magnet 54 Address sequence 56 Data sequence 104 Shift register 106 Non-volatile memory 108 Buffer memory 110 Address match determination circuit 112 Clock distribution circuit 115 Command data determination circuit 128 Drive clock frequency dividing circuit Circuit 200 Shift register 202 A ₀ New data latch 203 A ₀ Old data latch 208 Rotation condition determination circuit 210 Drive control circuit 214 Coil 1 ₀ drive output circuit 216 Drive pulse generator

Claims (9)

[Claims] 1. A motor is constructed by arranging a stator, a yoke and a coil on a permanent magnet fixed to a multicolored tubular color display member and rotatably supporting the magnet, and controlling energization to the coil. The color display device is formed by arranging a plurality of units in which color display elements are arranged in a matrix by rotating the color display body in a desired direction to display a color, and each unit forms one address circuit and a plurality of units. In a color display device including a drive circuit, an address circuit receives a input signal and transmits it to each unit, a shift register that latches an address string in an input data signal, and its own address data. A non-volatile memory that has been written, an address match determination circuit that compares the address sequence latched in the shift register with its own address data in the non-volatile memory, A clock distribution circuit that receives a match signal from the dress match determination circuit and distributes a shift clock to each drive circuit, and an output control unit that supplies a data string in an input data signal to each drive circuit are provided. Characteristic color display device. 2. The color display device according to claim 1, wherein the address circuit includes a working buffer memory that stores the same address data as the address data written in the nonvolatile memory. And color display device. 3. A motor is constructed by fixing a permanent magnet to a multi-colored tubular color display member and rotatably supporting it, and arranging a stator, a yoke and a coil to control energization of the coil. The color display device is formed by arranging a plurality of units in which color display elements are arranged in a matrix by rotating the color display body in a desired direction to display a color, and each unit forms one address circuit and a plurality of units. In a color display device including a driving circuit, the address circuit uses a driving clock frequency dividing circuit that divides an input clock to generate a driving clock with a constant frequency, and a number of input clock frequencies. A nonvolatile memory in which frequency division ratio data for dividing the frequency of one selected clock is written, and the drive according to the frequency division ratio data written in the nonvolatile memory. The color display device, characterized in that it comprises a frequency dividing ratio decoder to specify the frequency division ratio data of the lock divider. 4. The color display device according to claim 3, wherein the address circuit includes a working buffer memory that stores the same division ratio data as the division ratio data written in the nonvolatile memory. A color display device comprising. 5. A motor is constructed by arranging a stator, a yoke, and a coil on a cylindrical color display body, which is painted in different colors, and rotatably supporting the permanent magnet, and arranging a stator, a yoke, and a coil to control energization of the coil. The color display device is formed by arranging a plurality of units in which color display elements are arranged in a matrix by rotating the color display body in a desired direction to display a color, and each unit forms one address circuit and a plurality of units. In the color display device including the drive circuit, the address circuit determines whether the data in the shift register is address data or command data,
And a command data discriminating circuit that discriminates what kind of command is discriminated as command data, and a drive trigger that causes the drive circuit to start a display color switching operation when a drive command is detected by the command data discriminating circuit. A color display device comprising a drive trigger signal generator for generating a signal. 6. The color display device according to claim 5, wherein, in addition to the drive command, the command data determination circuit erases and writes unit address data in a nonvolatile memory and reads unit address data in a buffer memory. A color display device characterized by discriminating each command of. 7. A motor is constructed by arranging a stator, a yoke and a coil on a cylindrical color display body, which is colored in different colors, and rotatably supporting the permanent magnet, and arranging a stator, a yoke and a coil to control the energization of the coil. The color display device is formed by arranging a plurality of units in which color display elements are arranged in a matrix by rotating the color display body in a desired direction to display a color, and each unit forms one address circuit and a plurality of units. In a color display device equipped with a drive circuit, the drive circuit includes a shift register that takes in the display color data supplied from the address circuit, a drive pulse generator that generates several types of drive pulse waveforms, and drive generated by the drive pulse generator. A color display device comprising a coil driving section for controlling driving of a coil by a pulse waveform. 8. The color display device according to claim 7, wherein the coil drive unit in the drive circuit includes a new data latch that latches the display color data of this time based on the display color data of the shift register, and a previous display. An old data latch that holds color data, a rotation condition determination circuit that determines the rotation angle, rotation direction, and color change from the display color data of both latches, including the case of non-rotation, and the drive generated by the drive pulse generator. A color display device comprising: a drive control circuit that assembles a drive pulse from a pulse waveform based on the determination result of the rotation condition determination circuit; and a coil drive output circuit that receives the assembled drive pulse waveform and excites a coil. 9. The color display device according to claim 7, wherein the drive pulse generator comprises a frequency divider circuit for dividing the drive clock, a counter for counting the output of the frequency divider circuit, and a specific counter for the counter. A decoder for selecting a numerical value, a drive pulse waveform generator that receives the output of the decoder to generate several types of drive pulse waveforms, and a pulse reset circuit that transmits a reset signal when one operation is completed. Color display device.