JP5795089B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine that generates a big hit state by a lottery process resulting from detection of a switch signal, and more particularly to a gaming machine that can store and retain gaming results over a long period of time.

  A ball and ball game machine such as a pachinko machine has a symbol start port provided on the game board, an image display unit for displaying a series of symbol variation modes by a plurality of display symbols, and a grand prize opening for opening and closing the opening and closing plate. Configured. When the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the display symbol is changed for a predetermined time in the image display unit. Thereafter, when the symbol is stopped in a predetermined manner such as 7, 7, 7, etc., a big hit state is established, and the big winning opening is repeatedly opened to generate a gaming state advantageous to the player.

  Whether or not to generate such a gaming state is determined by a jackpot lottery executed on condition that a game ball has won a symbol start opening, and the image effect executed by the image display unit is determined by this lottery. Based on the results. For example, when the lottery result is in a winning state, an image effect called reach action or the like is executed for about 20 seconds, and then special symbols are aligned. On the other hand, a similar reach action may be executed even in a lost state. In this case, the player pays close attention to the big hit state and pays close attention to the transition of the image effect. When the predetermined design is aligned with the stop line at the end of the image effect, the player is guaranteed to be in the big hit state.

  Note that, regardless of whether or not the big hit state is reached, at the time of the image production in the image display unit, a lamp production and a sound production synchronized with the image production are executed in order to excite the player.

JP 2013-143999 A JP 2012-085733 A JP 2009-018021 A JP 2006-280442 A JP 2006-087500 A JP 2005-279086 A

  By the way, this type of gaming machine is generally composed of a main control unit that is centrally responsible for game control operations and a sub-control unit that operates based on control commands received from the main control unit. The sub-control unit includes a payout control unit in charge of a payout operation for the player and an effect control unit in charge of various effect operations including an image effect, a lamp effect, and a sound effect.

  Here, since the backup power supply is arranged in the main control unit and the payout control unit, even if a power failure occurs during the game operation, the game state at that time is stored and held. Therefore, the big hit state before the power failure does not disappear due to the power failure, and the prize ball to be paid out does not disappear, and the player's profit is surely secured.

  However, in the first place, a power outage condition occurs very rarely, and the saving of the performance operation is almost worthless for the player compared to the need to save the big hit state etc. It is reasonable not to place a power supply.

  However, if past gaming achievements of the gaming machine, such as the occurrence frequency of big hits and the transition of the number of prize balls, can be accumulated over a long period of time, customer services can be improved by informing this to the player. Can do.

  Here, it is known that a writable nonvolatile memory is arranged in a gaming machine (Patent Documents 1 to 6), but any invention uses only a flash memory. Therefore, the fate of the flash memory has a problem that random access cannot be performed in the same procedure as that of a normal RAM due to the data erasing operation in units of sectors and the special characteristics of the data writing operation. In addition, it is necessary to provide a dedicated access circuit having a power supply voltage different from that of a normal RAM, which causes a fatal problem that the device configuration becomes complicated and the manufacturing cost increases.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a gaming machine that can store and retain game results over a long period of time without complicating the device configuration.

In order to achieve the above object, the present invention provides a gaming machine provided with an effect control means for executing an effect operation based on a control command received from another control means, wherein the effect control means includes a predetermined control. The first means that is activated by receiving the command and obtains game information related to the gaming performance of the gaming machine on an acquisition path different from the transmission path of the control command , and the game information acquired by the first means is timed. And a second means for storing the information in a non-volatile manner in the game result memory as history information with the clock information from the means, and the history information is configured to be notified to the player when necessary. ing.

The nonvolatile memory is configured to operate in response to an address bus signal, a chip select signal, and a read permission signal,
When the chip select signal is at the active level, it is preferable that the data read operation from the memory address specified by the address bus signal is started in response to the change of the read permission signal. The data bus signal, the address bus signal, the chip select signal, and the write enable signal are configured to operate. When the chip select signal is at an active level, in response to the change of the write enable signal, It is preferable that the write operation of the data bus signal is started at the memory address specified by the address bus signal. When such a configuration is adopted, not only the circuit configuration is simplified, but also the CPU can perform memory access in the same procedure as a normal ROM or RAM (especially SRAM).

  According to the gaming machine of the present invention described above, it is possible to realize a gaming machine that can store and retain gaming results over a long period of time without complicating the device configuration.

It is a perspective view of the pachinko machine shown in an example. It is the front view which illustrated the game board of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of FIG. It is a circuit diagram which shows the ferroelectric memory circuit of the payout control part. It is a circuit block diagram which shows the internal structure of the ferroelectric memory of a payout control part. It is drawing explaining the circuit configuration (a) and circuit operation | movement (b) of the serial port of a payout control part. 6 is a time chart for explaining an access operation of a ferroelectric memory. It is drawing explaining the circuit structure (a) of an effect control part, and an RTC circuit. 3 is a circuit block diagram showing an internal configuration of a ferroelectric memory of an effect control unit. FIG. It is drawing explaining the circuit structure (a) and circuit operation | movement (b) of the serial port of an effect control part. It is a flowchart explaining operation | movement of the payout control part after a power supply reset. It is a flowchart explaining the timer interruption process of a payout control part. It is a flowchart explaining operation | movement of an effect control part. It is drawing which shows the memory content of the ferroelectric memory of a payout control part and an effect control part.

  Hereinafter, the present invention will be described in detail based on examples. FIG. 1 is a perspective view showing a pachinko machine GM of the present embodiment. This pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably mounted on an island structure, and a front frame 3 that is pivotably mounted via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 from the front side, not from the back side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be openable and closable.

  On the outer periphery of the glass door 6, an electric lamp such as an LED lamp is arranged in a substantially C shape. On the other hand, at the upper left and right positions and the lower side of the glass door 6, all three speakers are arranged. The two speakers arranged in the upper part are each configured to output sound of the left and right channels R and L, and the lower speaker is configured to output heavy bass.

  The front plate 7 is provided with an upper plate 8 for storing game balls for launching, and a lower plate 9 for storing game balls overflowing or extracted from the upper plate 8 and a launch handle at the lower part of the front frame 3. 10 are provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated with the left hand of the player, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is turned on and can be operated. The button chance state is a game state provided as necessary.

  On the right side of the upper plate 8, an operation panel 12 for ball lending operation with respect to the card-type ball lending machine is provided, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a ball of game balls for a predetermined amount A ball lending switch for instructing lending and a return switch for instructing to return the card at the end of the game are provided.

  As shown in FIG. 2, a guide rail 13 made of a metal outer rail and an inner rail is provided on the surface of the game board 5 in an annular shape, and a central opening HO is provided at the approximate center thereof. A display device DS composed of a large liquid crystal color display (LCD) is disposed in the central opening HO.

  The display device DS is a device that variably displays a specific symbol related to the big hit state and displays a background image and various characters in an animated manner. This display device DS has special symbol display portions Da to Dc in the center portion and a normal symbol display portion 19 in the upper right portion. In the special symbol display portions Da to Dc, there is a case where a reach effect that expects a big hit state is invited, and in the special symbol display portions Da to Dc and the surroundings, an appropriate notice effect is executed.

  In the game area where the game ball falls and moves, a symbol start port 15, a big winning port 16, a normal winning port 17, and a gate 18 are arranged. Each of these winning openings 15 to 18 has a detection switch inside, and can detect the passage of a game ball.

  The symbol start port 15 is configured to be opened and closed by an electric tulip having a pair of left and right open / close claws 15a, and when the stop symbol after the fluctuation of the normal symbol display unit 19 displays a winning symbol, a predetermined time is displayed. The opening / closing claw 15a is opened only until a predetermined number of game balls are detected.

  The normal symbol display unit 19 displays a normal symbol. When a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates for a predetermined time and is extracted when the game ball passes through the gate 18. The stop symbol determined by the selected lottery random value is displayed and stopped.

  The special winning opening 16 includes an opening / closing plate 16a that advances and retreats in the front-rear direction. The operation of the special winning opening 16 is not particularly limited, but in a typical big hit state, a predetermined time elapses after the opening / closing plate 16a of the special winning opening 16 is opened, or a predetermined number (for example, ten) of games. When the ball wins, the opening / closing plate 16a is closed. Such an operation is continued up to 15 times, for example, and is controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol among the special symbols, there is a privilege that the game after the end of the special game becomes a high probability state (probability variation state). Is granted.

  FIG. 3 is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes the above-described operations. As shown in the figure, this pachinko machine GM mainly receives a 24V AC and outputs various DC voltages, power supply abnormality signals ABN1, ABN2, a system reset signal (power reset signal) SYS, and the like, and a game control operation. Based on the main control board 21 that performs overall control, the effect control board 22 that executes the lamp effect and the sound effect based on the control command CMD received from the main control board 21, and the control command CMD ′ received from the effect control board 22 The image control board 23 for driving the display device DS, the payout control board 24 for controlling the payout motor M based on the control command CMD "received from the main control board 21, and paying out the game balls. It is mainly composed of a launch control board 25 that responds and launches a game ball.

  However, in this embodiment, the control command CMD output from the main control board 21 is transmitted to the effect control board 22 via the command relay board 26 and the effect interface board 27. The control command CMD ′ output from the effect control board 22 is transmitted to the image control board 23 via the effect interface board 27 and the image interface board 28, and is output from the main control board 21. Is transmitted to the payout control board 24 via the main board relay board 32. Although the control commands CMD, CMD ′, and CMD ″ are all 16 bits long, the main control board 21 and the payout control board 24 are used. The control commands related to are transmitted in parallel every two 8 bit lengths. On the other hand, the control command CMD 'transmitted from the effect control board 22 to the image control board 23 is 16 bits in length and transmitted in parallel. Therefore, even when the notification effects including the movable notification effect are diversified and a large number of control commands are continuously transmitted and received, the processing can be completed quickly, and other control operations are not hindered.

  By the way, in the present embodiment, the production interface board 27 and the production control board 22 are directly connected to each other by a male connector and a female connector without passing through a wiring cable, and two circuit boards are laminated. . Similarly, with respect to the image interface board 28 and the image control board 23, two circuit boards are laminated by directly connecting a male connector and a female connector without going through a wiring cable. Therefore, even if the circuit configuration of each electronic circuit is complicated and sophisticated, the storage space of the entire board can be minimized, and noise resistance can be improved by minimizing the connection lines.

  The main control board 21, the effect control board 22, the image control board 23, and the payout control board 24 are each equipped with a computer circuit including a one-chip microcomputer. Therefore, in this specification, the control board 21 to 24, the circuits mounted on the interface boards 27 to 28, and the operations realized by the circuits are generically named. May be referred to as a section 22 ′, an image control section 23 ′, and a payout control section 24. That is, in this embodiment, the effect control board 22 and the effect interface board 27 constitute an effect control part 22 ′, and the image control board 23 and the image interface board 28 constitute an image control part 23 ′. . Note that all or part of the effect control unit 22 ′, the image control unit 23 ′, and the payout control unit 24 are sub-control units.

  The pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 3 and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes a front frame 3 on which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof. Is fixedly installed. On the other hand, the board side member GM2 is replaced in response to the model change, and a new board side member GM2 is attached to the frame side member GM1 instead of the original board side member. All except the frame side member 1 is the panel side member GM2.

  As shown in the broken line frame in FIG. 3, the frame side member GM1 includes a power supply board 20, a payout control board 24, a launch control board 25, a frame relay board 35, and a lamp drive board 36. These circuit boards are respectively fixed at appropriate positions of the front frame 3.

  As illustrated, the power supply board 20 is connected to the main board relay board 32 through the connection connector C2, and is connected to the power supply relay board 33 through the connection connector C3. The power supply board 20 is provided with a power supply monitoring unit MNT that monitors whether AC power is turned on or off. When power supply monitoring unit MNT detects that AC power is turned on, it maintains system reset signal SYS at L level for a predetermined time, and then transitions it to H level.

  Further, when power supply monitoring unit MNT detects the interruption of the AC power supply, power supply abnormality signals ABN1 and ABN2 are immediately shifted to the L level. The power supply abnormality signals ABN1 and ABN2 quickly become H level after the power is turned on.

  Incidentally, the system reset signal of this embodiment is generated by a DC power supply based on an AC power supply. For this reason, after detecting the turning-on of the AC power supply (usually turning on the power switch) and increasing it to the H level, the H level is maintained unless the DC power supply voltage drops to an abnormal level. Therefore, even if the AC power supply is in an instantaneous power interruption state while the DC power supply voltage is maintained, the system reset signal SYS does not reset the CPU. The power supply abnormality signals ABN1 and ABN2 are also output even when the AC power supply is instantaneously stopped.

  The system reset signal SYS output from the power supply board 20 is a power supply reset signal indicating that the AC power supply 24V has been applied to the power supply board 20, and one of the effect control unit 22 ′ and the image control unit 23 ′ is generated by the power supply reset signal. The chip microcomputer is reset together with other IC elements.

  However, the system reset signal SYS is not supplied to the main control unit 21 and the payout control unit 24, and a power reset signal (CPU reset signal) is generated in the reset circuit RST of each of the circuit boards 21 and 24. ing. Therefore, for example, even if the connection connector C2 is rattled or noise is superimposed on the wiring cable, there is no possibility that the CPU of the main control unit 21 or the payout control unit 24 is abnormally reset. The production control unit 22 ′ and the image control unit 23 ′ execute production operations dependently on the basis of a control command from the main control unit 21, and therefore, in order to avoid complication of the circuit configuration, A system reset signal SYS output from the substrate 20 is used.

  As shown in FIG. 3, the payout control board 24 is directly connected to the power supply board 20 without going through the relay board. When the main control unit 21 receives the power supply abnormality signal ABN2 and the backup power supply BAK, etc. Directly with the power supply voltage. The reset circuits RST provided in the main control unit 21 and the payout control unit 24 each have a built-in watchdog timer, and unless a regular clear pulse is received from the CPUs of the control units 21 and 24, Each CPU is forcibly reset.

  Incidentally, a ferroelectric memory circuit 37 is disposed in the payout control unit 24 of the present embodiment. Here, the ferroelectric memory (Ferroelectric Random Access Memory) is a non-volatile memory using the polarization of the ferroelectric, and in this embodiment, it operates with a single power source, can be accessed randomly, and is read / read. A memory element capable of writing is used. Therefore, the circuit configuration and program processing are not complicated as in the case where a flash memory is mounted.

  In this embodiment, since the ferroelectric memory FeRAM is configured to store the prize ball results for one day, an element having a storage capacity of 16 Kbytes (= 16,384 bytes) is used. Elements that operate using the (Serial Peripheral Interface) method are adopted. Therefore, in the payout control unit of this kind of gaming machine in which the memory capacity is legally restricted, the storage capacity of the SRAM or ROM of the payout control unit 24 is not eroded by the ferroelectric memory FeRAM, and the original payout Does not interfere with control operations.

  The ferroelectric memory FeRAM is configured to be accessible from the one-chip microcomputer of the payout control unit 24 and to be accessible from the one-chip microcomputer of the effect control unit 22. That is, as shown in FIG. 3, the one-chip microcomputer of the effect control unit 22 passes through the effect interface board 27, the frame relay board 34, and the frame relay board 35 to the ferroelectric memory circuit 37. It is connected so that it can communicate bidirectionally.

  Therefore, the data such as the result of the winning ball stored in the ferroelectric memory FeRAM can be grasped by the effect control unit 22 at a necessary timing, and the effect control unit 22 performs appropriate aggregation processing and statistical processing. be able to. Further, in the present embodiment, the work added to the payout control unit 24 is only to store the prize ball data relating to payout in the ferroelectric memory FeRAM, so that the processing can be completed in a short time. And has virtually no effect on the original payout control. However, it is not particularly limited to the write operation, and a read operation for the ferroelectric memory FeRAM may be added.

  On the other hand, in the present embodiment, the operation of the effect control unit 22 is restricted to read access to the ferroelectric memory FeRAM, and the write access to the ferroelectric memory FeRAM is prohibited, thereby causing a security problem. It is preventing.

FIG. 4A is a circuit diagram showing a connection relationship between the ferroelectric memory circuit 37 and the one-chip microcomputer of the payout control unit 24 and the one-chip microcomputer of the effect control unit 22. As for the one-chip microcomputer of the payout control unit 24, only the parallel output port PARAa _OUT , the parallel input port PARAa _IN, and the serial port SERIa are described, and the parallel output port PARAb of the effect control unit 22 is also described. Only _OUT , parallel input port PARAb _IN , and serial port SERIb are shown. Although not particularly limited, in this embodiment, the serial port SERIa of the payout control unit 24 executes only the serial output operation (memory Write), and the serial port SERIb of the effect control unit 22 performs the serial output operation (OUT). The serial input operation (IN) is executed as described above.

  The ferroelectric memory circuit 37 includes a ferroelectric memory FeRAM that operates in the SPI system, a selection circuit SEL that selects a total of 6-bit serial signals and outputs a 3-bit serial signal, and a selection circuit SEL. And an access control circuit DET for generating a control signal SELECT defining the selection operation. As shown, the ferroelectric memory circuit 37 receives 3-bit signals (CS bar, So, CK) from the effect control unit 22 and the payout control unit 24, respectively.

  FIG. 5 is a block diagram showing an internal configuration of the ferroelectric memory FeRAM operating in the SPI system. This ferroelectric memory FeRAM becomes active when the chip select terminal CS bar is at the L level, receives serial data from the serial input terminal Si, and receives the transmission clock SCK from the clock terminal CK, in synchronization with the transmission clock SCK. The serial data is acquired bit by bit.

  The serial data acquired by the ferroelectric memory FeRAM includes an 8-bit operation instruction command and 16-bit address data. The operation instruction command includes a SWE (Set Write) that permits a memory write operation. (Enable) command (06H), RWE (Reset Write Enable) command (04H) for prohibiting memory write operation, WRITE command (02H) for instructing memory write operation, and READ command (= 03H for instructing memory read operation) ) And are included.

  In the memory write operation, the SWE command is preceded, the WRITE command (8 bits) and address data (16 bits) are supplied, the write destination address is specified, and then the write data is supplied. Become.

  FIG. 7A is a time chart showing the operation at the time of writing the SWE command (= 06H). As shown in the drawing, an 8-bit SWE command is transmitted from the MSB (Most Significant Bit) to the LSB (Least Significant Bit) while the chip select signal CS bar is at the active level (L). Each bit data is acquired in the ferroelectric memory FeRAM (internal register of the control circuit in FIG. 5) in synchronization with the rising of the transmission clock SCK. As a result, the memory write is performed on the ferroelectric memory FeRAM. Operation is possible.

  FIG. 7D is a time chart for explaining the memory write operation executed after the operation of FIG. As shown in the figure, while the chip select signal CS bar is at the active level (L), the WRITE command (= 02H) and the address data are supplied from the MSB to the LSB in synchronization with the transmission clock SCK. Since the storage capacity of the FeRAM in the embodiment is 16 Kbytes (= 16,384), the upper 2 bits of the address data are dummy data (×).

  In the description of FIG. 7D, the write data ends with 8 bits. However, if serial transmission of the write data is continued thereafter, the first designated address is sequentially updated (automatic increment), and a series of The write operation to the memory area is continued. When the chip select signal CS bar is returned to the inactive level (H), thereafter, the memory write operation is automatically prohibited. Therefore, according to the present embodiment, malfunctions in which the contents of the memory are rewritten without influence due to noise or the like are avoided.

  FIG. 7C is a time chart for explaining the memory read operation. When the chip select signal CS bar is at the active level (L), the READ command (= 03H) and the address data are transmitted from the MSB to the LSB, respectively. A state in which the signal is supplied in synchronization with the transmission clock SCK is shown. Here, the Read operation ends with 8 bits. However, if the supply of the transmission clock SCK is continued thereafter, the first designated address is sequentially updated, and the read operation from the series of memory areas is continued. When the necessary read operation is completed, the chip select signal CS bar is returned to the inactive level (H).

  On the other hand, FIG. 7B is a time chart showing the operation at the time of writing the RWE command (= 04H). In the ferroelectric memory FeRAM, since the memory write operation is disabled after acquiring the RWE command, a write operation of the RWE command is executed when necessary to prevent a malfunction in which the contents of the memory are erroneously rewritten. can do. However, in this embodiment, the memory write operation is automatically disabled when the chip select signal CS bar returns to the inactive level after power reset or after the WRITE command (= 02H) is executed. Therefore, execution of the RWE command (= 04H) is not always essential. Of course, the memory read operation is not prohibited even in the memory write prohibited state.

  As described above, the ferroelectric memory FeRAM has been described in detail. Returning to FIG. 4A, the description of the circuit configuration of the ferroelectric memory circuit 37 will be continued. The selection circuit SEL is configured using a general-purpose IC such as SN74157 (Quad 2-line to 1-line data selectors). When the control signal SELECT = H level, the 3-bit A group signal from the payout control unit 24 is selected, and when the control signal SELECT = L level, the 3-bit length from the effect control unit 22 is selected. The B group signal is selected and output as a Y signal. The strobe terminal G is at the ground level, and the selection circuit SEL is always operable.

  The 3-bit signal selected by the selection circuit SEL is a chip select signal CS bar for activating the ferroelectric memory FeRAM, a transmission clock SCK defining serial transmission timing, and a serial input signal SI. Here, the serial input signal SI is serial data obtained by connecting an operation instruction command that defines the operation of the ferroelectric memory FeRAM, address data that defines a memory access address, and write data. When a memory READ command (= 03H) is received from the serial output terminal SO of the ferroelectric memory FeRAM, read data from the address defined by the address data is serially output in synchronization with the transmission clock SCK. Is done.

As shown in the figure, the Listen signal requesting access permission of the ferroelectric memory FeRAM from the parallel output ports PARAa _OUT and PARAb _{OUT of} the payout control unit 24 and the effect control unit 22 to the access control circuit DET, and the access control circuit DET And a CLR signal for returning the signal to the initial state.

  As shown in FIG. 4B, the Listen signal and the CLR signal are positive logic pulses having a predetermined pulse width. In FIG. 4A, in order to simplify the circuit configuration, the CLR pulse is generated by the CPU of the payout control unit 24 and the effect control unit 22, but actually, the one-shot multivibrator (1- By adopting a configuration in which CLR pulses are automatically generated by shot multi) or the like, the software burden is reduced (see the broken line portion in FIG. 4A).

In any case, chip select signals CSa and CSb of the ferroelectric memory FeRAM are supplied from the parallel output ports PARAa _OUT and PARAb _{OUT of} the payout control unit 24 and the effect control unit 22 to the selection circuit SEL. . The chip select signal CSa bar (CSb bar) is a negative logic pulse having a predetermined pulse width.

On the other hand, a response signal is supplied from the access control circuit DET to the parallel input ports PARAa _IN and PARAb _IN . Here, the Response signal is a response signal to the access permission request (Listen signal), and means that access is permitted when the Response signal = H level, and access is not permitted when the Response signal = L level (see FIG. 4B).

  Further, clock signals CKa and CKb and serial signals Soa and Sob are supplied from the serial ports SERIa and SERIb to the selection circuit SEL. Here, one of the clock signals CKa and CKb is selected and supplied to the clock terminal SCK of the ferroelectric memory FeRAM as the transmission clock SCK. One of the serial signals Soa and Sob is selected and supplied to the serial input terminal SI of the ferroelectric memory FeRAM. Therefore, the serial signals Soa and Sob output from the serial ports SERIa and SERIb are serial input signals SI for the ferroelectric memory FeRAM.

  As described above, the serial input signal SI at the time of the memory write includes the SWE command (06H) for permitting the memory write operation, the WRITE command (02H) for instructing the memory write operation, and an address for specifying the memory access address. A group of serial data obtained by concatenating data and a series of write data.

  On the other hand, the serial input signal SI at the time of memory read is serial data (8 + 16 bit length) obtained by concatenating a READ command (03H) for instructing a memory read operation and address data defining a memory access address. When a READ command (03H) is received from the serial output terminal SO of the ferroelectric memory FeRAM, read data from the address defined by the address data is serially output in synchronization with the transmission clock SCK. .

  Next, the access control circuit DET will be described. As shown in FIG. 4A, the access control circuit DET is configured by combining two D-type flip-flops FF1 and FF2 and various gates G1 to G8. In each flip-flop FF1, FF2, the Q bar output is fed back to the D input terminal, and each flip-flop FF1, FF2 executes a toggle operation in synchronization with the rising edge of the input signal to the clock terminal CK. It is configured as follows.

Further, the positive logic CLR signals (CLRa pulse, CLRb) output from the parallel port PARA _{OUT of} the payout control unit 24 and the effect control unit 22 via the NOR gate G4 to the clear terminals CLR of the flip-flops FF1 and FF2. Pulse) is supplied, and the flip-flops FF1 and FF2 are cleared based on one of the CLR signals.

  As shown, the Qa output of the flip-flop FF1 is supplied to the NAND gate G6, while the Qb output of the flip-flop FF2 is supplied to the NAND gate G6 via the NOT gate G5. Here, the output of the NAND gate G6 is a control signal SELECT for the selection circuit SEL. Based on the above configuration, the control signal SELECT is L only when the Qa output is H level and the Qb output is L level. Otherwise, the control signal SELECT becomes H level.

  As described above, when the control signal SELECT = H level, the 3-bit A group signal from the payout control unit 24 is selected and output from the selection circuit SEL as the Y signal. Therefore, in the present embodiment, the 3-bit A group signal from the payout control unit 24 is ferroelectric only when the Qa output of the flip-flop FF1 is H level and the Qb output of the flip-flop FF2 is L level. The B group signal from the effect control unit 22 is supplied to the ferroelectric memory FeRAM at other timings.

  As will be described later, the Qa output of the flip-flop FF1 becomes H level during a period from when the Listen (a) signal is received from the payout control unit 24 until the payout control unit 24 outputs the clear pulse CLRa. (See FIG. 4B).

  In the circuit configuration of FIG. 4A, the AND gates G1 and G2 operate based on the output of the AND gate G3, and the Listen (a) signal and the Listen (b) signal are sent to the clocks of the flip-flops FF1 and FF2. It controls whether or not to supply to the terminal CK. Here, the Listen (a) signal and the Listen (b) signal are signals for inquiring whether or not this is possible when the payout control unit 24 or the effect control unit 22 wants to access the ferroelectric memory FeRAM.

  As shown in the figure, since the Q-bar outputs of the flip-flops FF1 and FF2 are supplied to the AND gate G3, when both Q-bar outputs are at the H level, that is, the flip-flops FF1 and FF2 are in the reset state. Only in some cases, the Listen signal will be supplied to the corresponding flip-flop FFi.

  The flip-flop FFi that has received the Listen signal executes a toggle operation in synchronization with the rising edge of the Listen signal, so that the flip-flop FFi transitions from the reset state to the set state. Therefore, thereafter, the output of the AND gate G3 transitions to the L level, and reception of any Listen signal is blocked.

  In this sense, the AND gates G1 to G3 perform an earlier winning logical operation with respect to the Listen (a) signal and the Listen (b) signal. The flip-flop FFi that has transitioned to the set state enters a reset state upon receiving a positive logic CLR signal (CLRa pulse or CLRb pulse), and transitions the output of the AND gate G3 to the H level. Therefore, after receiving the CLR signal, the AND gates G1 to G3 resume the earlier winning logic operation for the Listen (a) and Listen (b) signals received thereafter.

  Incidentally, the XOR gate G7 and the AND gate G8 constitute a priority circuit that prioritizes access from the payout control unit 24. That is, the XOR gate G7 is supplied with the Listen (a) signal output from the payout control unit 24 and the Listen (b) signal output from the effect control unit 22, and it is assumed that the two Listen signals are simultaneously H. When rising to the level, the output of the XOR gate G7 becomes L level. Therefore, the Listen (b) signal cannot pass through the AND gate G8, and the flip-flop FF2 cannot be toggled.

  As is clear from the above description, when the payout control unit 24 and the effect control unit 22 simultaneously raise the Listen signal, the Listen (b) signal from the effect control unit 22 is cut off, so that the payout control is performed. Only the Listen (a) signal from the unit 24 is accepted. That is, priority is given to access from the payout control unit 24, but in this embodiment, the payout control unit 24 performs the memory write operation and the effect control unit 22 performs the memory read operation. Therefore, the memory write operation is prioritized.

  As described above, since the priority circuit using the two gates (G7 + G8) is provided in this embodiment, even if the memory access timings of the payout control unit 24 and the effect control unit 22 that operate independently and asynchronously collide, Memory Read / Memory Write operation is always guaranteed.

  FIG. 4B is a time chart for explaining the operation of the ferroelectric memory circuit 37 including the above priority operation. The two flip-flops FF1 and FF2 are initially in the reset state, and the output of the AND gate G3 is at the H level in the initial state. In this initial state, when the payout control unit 24 raises the Listen (a) signal (timing T1), this is accepted and the Qa output of the flip-flop FF1 becomes H level, so that the Response (a) signal Becomes H level.

  As a result, the output of the NAND gate G6 becomes L level, and the selection circuit SEL passes the A group signal from the payout control unit 24 and supplies it to the ferroelectric memory FeRAM. For this reason, the payout control unit that has confirmed the H level Response (a) signal lowers the chip select signal CSa bar, and then serially outputs the clock signal CKa and the serial signal Soa, and thus the ferroelectric memory FeRAM. Execute data write operation for.

  During such an operation, the production control unit 22 raises the Listen (b) signal at timing T2. At this timing, the output of the gate G3 is at the L level, so the Listen (b) signal is accepted. There is nothing. That is, since the Response (b) signal does not transition to the H level, the effect control unit 22 recognizes that the ferroelectric memory FeRAM is in the Busy state based on the H level of the Response (b) signal. Can do. Therefore, after a little waiting time, the effect control unit 22 raises the Listen (b) signal again to inquire whether the Busy state has been eliminated.

  In this embodiment, the payout control unit 24 is configured to raise the chip select signal CSa bar and output the clear pulse CLRa when the data write operation to the ferroelectric memory FeRAM is completed (timing T3). Timing T3 ′).

  Therefore, at the timing T3 ', the Qa output of the flip-flop FF1 becomes L level, and the subsequent reception of the Listen signal is permitted. Therefore, when the production control unit 22 raises the Listen (b) signal at the timing T4, this is accepted and the Qb output of the flip-flop FF2 becomes H level, so that the Response (b) signal becomes H. Become a level.

  For this reason, the production control unit 22 that has confirmed the H level Response (b) signal lowers the chip select signal CSb bar to the L level, and then serially outputs the clock signal CKb and the serial signal Sob. A data read operation is performed on the dielectric memory FeRAM.

  During such a data read operation, for example, even when the payout control unit 24 raises the Listen (a) signal at timing T5, the Listen (a) signal is not accepted.

  After that, when the data read operation for the ferroelectric memory FeRAM is finished (timing T6), the effect control unit 22 raises the chip select signal CSb bar to the H level and outputs the clear pulse CLRb. Is finished (timing T6 ′).

  Note that at timing T7, the Listen (a) signal and the Listen (b) signal are output in an overlapping manner. However, in this case, when the output of the XOR gate G7 becomes H level, the Listen (b) signal is ignored and the Listen (a) signal is accepted. That is, as described above, the memory write operation has priority over the memory read operation for the ferroelectric memory FeRAM.

  FIG. 6A is a block diagram showing an internal configuration of the serial port SERIa built in the one-chip microcomputer of the payout control unit 24. As illustrated, the serial port SERIa includes a transmission data register DR that receives 1-byte data from the CPU core, a shift register SR that receives transfer of 1-byte data from the transmission data register DR, and outputs a serial signal Soa, and a serial port And a baud rate generator BG that receives the output pulse Φ of the counter circuit CT and outputs a clock signal CKa having a frequency division ratio designated by the control register RG. Has been.

  Here, the control register RG includes a control register including the empty bit EMP and capable of performing a read operation, and indicates whether or not the transmission data register DR can accept new data. That is, when transmission of 1-byte data in the shift register SR is completed, the empty bit EMP changes to H level (empty level), indicating that new data can be written into the transmission data register DR. Therefore, the CPU core (hereinafter referred to as CPU) writes new data into the transmission data register DR after confirming that the empty bit EMP is at the H level.

  The control register RG includes a control register capable of write operation including a data output permission flag SOE, a reception permission flag RXE, and a transmission permission flag TXE. The data output permission flag SOE is ON (H). When the CPU sets the transmission permission flag TXE to the ON (H) level in the level state, the transmission operation of the serial port is permitted, and when it is set to the OFF level, the transmission operation is prohibited. Therefore, in this embodiment, the CPU sets the transmission permission flag TXE to the ON state at the start of the transmission process, and resets the transmission permission flag TXE to the OFF level at the end of the transmission process.

  Similarly, when the CPU sets the reception permission flag RXE to the ON (H) level, the reception operation of the serial port is permitted, and when it is set to the OFF level, the reception operation is prohibited. However, since the payout control unit 24 of this embodiment does not execute the serial reception operation, the data output permission flag SOE is maintained in the ON (H) state, while the reception permission flag RXE is maintained in the OFF (L) state. Therefore, the serial reception operation is constantly prohibited.

  FIG. 6B is a time chart showing an operation at the start of transmission for the serial port SERIa of the payout control unit 24. As shown in the figure, when the serial port SERIa is in the transmission prohibited state (TXE = L) or after the data of the transmission data register DR is serially output, the clock signal CKa is at the H level in the fixed state. The transmission data register DR is empty, and the empty bit EMP is also at the H level (empty level).

  Then, after the CPU sets the transmission permission flag TXE to the ON state (transmission permission state) and then writes the first byte of transmission data to the transmission data register DR, the empty bit EMP transitions to the L level, and then After a predetermined time (τ) elapses, the first byte of transmission data is transferred to the shift register SR, and the serial transmission operation is started.

  In addition, since the transmission data is transferred to the shift register SR, the empty bit EMP transitions to the H level (empty level) thereafter in response to the start of serial transmission of the first bit. Therefore, after confirming the H level empty bit EMP, the CPU writes the second byte of transmission data into the transmission data register DR.

  Then, in response to the data write operation to the transmission data register DR, the empty bit EMP transitions to the L level (full level). After that, when all the transmission data of the first byte is transmitted, the second byte of data is transferred from the transmission data register DR to the shift register SR, data transmission of the second byte is started, and the empty bit EMP is set. Transition to H level.

  The empty bit EMP changes to the L level in response to the data write operation of the third byte to the transmission data register DR. However, as shown in the figure, the empty bit EMP maintains the H level when no new data is written. . Further, after all the data has been transmitted, the clock signal CKa maintains the H level and does not change.

  In this embodiment, in correspondence with the internal operation of the ferroelectric memory FeRAM, the transmission operation is set to be executed in synchronization with the clock signal CKa from the MSB of the 1-byte data to the LSB (MSB first). ).

  As described above, the serial signal Soa output from the serial port SERIa includes the SWE command (= 06H), the WRITE command (= 02H), address data (16 bits), and an appropriate number of write data (8 bits). ) And a series of serial data.

Prior to such a memory write operation, a listen (a) signal (listen pulse) is output from the parallel output port PARAa _OUT , and then a response (a) signal is obtained from the parallel input port PARAa _IN. As described above, the L level chip select signal CS bar is output from the parallel output port PARAa _OUT on the condition that it is at the H level (see FIGS. 7A and 7D). Similarly, when a series of memory write operations are completed, the H level chip select signal CS bar is output from the parallel output port PARAa _OUT .

  As described above, the ferroelectric memory circuit 37 has been described in detail. Returning to FIG. 3, the overall configuration of the gaming machine will be further described. As shown in FIG. 3, corresponding to the frame side member GM1 having the payout control unit 24 on which the ferroelectric memory circuit 37 is mounted, the main control board 21, the effect control board 22, the image on the back of the game board 5 The control board 23 is fixed together with the display device DS and other circuit boards. And the frame side member GM1 and the board | substrate side member GM2 are electrically connected by the connection connectors C1-C4 concentratedly arranged in one place.

  The main board relay board 32 outputs the power abnormality signal ABN1, the backup power supply BAK, and DC5V, DC12V, and DC32V output from the power board 20 to the main control unit 21 as they are. On the other hand, the power relay board 33 outputs the system reset signal SYS received from the power board 20 and the AC and DC power supply voltages to the effect interface board 27 as they are. The effect interface board 27 outputs the received system reset signal SYS to the effect control unit 22 'and the image control unit 23' as it is.

  In this embodiment, the RAM clear signal CLR is generated by the main control unit 21 and transmitted to the one-chip microcomputer of the main control unit 21 and the payout control unit 24. Here, the RAM clear signal CLR is a signal for deciding whether or not to initialize all the areas of the built-in RAM of the one-chip microcomputer of each control unit 21 and 24. The initialization switch SW operated by the attendant is turned on. It has a value corresponding to the / OFF state.

  The main control unit 21 and the payout control unit 24 receive the power supply abnormality signals ABN1 and ABN2 from the power supply board 20 to start necessary end processing prior to a power failure or business end. The backup power supply BAK is a DC5V DC power source that retains data in the RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24 even after the AC power supply 24V is shut off due to business termination or power failure.

  Therefore, the main control unit 21 and the payout control unit 24 can resume the game operation before power-off after power-on (power backup function). This pachinko machine is designed to retain the stored contents of the RAM of each one-chip microcomputer for at least several days. However, since the ferroelectric memory FeRAM of the ferroelectric memory circuit 37 is a non-volatile memory using the polarization of the ferroelectric, it is not necessary to supply the backup power supply BAK at all.

  As shown in FIG. 3, the main control unit 21 transmits a control command CMD ″ to the payout control unit 24 via the main board relay board 32, while the payout control unit 24 indicates a game ball payout operation. A prize ball counting signal, a status signal CON relating to an abnormality in the payout operation, and an operation start signal BGN are received, and the status signal CON includes, for example, a replenishment signal, a payout shortage error signal, and a lower plate full signal. The operation start signal BGN is a signal for notifying the main control unit 21 that the initial operation of the payout control unit 24 has been completed after the power is turned on.

  The main control unit 21 is connected to each game component of the game board 5 via the game board relay board 31. And while receiving the switch signal of the detection switch built in each winning opening 16-18 on a game board, solenoids, such as an electric tulip, are driven. The solenoids and the detection switch are configured to operate with the power supply voltage VB (12 V) distributed from the main control unit 21. Each switch signal indicating a winning state to the symbol start opening 15 is converted to a TTL level or CMOS level switch signal by an interface IC that operates with the power supply voltage VB (12 V) and the power supply voltage Vcc (5 V). And then transmitted to the main control unit 21.

  In this embodiment, a plurality of detection sensors capable of detecting illegal acts are arranged on the game board, and an abnormal signal from each detection sensor is sent to the main control unit 21 via the game board relay board 31. Is being transmitted.

  Examples of illegal games that can be detected include (1) an act of guiding the game ball to the symbol start port 15 by a magnet or vibration, and (2) an act of causing the detection switch of the symbol start port 15 to malfunction by an illegal radio wave, (3) For example, an act of forcibly opening the closed symbol starting port 15 or the grand prize winning port 16 with a wire or the like.

  And the main control part 21 which grasped | ascertained generation | occurrence | production of these abnormal situations is comprised so that the abnormality notification command corresponding to the grasped abnormality may be transmitted to effect control part 22 '. It should be noted that the abnormality notification command is (4) when the detection frequency of the detection switch of the normal winning opening 17 or the gate 18 is abnormally high, or (5) when receiving a notification from the payout control unit 24 that the door opening is detected. Also transmitted to the effect control unit 22 ′.

  By the way, the production control board 22 and the production interface board 27 are integrated by connector connection, and the production control unit 22 ′ is connected to the DC voltage (5 V) of each level from the power supply board 20 via the power supply relay board 33. , 12V, 32V) and the system reset signal SYS (see FIGS. 3 and 8). Further, the effect control unit 22 'receives the control command CMD and the strobe signal STB from the main control unit 21 via the command relay board 26 (see FIGS. 3 and 8).

  The effect control unit 22 ′ supplies lamp drive data (serial signal) to the driver mounted on the lamp drive board 29 and the lamp drive board 30 via the effect interface board 27. Although not particularly limited, the driver mounted on the lamp driving substrates 29 and 30 has the same configuration as the driver mounted on the lamp driving substrate 36.

  As shown in FIG. 3 and FIG. 8, the effect control unit 22 ′ has two types of control command CMD ′ and strobe signal STB ′, and a system reset signal SYS received from the power supply board 20, for the image control unit 23 ′. DC voltage (12V, 5V).

  Then, the image controller 23 'drives the display device DS based on the control command CMD' to execute various image effects. The display device DS emits light by an LED backlight, and is driven by receiving five pairs of LVDS (Low voltage differential signaling) signals and a backlight power supply voltage (12 V) from the image interface board 28. (See FIG. 8).

  Next, the configurations of the effect control unit 22 'and the image control unit 23' will be described in more detail. As shown in FIG. 8, the production interface board 27 receives three types of DC voltages (5V, 12V, and 32V) from the power supply board 20 via the power supply relay board 33. Here, the DC voltage 5V is distributed as power supply voltage of the digital logic circuit to the rendering interface board 27, the lamp driving board 29, the lamp driving board 30, the image interface board 28, and the image control board 23, and is supplied to each digital circuit. Is operating.

  However, the direct current voltage 5V is not distributed on the effect control board 22, and the direct current voltage 3.3V stepped down from 12V by the DC / DC converter and the direct current stepped down from 3.3V by the DC / DC converter. Only the voltage 1.8V is distributed from the production interface board 27 to the production control board 22.

  In this way, the production control board 22 of the present embodiment is driven by the power supply voltage of 3.3V or lower because all the circuits are driven. Therefore, even if the production interface board 27 is arranged and laminated immediately above the production control board 22, there is no problem in heat dissipation.

  However, the DC voltage 12V received from the power supply board 20 is used as it is as the power supply voltage of the digital amplifier 46 and is distributed to the lamp drive board 30 and the lamp drive board 29 to become the power supply voltage of each lamp group. The direct current voltage 32V is stepped down to the direct current voltage 13V in the DC / DC converter of the production interface board and used as a drive power source for the production motors M1 to Mn as necessary.

  As shown in FIG. 8A, the effect control unit 22 ′ includes a one-chip microcomputer 40 that executes processing such as voice effect / lamp effect / notice effect / data transfer by effect movable body in units of 16 bits, and one chip. A ROM 41 that stores a control program for the microcomputer 40, a voice synthesis circuit 42 that reproduces and outputs a voice signal based on an instruction from the one-chip microcomputer 40, and compressed voice data that is the original data of the reproduced voice signal An audio memory 43 to be stored, a ferroelectric memory 38 capable of reading / writing in 16-bit units, and a real-time clock RTC are provided.

  Here, the real-time clock RTC is a clock IC that measures the current date and time, and is permanently operated by the secondary battery BT charged with the power supply voltage VDD of the effect control unit 22 '. That is, the secondary battery BT is charged while the gaming machine is powered on, and after the gaming machine is powered off, the internal circuit counts based on the charged secondary battery BT. Operation continues (backup operation).

  As shown in FIG. 8B, the real-time clock RTC of the embodiment is sent to the CPU of the one-chip microcomputer 40 through a 4-bit data bus, a 4-bit data bus, and a control bus RD + WR for Read / Write operation. It is connected. Then, the CPU stores important game information and abnormality information related to the game operation in the ferroelectric memory 38 by adding date information, day information and time information acquired from the real-time clock RTC. .

  This real-time clock RTC has two types of chip select terminals, CS1 and CS0 bars, and permits access from the CPU on condition that the input voltage to each terminal is at a normal level. Yes. Here, the CS0 bar terminal is a normal chip select terminal that receives the output of the address decoder. On the other hand, the CS1 terminal receives the output (voltage drop signal) Vo of the power supply abnormality detecting unit ER, and when the CS1 terminal receives the abnormal level output Vo, the abnormality detection flag Fos of the real-time clock RTC is automatically set. To be set.

  In the case of this embodiment, this abnormality detection flag Fos is determined by the CPU of the one-chip microcomputer 40 together with other abnormality detection flags TEMP when the power is turned on. If the abnormality detection flag Fos is set, the year at that time The date and time are notified. Therefore, if an abnormality in the clock function is recognized, it can be dealt with quickly.

  Even if the voltage of the secondary battery BT drops when the power is shut down, the voltage level of the secondary battery BT is quickly recovered by power recovery and the CS1 terminal returns to the normal level, so that access from the CPU is permitted. It will be. Therefore, when the configuration of the present embodiment in which the determination processing of the abnormality detection flag Fos is not adopted, there is a possibility that the abnormality of the real time clock RTC cannot be detected permanently.

  The real-time clock RTC of the embodiment is configured to output the interrupt signal IRQ once a week, for example, every Friday at 21:50. In the CPU that has received the interrupt signal IRQ, The game information and abnormality information stored in the ferroelectric memory 38 are appropriately tabulated.

  The game information to be aggregated is a summary of history information related to the big hit state. For example, (1) the number of winnings to the symbol start opening required to become the big hit state, (2) the symbol of the big hit state, Total value and statistical value of jackpot state whether or not it is probable, (3) type of notice effect or reach effect that reached the big hit state, (4) number of consecutive chants, (5) number of balls thrown out by consecutive chans Increasing trends are included. And these total information and statistical information are alert | reported suitably according to a player's request | requirement. The player's instruction is specified by, for example, pressing the chance button 11 during the demonstration effect, and the notification content is displayed on the display device DS.

  On the other hand, the abnormal information to be tabulated includes, for example, (1) the number of times the door is opened, (2) the detection type, the number of detection times and the detection time of the detection sensor for detecting illegal activities, This includes the number of detections, detection frequency, detection time, etc. of an act of forcibly opening the winning opening 16 with a wire or the like. The total information is displayed on the display device DS in response to a special operation by an attendant.

  As shown in FIGS. 8B to 8D, the real-time clock RTC of the embodiment is configured to have three internal register tables Bank0 to Bank2. Each register table is composed of 4 bytes × 16 registers, and the current date and time measured by the internal circuit are written in the Bank0 register table (FIG. 8C). Yes. Note that the Bank2 register table relates to time setting and date setting, and is not shown in FIG.

  As shown in FIG. 8C, in the register table of Bank0, bit 3 of the first register is an abnormality detection flag Fos, and bit 2 of the 14th register indicates that the built-in temperature sensor has detected an abnormal temperature. This is a temperature abnormality flag TEMP shown. In this embodiment, when the CPU of the effect control unit 22 is reset, the value of the abnormality detection flag Fos is determined, thereby preventing the abnormal timekeeping operation from continuing. In addition, the real-time clock RTC is disposed close to the one-chip microcomputer 40, and the temperature abnormality flag TEMP is repeatedly determined at appropriate time intervals to quickly detect the temperature abnormality of the one-chip microcomputer 40.

  In the register table of Bank0, bit 0 of the 15th register is a Busy flag indicating that the register table is being updated. In this embodiment, the current date and time are acquired from the register table of Bank 0 on the condition that the Busy flag is in a non-Busy state (update completion). For this reason, in this embodiment, there is no possibility of acquiring halfway during the update operation or irrational clock information, and the validity of the clock information stored in the ferroelectric memory 38 is ensured. For example, if clock information that is being updated from 1:59:59 to 2: 00: 00: 00 is acquired, there is a possibility that the clock information of 1: 0: 0 is acquired.

  Further, the register table of Bank 1 is configured so that the generation time of the interrupt signal IRQ can be set. Therefore, in this embodiment, an interrupt generation is instructed by setting 1 to bit 0 of the register No. 1 of Bank 1 (Interrupt Enable), and the day of the week of Friday is designated in the registers 0 to 8 of Bank 1. Time information of 30:30 hours is set.

  Although the real-time clock RTC has been described above, the present embodiment has a significant feature in that the effect control unit 22 ′ includes the ferroelectric memory 38. The ferroelectric memory 38 arranged in the effect control unit 22 ′ is a 512 Kbyte R / W-capable memory that operates at a single power source and can be randomly accessed. By connecting two in parallel (see FIG. 10), a nonvolatile memory having a storage capacity of 16 bits × 524288 is formed.

The internal configuration of the ferroelectric memory 38 is as shown in FIG. 9. By setting the CE1 bar terminal = L level and the CE2 terminal = H level, it can be driven in the same manner as a normal SRAM (asynchronous SRAM). It is. That is, the ferroelectric memory 38 changes the address signals A0 to A18 of the 19-bit address bus, and then changes the chip select signals CE2 and CE1 bars to the active level, and at the falling edge of the output enable signal OE bar. Since the read operation is started and valid read data appears at the output terminals I / O _{1 to} I / O ₈ during the period of +30 nS to +120 nS, the Read operation can be completed within the period. Since the above operation is simultaneously executed in the two ferroelectric memories 38, the CPU acquires 16-bit data collectively by the above-described Read operation.

Further, after changing the address signals A0 to A18 of the address bus and outputting significant 16-bit data to the data bus (input terminals I / O _{1 to} I / O _{8 of} each ferroelectric memory 38), the chip select signal is output. When the CE2 and CE1 bars are set to the active level, the write operation is started at the falling edge of the write enable signal WE bar. When the 16-bit data on the data bus is held for about 50 nS, the write operation is completed. Since this operation is also simultaneously executed in the two ferroelectric memories 38, 16-bit data is stored in the ferroelectric memory 38 by a series of write operations.

  As described above, according to the present embodiment, in the memory space to be accessed by the one-chip microcomputer 40, Rs at addresses 524 and 288 that can be randomly accessed in the same procedure as other ordinary memories (ROM and SRAM). A non-volatile memory capable of / W is arranged, and there is an advantage that necessary information can be stored permanently without a backup power source.

  The information stored and stored in the ferroelectric memory 38 includes the winning ball results read from the ferroelectric memory FeRAM of the payout control unit 24, the contents of the abnormality notification command received from the main control unit 21, and the control received from the main control unit 21. Game information based on commands (such as variation pattern commands) is included.

The one-chip microcomputer 40 that can access the ferroelectric memory 38 includes a plurality of parallel input / output ports PIO (Pi + Po + Po ′) and a serial port SERIb. The parallel input / output port Po ′ includes a parallel output port PARAb _OUT and a parallel input port PARAb _IN shown in FIG. The internal configuration of the serial port SERIb is as shown in FIG. 10A and is substantially the same as the circuit configuration and circuit operation of FIG.

  That is, the serial port SERIb of the production control unit 22 receives the 1-byte data from the CPU core, and receives the 1-byte data from the transmission data register DR to output the serial signal Sob, while receiving it from the outside. A shift register SR that receives the serial signal Sin bit by bit, a receive data register RR that receives 1-byte-length received data stored in the shift register SR as parallel data, and a number of controls that manage the internal operating state of the serial port A register RG and a baud rate generator BG that receives the output pulse Φ of the counter circuit CT and outputs a clock signal CKb having a frequency division ratio designated by the control register RG are configured.

  In this embodiment, the serial signal Sin is Read data read from the ferroelectric memory FeRAM disposed in the payout control unit 24, and includes a data output permission flag SOE, a transmission permission flag TXE, and a reception permission flag RXE ( In an appropriately set state (see FIG. 10B), the data is transmitted in synchronization with the clock signal CKb output from the serial port SERIb.

  The serial port SERIb of the effect control unit operates in a transmission / reception operation mode in which Read data is received following the READ command transmission processing and the read address transmission operation based on the set values in the flags SOE, TXE, RXE. To do. As described above, the data output permission flag SOE, the transmission permission flag TXE, and the reception permission flag RXE are a kind of flags included in the control register RG. The control register RG also includes a reception completion flag RDRF shown in FIG.

  However, before the serial port SERIb starts the above-described transmission / reception operation, it is necessary to confirm that the ferroelectric memory FeRAM of the payout control unit 24 is not in the Busy state prior to this. If the ferroelectric memory FeRAM is in the non-busy state, a preparatory operation for outputting the L level chip select signal CSb bar is required.

  After such a preparatory operation, the serial port SERIb serially transmits a READ command (= 03H) and read address data to the ferroelectric memory FeRAM under the control of the CPU. Thereafter, read data output from the ferroelectric memory FeRAM is serially received (see FIG. 7C).

In order to realize the above operation, the CPU first outputs the Listen (b) signal from the parallel output port PARAb _OUT, and the response (b) signal acquired at the parallel input port PARAb _IN changes to the H level. Confirm (see FIGS. 10 and 4B). If Response (b) = H level, the CPU next outputs a chip select signal CSb bar of L level from the parallel output port PARAb _OUT , and then follows the communication protocol shown in FIG. The serial transmission / reception operation is started.

  FIG. 8B is a time chart for explaining the serial transmission / reception operation, but for the sake of convenience, only the memory read operation is shown. However, the transmission operation of the READ command (= 03H) and the read destination address data is the same as in the case of FIG. 6B.

  That is, in the serial transmission / reception operation, the CPU sets the data output permission flag SOE = H level, the transmission permission flag TXE = H level, and the reception permission flag RXE = H level in the transmission data register DR of the serial port SERIb. The READ command (= 03H) and the read destination address data (16 bits) are written for each byte. As described with reference to FIG. 6B, the write operation to the transmission data register DR is performed while determining the empty bit EMP of the control register RG.

  In the transmission / reception operation mode, the output of the clock signal CKb is continued even after the serial transmission operation described above. After the ferroelectric memory FeRAM obtains the 3-byte data, the ferroelectric memory FeRAM The read data from the specified address is serially output. The read data is acquired (sampled) in the shift register SR in synchronization with the rising edge of the clock signal CKb (see FIG. 10B).

  When the shift register SR acquires the eighth bit data from the ferroelectric memory FeRAM, the 1-byte data of the shift register SR is transferred to the reception data register RR and the reception completion flag RDRF of the control register RG is set. Turns on. Therefore, in response to this operation, when the CPU that has grasped the reception completion flag RDRF in the ON state reads 1-byte data in the reception data register RR, the reception completion flag RDRF returns to the OFF state. After that, the reception completion flag RDRF is turned on again at the timing when the next 1-byte data is transferred from the shift register SR to the reception data register RR. Therefore, the same operation as described above may be repeated thereafter.

  When the necessary data is acquired, the CPU ends the serial transmission / reception operation by setting the data output permission flag SOE = L level, the transmission permission flag TXE = L level, and the reception permission flag RXE = L level. . In this embodiment, when EOF data (= 00H) is received, it is determined that acquisition of necessary data has been completed.

When the serial transmission / reception operation is completed by the above determination, an H level chip select signal CSb bar is output from the parallel output port PARAb _OUT , and then a clear pulse CLRb is output (see FIG. 4B). When the H-level chip select signal CSb bar is supplied to the ferroelectric memory FeRAM of the payout control unit 24, the access operation of the ferroelectric memory FeRAM is completely completed.

  As described above, the ferroelectric memory 38 and the serial port SERIb of the effect control unit 22 have been described in detail with reference to FIGS. 9 to 10, and another configuration of the effect control unit 22 will be described with reference to FIG. . As shown in FIG. 8, the lamp driving boards 36, 29, 30 are also connected to the parallel output port Po ′ of the parallel input / output port PIO. The drivers mounted on the lamp driving boards 36, 29, 30 are The operation is started based on any of the 3-bit length operation permission signals output from the parallel output port Po ′.

  On the other hand, the control command CMD and the strobe signal STB from the main control unit 21 are input to the input port Pi of the parallel input / output port PIO, and the control command CMD ′ and the strobe signal STB ′ are output from the command output port Po. It is comprised so that.

  Specifically, a control command CMD and a strobe signal (interrupt signal) STB output from the main control board 21 correspond to the power supply voltage 3.3 V in the buffer 44 of the effect interface board 27 at the input port Pi. Converted to a logic level to be supplied in units of 8 bits. The interrupt signal STB is supplied to the interrupt terminal of the one-chip microcomputer, and the effect control unit 22 'is configured to acquire the control command CMD by the reception interrupt process.

  The control command CMD acquired by the effect control unit 22 ′ specifies (1) an abnormality notification command and other notification control commands, and (2) an outline of various effect operations resulting from winning at the symbol start opening. A control command (variation pattern command) and a control command (designation command) for designating a design type are included. Here, the outline of the production operation specified by the variation pattern command includes the production total time from the production start to the production end and the result of winning or failing in the jackpot lottery.

  In addition, the symbol designating command includes information for identifying information on the jackpot type (15R probability variation, 2R probability variation, 15R normal, 2R normal, etc.) in the case of a jackpot according to the result of the jackpot lottery. In some cases, information for identifying a loss is included. The outline of the production operation specified by the variation pattern command includes the production total time from the production start to the production end, and the result of success or failure in the big hit lottery. In addition to these, the change pattern command including the presence or absence of the reach effect or the notice effect may be specified, but even in this case, the specific content of the effect content is not specified.

  Therefore, when the change pattern command is acquired, the effect control unit 22 ′ performs an effect lottery subsequently to further specify the effect outline specified by the acquired change pattern command. For example, the specific contents of the reach effect and the notice effect are determined. Then, in accordance with the determined specific game content, a lamp effect by blinking LEDs and a sound effect preparation operation by a speaker are performed, and an effect operation by a lamp or speaker is performed on the image control unit 23 ′. A control command CMD ′ relating to the synchronized image effect is output.

  In order to realize such an image effect synchronized with the effect operation, the effect control unit 22 ′, along with the strobe signal (interrupt signal) STB ′ for the image control unit 23 ′, is sent to the image control unit 23 ′ through the command output port Po. CMD ′ is output toward the production interface board 27. When the production control unit 22 ′ receives a design designation command, a notification control command related to the display device DS, and other control commands, the control command is summarized in a 16-bit length. It is output toward the production interface board 27 together with the interrupt signal STB ′.

  Corresponding to the configuration of the production control board 22 described above, the production interface board 27 is provided with an output buffer 45, and a 16-bit control command CMD ′ and a 1-bit interrupt signal STB ′ are sent to the image interface. It is output to the substrate 28. These data CMD ′ and STB ′ are transmitted to the image control board 23 via the image interface board 28.

  The effect interface board 27 is provided with a digital amplifier 46 that receives the audio signal output from the audio synthesis circuit 42. As described above, the speech synthesis circuit 42 operates with power supply voltages of 3.3 V and 1.8 V, and the digital amplifier 46 performs class D amplification operation with a power supply voltage of 12 V, reducing power consumption. It is possible to produce a loud sound while suppressing it.

  The left and right speakers at the upper part of the gaming machine and the speakers at the lower part of the gaming machine are driven by the output of the digital amplifier 46. Therefore, the voice synthesis circuit 42 needs to generate a three-channel voice signal, and if this is transmitted in parallel, the wiring between the voice synthesis circuit 42 and the digital amplifier 46 becomes complicated.

  The effect interface board 27 is provided with parallel output port Po 'of the one-chip microcomputer 40, serial buffer SI, and output buffer circuits 47, 48, and 49 for transmitting various signals to be output. Here, the output buffer 47 is related to the LED group of the 0th channel, and outputs various data output by the one-chip microcomputer 40 to the frame relay board 34. The output 3-bit signal is transmitted to the driver of the lamp driving board 36 via the frame relay board 34 and the frame relay board 35.

  Similarly, the output buffer 48 transmits various data output from the one-chip microcomputer 40 to the driver of the lamp driving board 29, and the output buffer 49 transmits various data to the driver of the lamp driving board 30. ing.

  Next, control operations executed by the CPUs of the payout control unit 24 and the effect control unit 22 will be described for the gaming machine GM of the embodiment having the above-described configuration.

  FIGS. 11 to 12 are flowcharts for explaining the control operation of the payout control unit 24. The control operation of the payout control unit 24 is realized by including a main routine (FIG. 11 (a)) executed after the CPU reset and a timer interrupt routine (FIG. 12 (a)) started at regular intervals. Yes.

  The operation content of the main routine (FIG. 11 (a)) will be described. When the power is turned on, the CPU sets itself to the interrupt disabled state (DI) (ST1) and then includes the serial port SERIa. Initial setting of each part of the chip microcomputer is performed (ST2).

  Next, it is checked whether or not the RAM clear signal CLR is supplied from the main control unit 21 (ST3). In this embodiment, the RAM clear signal CLR is supplied when the game hall is in operation, particularly when the clerk turns on the RAM clear switch. The signal CLR is not supplied.

  When the RAM clear signal CLR is not supplied, the value of the backup flag BAKFLG stored in the power monitoring process (FIG. 12A) is checked (ST4). If BAKFLG = 5AH, then the same checksum operation as in the power monitoring process is executed to calculate the sum value (ST5), which matches the sum value stored in the RAM area. Whether or not (ST6). If the sum value calculated in the main routine matches the sum value stored in the power supply monitoring process (ST31), it is considered that the process before power-off can be resumed, so the backup flag BAKFLG is cleared. (ST7).

  On the other hand, (1) as a result of the determination in step ST3, the RAM clear signal CLR is in an ON state, (2) as a result of the determination in step ST4, the backup flag is a value other than 5AH, or (3) step If an abnormality is recognized in the ST6 check, all the RAM areas are cleared (ST8).

  Next, the CPU initializes the write pointer PNT for the ferroelectric memory FeRAM to the value of the leading address-1 of the ferroelectric memory FeRAM, and at the same time, sets the EOF data ( Clear data) is written (ST9). As described above, in this embodiment, the payout control unit 24 stores the prize ball result data in order from the top address of the ferroelectric memory FeRAM every day (Write access), while the prize ball result is recorded. The effect control unit 22 is configured to read the data at an appropriate timing (Read access).

  In this embodiment, the number of payouts paid out to the player as a winning ball motion is managed by the variable NUM, and every time the payout number NUM reaches a reference value MAX (for example, 50). The award ball performance data is sequentially stored in the ferroelectric memory FeRAM of the payout control unit 24 (see FIGS. 12C and 11C). Incidentally, a part of the payout number NUM is settled corresponding to the fact that the winning ball performance data is stored in the ferroelectric memory FeRAM. Specifically, in step 45 of FIG. 12C, the operation of NUM ← NUM-MAX is executed.

  Further, the write address position of the ferroelectric memory FeRAM is managed by the write pointer PNT of the payout control unit 24. After the payout control unit 24 stores the winning ball result data, the next address position is EOF data is written (see FIG. 11C). Then, the effect control unit 22 that performs read access to the ferroelectric memory FeRAM confirms the EOF data, and determines that there is no winning ball result data at the subsequent addresses.

  Therefore, in the present embodiment, there is a possibility that the presentation control unit 22 may read-access the ferroelectric memory FeRAM before the payout control unit 24 writes the winning ball result data for the day into the ferroelectric memory FeRAM. In consideration of this, EOF data is written at the start address position of the ferroelectric memory FeRAM (ST9 in FIG. 11A).

  When the writing process (ST9) of the ferroelectric memory FeRAM having the above significance is completed, the CPU is set to the interrupt permitting state (ST10), and the infinite loop process is repeated. When the CPU enters an interrupt enabled state, the periodic processing (ST30 to ST40) shown in FIG. 12A is executed by a subsequent timer interrupt.

  FIG. 11B is a flowchart showing in detail the operation content of the writing process (ST9) to the ferroelectric memory FeRAM. Specifically, the CPU outputs a Listen (a) pulse (ST11), and obtains a Response (a) signal after a predetermined time (ST12). When it is confirmed that the response (a) is changed to the H level and the ferroelectric memory FeRAM is not in the Busy state, an L-level CSa bar signal is output (ST17). If the ferroelectric memory FeRAM is in the Busy state, the number of repetitions CNT is counted and a retry is made after a standby time (ST14 to ST15). Note that error processing is executed when the ferroelectric memory FeRAM is abnormal in which the Busy state is continued (ST16).

  On the other hand, if the ferroelectric memory FeRAM is in the non-busy state, subsequent to the processing in step ST17, the SWE command output processing (ST18) and the WRITE command output processing (to the ferroelectric memory FeRAM) ( ST19) After executing the write address output process (ST20), the EOF data output process is executed (ST21).

  By this operation, the write operation shown in FIG. 11D is realized for the ferroelectric memory FeRAM. As described above, the write address at this time is the head address of the ferroelectric memory FeRAM (ST9). When the above processing is completed, an H-level CSa bar signal is output (ST22), and a CLR (a) pulse is output to complete the processing (ST23).

  Next, the timer interrupt routine of the payout control unit 24 will be described with reference to FIG. In the timer interrupt routine, a power supply monitoring process for monitoring the voltage drop signal ABN is executed (ST31).

  In this power supply monitoring process (ST31), the backup flag BAKFLG setting process and the same calculation process as in step ST5 are executed. In addition to these, the process shown in FIG. 12B is executed.

  That is, after the write pointer PNT is incremented (ST41), the payout number NUM at that time is written to the PNT address of the ferroelectric memory FeRAM and EOF data is written to the next address (ST42). Such processing is executed when the game machine power supply is shut down and memorized the award ball performance data that has not been written in the ferroelectric memory FeRAM so far (below the reference value MAX). It is to do.

  Prior to the processing of step ST42, the inquiry processing (ST11 to ST16) shown in FIG. 11B and the transmission preparation processing (ST17 to ST19) shown in FIG. Of course, after the writing of EOF data (ST42), the transmission end processing (ST22 to ST23) shown in FIG. 12 (f) is executed.

  In addition, prize ball performance data that is less than the reference value MAX at the end of business on the day stored when the power is shut off is executed when the power is turned on the next day, and the initial setting process of the effect control unit 22 (see ST51 in FIG. 13). Is read-accessed and acquired in the ferroelectric memory 38 of the effect control unit 22 (see FIG. 14B).

  When the power supply monitoring process (ST31) having the above significance is finished, the payout control process similar to the normal payout control unit is executed (ST32 to ST40), and the timer interrupt process is finished. However, in the present embodiment, the process of FIG. 12C is added as the prize ball process (ST37).

  That is, when a prize ball is paid out to the player, the payout number NUM is increased by cumulative calculation (ST43), and it is determined whether or not the cumulative value NUM exceeds the reference value MAX (ST44). If the accumulated value NUM exceeds the reference value MAX, the payout number NUM is settled by the calculation of NUM ← NUM-MAX (ST45).

  Next, after the write pointer PNT is incremented (ST46), the busy state of the ferroelectric memory FeRAM is inquired (ST47), and the transmission preparation process shown in FIG. 12D is executed (ST48). Thereafter, a data writing process is executed (ST49). Specifically, as shown in FIG. 12E, a write address value which is a PNT value is output (ST20), and a specified value (FFH) is written to the corresponding address (PNT address) of the ferroelectric memory FeRAM. (ST21), EOF data is written to the next address (ST21 '). Finally, the transmission end process shown in FIG. 12 (f) is executed (ST50). With the above process, the write process shown in FIG. 12G is completed.

  Next, the operation of the effect control unit 22 will be described based on FIG. The control operation of the effect control unit 22 is performed from a main routine (FIG. 13A) executed after the CPU reset, a timer interrupt routine (not shown) activated at regular intervals, and a clock IC (real time clock) RTC. And an interrupt routine (FIG. 13B).

  In this embodiment, the winning ball result data of the ferroelectric memory FeRAM (payout control unit 24) is intermittently acquired by the effect control unit 22 (Read access) and acquired from the real-time clock RTC (FIG. 8B). Along with the time information, the game management list TBL1 (ferroelectric memory 38) shown in FIG. The read pointer PT1 is used for the Read access of the prize ball achievement data, and the write pointer PT2 is used for the storage operation of the prize ball achievement data. The values PT1 and PT2 of these pointers are used for the effect control unit. 22 is stored in the ferroelectric memory 38 in a nonvolatile manner.

  For error information specified based on the abnormality notification command received from the main controller 21, time information acquired from the real-time clock RTC in the error management list TBL2 (ferroelectric memory 38) shown in FIG. And stored in a nonvolatile manner. Note that the writing pointer PT3 used at this time is also stored in the ferroelectric memory 38 of the effect control unit 22 in a nonvolatile manner.

  Based on the above, the main routine (FIG. 13A) will be described. When power is turned on to the gaming machine, the CPU initializes each part of the one-chip microcomputer 40 including the serial port SERIb, and reads the abnormality flag Fos of the real-time clock RTC. If so, the time abnormality is notified (ST51).

  As described above, the abnormal flag Fos in the set state means that there is a voltage drop in the secondary battery BT for the real-time clock RTC when the power is turned off. In the case of the present embodiment, the set state of the abnormality flag Fos is configured to be maintained thereafter, so that the clerk resets the time information of the real-time clock RTC in response to the time abnormality notification operation. As long as the abnormality flag Fos is not reset by the initial processing, the same time abnormality is notified on the next day, and as a result, the validity of the time information of the real-time clock RTC is always ensured.

  In addition, as initial setting processing, unacquired winning ball result data before power-off of the previous day is acquired from the ferroelectric memory FeRAM of the payout control unit 24 (ST51). Specifically, the ferroelectric memory FeRAM of the payout control unit 24 is read-accessed, the payout number for the previous day that has not been acquired is acquired based on the read pointer PT1, and the acquired payout number is set as the write pointer PT2. Is stored in the game management list TBL1 of the effect control unit 22 (see the last column in FIG. 14B). Note that 24:00:00 of the previous day is stored in the corresponding column of the game management list TBL1 as time information.

  As described above, the read pointer PT1 and the write pointer PT2 are stored in the ferroelectric memory 38 of the effect control unit 22 in a nonvolatile manner. Therefore, the read operation is performed until the corresponding address of the ferroelectric memory FeRAM of the payout control unit 24 is read-accessed based on the value of the read pointer PT1 when the power is turned on, and then the read operation is continued until EOF data is detected. Get the number of payouts for the unacquired.

  The Read operation includes a Listen (b) pulse output process, a response (b) signal level determination process to be acquired thereafter, and a reception preparation process (RT17 to RT18) shown in FIG. Preceded. Further, the read operation is specifically as shown in FIG. 13 (e), in which the read address (PT1 value) output processing (RT20) and the ferroelectric memory FeRAM (payout control unit 24) read out. And processing (RT21) for storing data in the corresponding column of the game management list TBL1 indicated by the write pointer PT2. Finally, the reception end process shown in FIG. 13 (f) is executed.

  FIG. 14B shows the game management list TBL1 after the completion of the initial process (ST51), and in the final column, the award ball performance (final number) of 24:00:00 is displayed as the initial process ( The prize ball performance data (137 pieces) acquired in ST51) is described. In the present embodiment, since such an initial process (ST51) is provided, the effect control unit 22 determines the number of payouts stored in the ferroelectric memory FeRAM of the payout control unit 24 for each specified value (for example, 50). Despite intermittent Read access, the production control unit 22 can accurately grasp the number of payouts on the previous day. After the initial process (ST51) is completed, the read pointer PT1 is initialized to indicate the initial position of the ferroelectric memory FeRAM of the payout control unit 24.

  Thereafter, every time the number of interruptions by the timer interruption process (not shown) exceeds 15, the normal production control process (ST53 to ST59) as the production control unit 22 is executed. However, in the present embodiment, the process of FIG. 13C is added as the command analysis process (ST54).

  That is, when a variation pattern command is received from the main control unit 21, it is determined based on a predetermined update condition whether or not to update the winning ball results. The update conditions are set as appropriate, but in this embodiment, (1) receiving the variation pattern command of the lost state continuously five times, or (2) receiving the variation pattern command of the big hit state, Is an update condition. The big hit state is classified into a probability variation and a non-probability variation.

  On the other hand, if such an update condition is not satisfied, it is next determined whether or not an abnormality notification command has been received (ST71). As described above, in this embodiment, in this embodiment, (1) abnormalities in detecting magnets and vibrations, (2) abnormalities in detecting illegal radio waves, (3) abnormalities in which the symbol start opening 15 is unreasonably released The main control unit 21 is configured to transmit an abnormality notification command to that effect when (4) an abnormality is detected at the normal winning opening 17, and (5) when the door is opened.

  Therefore, the production control unit 22 that has received such an abnormality notification command accesses the real-time clock RTC to acquire time information, and associates the acquired time information with the abnormality notification command to cause an error in the ferroelectric memory 38. Stored in the corresponding column of the management list TBL2 (FIG. 14C). Note that the corresponding column of the error management list TBL2 is specified by the write pointer PT3.

  At this time, the storage contents of the game management list TBL1 are acquired, the cumulative payout number so far is specified, and stored in the corresponding column of the error management list TBL2. Since the data read operation from the game management list TBL1 and the data write operation to the error management list TBL2 are executed in the same procedure as the random access to the normal SRAM, a special control process (access process) is performed. It is never needed.

  In this way, in this embodiment, every time an abnormality notification command is received, the cumulative number of payouts so far is stored, so the number of payouts after receiving the above-described abnormality notification commands (1) to (5) is calculated. Then, it can be grasped at the timing of receiving the abnormality notification command. An appropriate abnormality notification operation can be executed by comprehensively evaluating the reception frequency of the abnormality notification command, the number of payouts after receiving the abnormality notification command for the first time, and the like.

  The abnormality notification command has been described above. Next, a case where a variation pattern command is received will be described. When the change pattern command is received and the update condition of the game performance data is satisfied, the read access is started from the read address indicated by the read pointer PT1 for the ferroelectric memory FeRAM of the payout control unit 24. Until the EOF data is acquired, the specified value FFH is repeatedly acquired as the winning ball performance data (ST62). In this acquisition operation, the Listen (b) pulse output process, the response (b) signal level determination process acquired thereafter, and the reception preparation process (RT17 to RT18) shown in FIG. Preceded.

  Further, the Read operation (the process of acquiring the specified value FFH) is specifically executed in the same manner as in FIG. 13E, but in the process of step ST62, the total of the acquired specified values FFH (prize ball performance data) ) Is temporarily saved in an appropriate work area. Then, after the reception end process shown in FIG. 13 (f) is executed, the value of the read pointer PT1 is increased and updated corresponding to the number of acquisitions of the specified value FFH (ST63).

  Next, the real-time clock RTC is accessed, and the current date and time are acquired. At the time of this access, the Busy flag of the real-time clock RTC is determined, and time information after the real-time clock RTC finishes the time update process is acquired. Then, the acquired time information and the total value of the prize ball performance data are associated with each other and stored in the storage position of the game management list TBL1 (ferroelectric memory 38) indicated by the writing pointer PT2.

  Thereafter, the write pointer PT2 is updated, and the values of the write pointer PT2 and the read pointer PT1 are stored in the corresponding area of the ferroelectric memory 38 (effect control unit 22) (ST64). This storage operation is the same as a normal write operation to the SRAM, and a procedure as in the case of accessing the ferroelectric memory FeRAM of the payout control unit 24 is not necessary.

  FIG. 14B is a drawing illustrating an example of the game management list TBL1 arranged in the ferroelectric memory 38 of the production control unit 22, from the middle of business on a certain business day (○ year ○ month ○ day) to the end of business. The prize ball performance data is shown. In this example, the number of payouts from the middle of business until receiving a variation pattern command per uncertain variation is Δ (first description column). After that, the change pattern command of the losing state is received 10 times continuously, but the first five payouts are ○, and the next five payouts are ● (described in the second to third descriptions). Column).

  Next, the number of payouts until the variation pattern command per probability change is received is □, and the number of payouts after receiving the variation pattern command in the lost state is Δ (columns 4-5). After that, as shown in the sixth column, after receiving a variation pattern command per probability variation (number of payouts ■), after the possibility of receiving the variation pattern command of the loss state less than 5 times, the variation pattern per non-probability variation The command is received (sixth column: number of payouts ▽). After that, the final number of payouts is 137 including the possibility that the change pattern command in the lost state is received less than 5 times.

  This game management list TBL1 is arranged in the ferroelectric memory 38 of the effect control unit 22 and can permanently store the above-mentioned stored data, so that not only a transition of the number of prize balls paid out but also a big hit state. It is possible to store and save the number of times, the number of times of probability variation and non-accuracy variation, the number of consecutive chunks, etc. beyond the business day.

  In this gaming machine, when a probable hit state is reached, the winning probability of the subsequent big hit lottery rises and the electric tulip is opened for a long time called `` electric chew support ''. The game state of the chew support is terminated when a variation pattern command per uncertain variation is received. In general, a player calls this electric chew support period as a continuous chain or the like, but according to the present embodiment, the number of payouts in the continuous channel period can be accurately stored. For example, in the case of FIG. 14B, the number of payouts from receiving the variation pattern command per probability variation until receiving the variation pattern command per non-probability variation is Δ + ■ + ▽.

  In the present embodiment, the above-mentioned information useful for the player is stored in the ferroelectric memory 38 of the effect control unit 22 for a long period of time, so that it is possible to statistically grasp the gaming state of the gaming machine. it can. The total interrupt process shown in FIG. 13B is a process for that purpose. For example, at 21:50 every Friday, an appropriate total process is executed based on the interrupt signal IRQ received from the real time clock RTC ( ST60).

  In this tabulation process, not only statistical processing based on the game management list TBL1 of FIG. 14B but also tabulation processing based on the error management list TBL2 of FIG. 14C is executed. The statistical processing is executed by accessing the ferroelectric memory 38 (the production control unit 22). However, since it can be randomly accessed in the same procedure as a normal SRAM, no matter how complicated and advanced statistical processing is executed, Therefore, the processing time is not prolonged, and other control operations of the effect control unit 22 are not adversely affected. Further, even if the total interruption process is started immediately before the end of business, the necessary statistical processing can be surely completed by the end of business.

  As described above, in the present embodiment, since the non-volatile memory that can be randomly accessed is arranged in the payout control unit and the effect control unit, the game performance can be stored and held for a long period of time.

  Although the embodiments have been described in detail above, the specific description does not particularly limit the present invention. For example, in the embodiment, a ferroelectric memory (Ferroelectric Random Access Memory) is used as a non-volatile memory that can be randomly accessed. However, the present invention is not limited at all. For example, a magnetoresistive memory (Magnetoresistive RAM) may be used. Is preferred.

  In addition, an element that operates according to an SPI (Serial Peripheral Interface) method is arranged in the payout control unit 24, and an element that operates in an access procedure equivalent to that of a normal SRAM is arranged in the effect control unit 22, but there is no limitation. That is, a configuration may be adopted in which a non-volatile memory that operates according to an access procedure equivalent to that of a normal SRAM is arranged in the payout control unit 24, and the storage content is acquired by the effect control unit 22 when necessary.

  If the production control unit 22 adopts a configuration in which the non-volatile memory arranged in the payout control unit 24 is directly read-accessed, an additional address bus is required. In response to the request signal (preferably a 1-bit signal), it is preferable that the payout control unit 24 reads the contents of the nonvolatile memory and serially transmits it to the effect control unit 22.

  In the embodiment, the error notification command is transmitted in parallel from the main control unit 21 to the effect control unit 22, but it is also preferable to serially transmit the error notification command. In this case, if a non-volatile memory that operates in the SPI method is arranged in the effect control unit 22, the main control unit can directly perform write access to the non-volatile memory.

  In addition, in the case where the same memory element is accessed by a plurality of CPUs including such a case, it is necessary to prevent a simultaneous access collision from different CPUs, and an access control circuit similar to FIG. 4 is required. Become. However, in the circuit configuration as shown in FIG. 4, it is not essential to supply the CLR pulse from the CPU. Rather, the CLR pulse is generated by a one-shot multivibrator that functions in synchronization with the rising edge of the chip select signal CS bar. It is preferable to generate automatically.

  In the above embodiment, a pachinko machine has been described. However, the application of the present invention is not limited to a ball game machine, and it is also suitable to be applied to a spinning machine (slot machine). For example, in the case of a slot machine divided into a main control unit and a sub-control unit, if a non-volatile memory capable of random access is arranged in one or both, the main control can be performed without complicating the device configuration. The game performance can be permanently stored in the department and / or the sub-control part.

  Examples of information for identifying the game results include (1) history information on the number of medals earned by the player (= the number of paid-out medals−the number of consumed medals), and (2) a big hit game (bonus called “big bonus” or “regular bonus”). History information regarding (game), (3) history information regarding player support including AT (assist time) and ART (assist replay time), and (4) history information regarding pseudo bonus. It should be noted that the gaming machine provided with the “latent mode” as a gaming state that affects the winning probability of the pseudo bonus includes history information relating to such a gaming state. If the sub-control unit executes AT / ART / pseudo-bonus winning lottery, the sub-control unit can grasp all the above-mentioned game results, and the sub-control unit has no legal restrictions on the memory capacity. It can be stored permanently.

  In each of the above embodiments, a non-volatile memory is exclusively used. However, the present invention is not necessarily limited to such a configuration. That is, for example, when the real-time clock RTC as shown in FIG. 8B is mounted in the main control unit or the sub-control unit, an SRAM (Static RAM) driven by the power supply voltage supplied to the real-time clock RTC is used. You may memorize | store in the historical information regarding a game. Although the use of DRAM (Dynamic RAM) is not prohibited, SRAM can significantly reduce the power consumption in the memory holding state as compared with DRAM, so it is necessary to use SRAM in combination with real-time clock RTC. Is preferred.

  In any case, it is preferable that the history information backed up in the volatile memory is appropriately tabulated based on the interrupt signal IRQ periodically (for example, a predetermined time on a predetermined day of the week) received from the real-time clock RTC. (Refer to ST60).

GM gaming machine 21 Other control means ST62 First means ST64 Second means FeRAM Nonvolatile memory

Claims (4)

A gaming machine provided with an effect control means for executing an effect operation based on a control command received from another control means,
The production control means includes
A first means that is activated by receiving a predetermined control command, and acquires game information related to a gaming result of the gaming machine on an acquisition path different from the transmission path of the control command;
A second means for storing the game information acquired by the first means in a non-volatile manner in the game result memory as history information to which clock information from the time measuring means is added ,
A gaming machine, wherein the history information is configured to be notified to a player when necessary .   The gaming machine according to claim 1, wherein the acquisition path is a serial communication path. The gaming machine according to claim 1 or 2, wherein the gaming result memory is a nonvolatile memory that functions with a single power source.   The gaming machine according to claim 1 or 2, wherein the history information is stored in a non-volatile manner by driving the gaming result memory with the same power supply voltage as that of the electronic element that realizes the time measuring means.

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