JPH0799258A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the dispersion of the characteristics of an element caused by the formation of the boundary of two single-crystal semiconductor films grown in a solid phase in element active regions. CONSTITUTION:This is the method for forming a single-crystal semiconductor film. A plurality of seed parts 1 are formed so that element active regions 2 are not present at the positions separated by the equal distance from the neighboring two seed parts 1. The amorphous semiconductor film is converted into the single-crystal semiconductor film by the solid-phase growth from the seed parts 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a semiconductor film formed by solid phase growth.

[0002]

2. Description of the Related Art In recent years, semiconductor memory devices such as EEPROMs have been developed as memory devices. Since the semiconductor memory device does not have a mechanical driving part, it has an advantage that it is resistant to impact and can be accessed at high speed.

In the case of EEPROM, polycrystalline silicon is usually used as the material of the floating gate electrode. However, due to the grain boundaries existing in the polycrystalline silicon, variations in electrical characteristics such as threshold voltage between elements and deterioration of insulation characteristics of the gate insulating film, tunnel insulating film, or insulating film on the floating gate electrode may occur. It's a problem.

In order to solve such a problem, an amorphous semiconductor film is crystal-grown with a seed portion formed on the surface of a single crystal semiconductor substrate as a nucleus, and then an amorphous semiconductor film is grown by solid phase growth by annealing. There has been proposed a technique of replacing the single crystal semiconductor film with a single crystal semiconductor film and using this as a gate electrode (Japanese Patent Laid-Open No. 3-173120).

In this type of single crystal technique, since only one single crystal semiconductor film having an area of about 200 μm ² is formed from one seed portion, it is necessary to form a large number of seed portions on the same substrate. As a result, with a certain probability, the boundary between the two single crystal semiconductor films solid-phase grown from the adjacent seed portion is formed in the element active region.

An element having the above-mentioned boundary in the element active region exhibits electric characteristics different from those of other elements, so that the element characteristics vary. Further, since the seed portion is connected to the element active region through the element isolation region, the crystallinity changes at the uneven portion of the element isolation region during solid phase growth.

Therefore, it is difficult to obtain a high quality single crystal semiconductor film in the entire element active region. Further, the seed portion needs to be provided in a region different from the device active region and the device isolation region, which is disadvantageous for high integration of the device.

[0008]

As described above, after the amorphous semiconductor film is crystal-grown with the seed portion as a nucleus, the amorphous semiconductor film is converted into a single crystal semiconductor film by solid phase growth. In the crystal technique, a boundary between two single crystal semiconductor films solid-phase-grown from adjacent seed portions is formed in the element active region with a probability.

Therefore, there is a problem that an element having the above-mentioned boundary in the element active region exhibits electric characteristics different from those of other elements and the element characteristics vary. The present invention has been made in consideration of the above circumstances, and an object thereof is to prevent variations in device characteristics due to formation of a boundary between two solid-phase-grown single crystal semiconductor films in a device active region. It is to provide a method of manufacturing a semiconductor device that can be manufactured.

[0010]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention (claim 1) comprises:
Forming an insulating film having a plurality of openings on the single crystal semiconductor substrate; forming an amorphous semiconductor film on the plurality of openings and the insulating film; and heat treating the amorphous semiconductor film. By solid phase growth to form a single crystal semiconductor film, and by patterning the single crystal semiconductor film, a region other than a position equidistant from the two closest openings of the plurality of openings, And arranging the element parts in a direction substantially perpendicular to the direction connecting the two closest openings.

Another method of manufacturing a semiconductor device according to the present invention (claim 2) is a step of forming an insulating film having a plurality of openings on a single crystal semiconductor substrate, the plurality of openings and the insulating film. Forming an amorphous semiconductor film on the film, and removing the region of the amorphous semiconductor film including a position equidistant from the two closest openings of the plurality of openings, Forming a groove along a direction substantially perpendicular to a direction connecting two adjacent openings; forming a single crystal semiconductor film by solid phase growing the amorphous semiconductor film by heat treatment; and forming the single crystal By patterning the semiconductor film, the element portion is formed in a region substantially equidistant from the two closest openings of the plurality of openings in a region substantially equidistant from the two closest openings. Arrange And having a degree.

[0012]

In general, since the solid phase growth rates from the respective seed parts are almost equal to each other, if there is no element active region at a position equidistant from the two adjacent seed parts as in the present invention, the two adjacent seed parts are not formed. The boundary between the single crystal semiconductor films solid-phase-grown from the portion does not occur in the element active region. Therefore, it is possible to prevent variations in device characteristics due to the boundaries.

Even when the solid phase growth rate from each seed portion is different or the seed portion and the device active region are separated from each other, as in the present invention (claim 2), two adjacent device active regions are provided. By removing at least a part of the amorphous semiconductor film existing between the two, it is possible to prevent the boundary between the single crystal semiconductor films from being formed in the element active region prior to the removed portion, and prevent variations in element characteristics.

[0014]

Embodiments will be described below with reference to the drawings. 1 and 2 are plan views for explaining the basic concept of the present invention. In FIG. 1A, reference numeral 1 denotes a seed portion, and a region 3 where an element active region is to be formed (hereinafter simply referred to as an element active region) 2 is provided at a position 3 equidistant from two adjacent seed portions 1. Each seed part 1 is arranged so that it does not exist.

Therefore, since the solid phase growth rates from the seed portions 1 are usually almost equal, the boundary between the single crystal semiconductor films solid-phase grown from the adjacent seed portions 1 is the element active region 2.
Never formed.

As described above, the solid-phase growth rates from the seed portions are usually almost equal, but the difference in the interface state between the seed portion and the amorphous semiconductor film and the interface between the base insulating film and the amorphous semiconductor film. The solid phase growth rate from each seed portion may be different due to the non-uniformity of the state, the non-uniformity of the amount of impurities in the amorphous semiconductor film, and the like.

In particular, as shown in FIG. 1B, when the element active region group 4 is long, the boundary 5 between the single crystal semiconductor films solid-phase-grown from two adjacent seed portions 1 is the element active region group 4. May be formed in.

In this case, as shown in FIG.
After removing the portion 6 of the amorphous semiconductor film deposited on the insulating film, which includes the position 3 equidistant from two adjacent seed portions 1, the amorphous semiconductor film is crystallized by solid phase growth. Then, as shown in FIG. 2B, the boundary 5 between the single crystal semiconductor films can be prevented from being formed in the element active region group 4. At this time, the removal region 6 preferably includes a region sandwiched between a boundary 7 of the seed portion 1 on the element active region group 4 side and a boundary 8 of the element active region group 4 on the opposite side of the seed portion 1. .

For high integration, it is preferable not to provide a special region for the seed portion. For example, when the present invention is applied to an EEPROM cell, the seed portion is a source layer, a drain layer on the single crystal semiconductor substrate, or at least a part of a region where a contact portion between the single crystal semiconductor substrate and the bit line is to be formed, Alternatively, if it is provided in at least a part of the region where the embedded element isolation portion of the single crystal semiconductor substrate is to be formed, these regions have no influence on the solid-phase growth of the amorphous semiconductor film, so that the degree of integration is reduced. It can be prevented.

Next, an embodiment in which the present invention is applied to a floating gate of a NAND type EEPROM will be described. First, as shown in FIG. 3, an element isolation oxide film (element isolation region) 12 having a thickness of 700 nm is formed on a p-type single crystal silicon substrate 11 by a thermal oxidation method. Then, after forming a gate oxide film 13 having a thickness of 10 nm by using a thermal oxidation method, a first amorphous silicon film 14 having a thickness of 50 nm is formed on the entire surface by an LPCVD method using a raw material such as silane or disilane. To do.

Next, as shown in FIG. 4, a photoresist 15a is applied on the first amorphous silicon film 14, and then the p-type single crystal silicon substrate 11 and the bit line are included in the photoresist 15a. A part of the region where the contact portion is to be formed is removed. Then, using the remaining photoresist 15a as a mask, the first amorphous silicon film 14 and the gate oxide film 13 are dry-etched to form a seed portion 16. Here, two adjacent seed parts 1
A position equidistant from 6 is a region where the element isolation region 12 or the diffusion layer is to be formed, and there is no device active region. In addition, since the native oxide film 17 is formed on the substrate surface of the seed portion 16 in the above process, the photoresist 15a
Then, the natural oxide film 17 is removed by exposing the p-type single crystal silicon substrate 11 to hydrogen fluoride gas.

Next, as shown in FIG. 5, a second amorphous silicon film 18 having a thickness of 100 nm is formed on the first amorphous silicon film 14 and the seed portion 16 by LPCVD by using silane or disilane. Etc. are formed by thermal decomposition.

Next, as shown in FIG. 6, a photoresist 15b is applied on the second amorphous silicon film 18, and two adjacent seed portions 1 of the photoresist 15b are applied.
A part on the element isolation region 12 including a position equidistant from 6 is removed. Then, using the remaining photoresist 15b as a mask, the second and first amorphous silicon films 18 and 1 are formed.
A removal region 19 is provided in the amorphous silicon films 14 and 18 by sequentially performing dry etching on the amorphous silicon films 14 and 18.

Next, as shown in FIG.
After removing 5b, an annealing treatment at a low temperature of about 500 to 550 ° C. is performed in a nitrogen or argon gas atmosphere, and the first and second amorphous silicon films 14 are formed by solid phase epitaxial growth from the seed portion 16. 18
The single crystal silicon film 20 is used.

At this time, as described above, the element active region does not exist at the position equidistant from the two adjacent seed portions 16, and further, the position equidistant from the two adjacent seed portions 16 is included. Since the removal region 19 exists in a part of the element isolation region, as shown in FIG. 11, the boundary 33 between the single crystal silicon films solid-phase grown from the two adjacent seed portions 16 is the element isolation region. 12 or the diffusion layer formation planned region 32, and is not formed in the element active region.

Next, as shown in FIG. 8, phosphorus or arsenic is diffused in the single crystal silicon film 20, and then the crystalline silicon film 2 is formed.
An insulating film 21 made of a silicon oxide film and a silicon nitride film and having a thickness of 20 nm is formed on the insulating film 21. The silicon oxide film and the silicon nitride film are formed, for example, by a thermal oxidation method, L
It is formed by the PCVD method. Then, a polycrystalline silicon film 22 having a thickness of 20 nm is formed on the insulating film 21, and then phosphorus or arsenic is diffused into the polycrystalline silicon film 22.

Next, as shown in FIG. 9, the polycrystalline silicon film 22, the insulating film 21, and the single crystal silicon film 20 are selectively etched into a gate electrode shape, and the word line 34 of the memory cell portion 23 and the word of the selection gate 24 are selected. Form line 35. Here, the single crystal silicon film 20 of the memory cell portion 23
Serves as a floating gate, and the polycrystalline silicon film 22 serves as a control gate.

Next, as shown in FIG. 10, the p-type single crystal silicon substrate 11 is formed by using the gate portion composed of the polycrystalline silicon film 22, the insulating film 21 and the single crystal silicon 20 as a mask.
An n-type diffusion layer 25 is formed by ion-implanting arsenic into. Next, after depositing the interlayer insulating film 26 on the entire surface,
Interlayer insulating film 26 including the region used as the seed portion 16
By etching away a part of the p-type single crystal silicon substrate 1
A contact portion 27 between 1 and the bit line is formed.

As described above, in this embodiment, since the seed portion 16 is formed in the region to be the contact portion 27, it is not necessary to provide a special seed region as in the case of the conventional method, and therefore, the device integration There is no problem of diminishing degrees.

The p-type single crystal silicon substrate 11 of the seed portion 16 is used as the gate oxide film 1 for forming the seed portion 16.
The etching process of 3 and the etching process of the interlayer insulating film 26 for forming the contact portion 27 are performed twice. FIG. 15A shows a sectional view when the opening portion when forming the seed portion 16 is larger than the opening diameter when forming the contact portion 27, and FIG. As shown in FIG. 15A or 15B, the seed portion 1
The surface of the p-type single crystal silicon substrate 11 of 6 has a step in the depth direction.

Finally, an Al wiring 28 to be a bit line and a passivation film 29 are formed to complete an EEPROM cell. When all the devices formed on the substrate according to the method of this example were examined, it was confirmed that no grain boundary existed in the floating gate electrode on the device active region. In addition, it was possible to completely suppress variations in electrical characteristics between devices due to grain boundaries, and also to completely suppress deterioration in reliability of the insulating film on the floating gate electrode due to grain boundaries.

Thus, according to the present embodiment, the amorphous silicon film forming all the floating gate electrodes of the EEPROM cell can be completely made into a single crystal without lowering the integration degree of the elements, and the electrical characteristics of the elements can be improved. Variation can be completely suppressed.

By the way, in the case of a normal EEPROM cell, as shown in FIG. 12, a step is formed on the surface of the gate oxide film 13 under the amorphous silicon film 14. This is because the film thickness of the tunnel oxide film and the film thickness of the gate oxide film of the select gate transistor are different.

When the amorphous silicon films 14 and 18 thus deposited on the stepped gate oxide film 13 are solid-phase grown, the stepped portion becomes a new crystallization nucleus and a desired single crystal silicon film is formed. May not be formed.

To prevent this, for example, the thickness t of the amorphous silicon films 14 and 18 is set to the step d of the gate oxide film 13.
It is effective to deposit the amorphous silicon films 14 and 18 so as to be 5 times or more.

Further, in the above embodiment, the seed portion 16 is used.
Are formed in a part of the region where the contact portion 27 between the p-type single crystal silicon substrate 11 and the bit line is to be formed. In the step of forming the seed portion 16, the gate oxide film 1 of the seed portion 16 is formed.
3 has been removed. As a result, the surface of the p-type single crystal silicon substrate 11 of the seed portion 16 is etched in the selective etching process of the single crystal silicon film 20 when forming the gate electrode.

Therefore, as shown in FIG. 13A, the junction depth of the n-type diffusion layer 25a of the contact portion 27 becomes deeper than that of the other n-type diffusion layer 25b, and the transistor characteristics of the select gate portion 24 are increased. May deteriorate.

To reduce the amount of etching on the surface of the p-type single crystal silicon substrate 11, for example, as shown in FIG. 13B, the distance L between the end of the seed portion and the end of the select gate electrode is set.
Should be longer than the junction depth x _j of the n-type diffusion layer 25a. Further, making the thickness of the first amorphous silicon film 14 thinner than the thickness of the second amorphous silicon film 18 is also effective in reducing the etching amount.

The present invention is not limited to the above embodiment. For example, in the above embodiment, impurities such as phosphorus and arsenic are diffused in the single crystal silicon film obtained by solid phase growth, but after the impurities are diffused in the amorphous silicon film before solid phase growth, The amorphous silicon film may be changed to a single crystal silicon film by solid phase growth.

The seed portion 16 does not necessarily have to be provided on the p-type single crystal silicon substrate 11, but may be provided, for example, in an amorphous silicon film deposited on an insulating film. That is, by locally changing the impurity concentration in the amorphous silicon film, a region having a high crystallization rate can be provided, and solid-phase growth can be performed using this region as a nucleus.

Further, in the above embodiment, the case of the floating gate electrode of the EEPROM cell is explained, but the present invention can be applied to the gate electrode of the MOS transistor.

Furthermore, the present invention can be applied to a semiconductor device in which a buried element isolation portion is formed after element formation. For example, when it is applied to an EEPROM cell as in the above-described embodiment, as shown in FIG. 14, a seed part 43 is planned to form a buried element isolation region that divides a region 44 to be a element active region to be formed on a semiconductor substrate. It can also be provided in at least a part of the region 41. In addition, if the decrease in the degree of integration of the device does not pose a problem, a region for the seed portion 43 may be specially provided.

In FIG. 14, reference numeral 42 is a region where a diffusion layer is to be formed, and 45 is a contact portion between the substrate 1 and the bit line. In addition, various modifications can be made without departing from the scope of the present invention.

[0044]

As described above in detail, according to the present invention, it is possible to prevent a boundary between single crystal semiconductor films solid-phase-grown from two adjacent seed portions from being generated in the element active region, and to disperse the element characteristics. Can be made smaller.

[Brief description of drawings]

FIG. 1 is a plan view for explaining the basic concept of the present invention.

FIG. 2 is a plan view for explaining the basic concept of the present invention.

FIG. 3 is a NAND type EEPROM according to an embodiment of the present invention.
Drawing for demonstrating the manufacturing method of M

FIG. 4 is a NAND type EEPROM according to an embodiment of the present invention.
Drawing for demonstrating the manufacturing method of M

FIG. 5 is a NAND type EEPROM according to an embodiment of the present invention.
Drawing for demonstrating the manufacturing method of M

FIG. 6 is a NAND-type EEPRO according to an embodiment of the present invention.
Drawing for demonstrating the manufacturing method of M

FIG. 7 is a NAND type EEPROM according to an embodiment of the present invention.
Drawing for demonstrating the manufacturing method of M

FIG. 8 is a NAND-type EEPROM according to an embodiment of the present invention.
Drawing for demonstrating the manufacturing method of M

FIG. 9 is a NAND-type EEPROM according to an embodiment of the present invention.
Drawing for demonstrating the manufacturing method of M

FIG. 10 is a NAND-type EEPR according to an embodiment of the present invention.
Diagram for explaining the method of manufacturing the OM

FIG. 11 is a top view showing a position of a boundary between single crystal silicon films.

FIG. 12 is a cross-sectional view for explaining a method for solving a problem that may occur when solid-phase growing a first amorphous silicon film on a stepped gate oxide film.

FIG. 13 is a cross-sectional view illustrating a method for solving a problem that may occur during selective etching of a single crystal silicon film when forming a gate electrode.

FIG. 14 is a top view for explaining an example in which the present invention is applied to embedded element isolation.

FIG. 15 is a cross-sectional view showing a surface shape of a p-type single crystal silicon substrate of a seed portion.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Seed part 2 ... Element active region 3 ... Position equidistant from a seed part 4 ... Element active region group 5 ... Boundary between single crystal semiconductor films 6 ... Part including a position equidistant from a seed part 7 ... Seed part Of the element active region group side 8 ... Boundary of the element active region group side opposite to the seed portion 11 ... P-type single crystal silicon substrate 12 ... Element isolation oxide film (element isolation region) 13 ... Gate oxide film 14 ... first amorphous silicon film 15a, 15b ... photoresist 16 ... seed part 17 ... natural oxide film 18 ... second amorphous silicon film 19 ... removal region 20 ... single crystal silicon film 21 ... insulating film 22 ... Polycrystalline silicon film 23 ... Memory cell part 24 ... Select gate part 25 ... N-type diffusion layer 26 ... Interlayer insulating film 27 ... Contact part 28 ... Al wiring (bit line) 29 ... Passivation film 32 ... Diffusion layer formation Constant region 33 ... Boundary between single crystal silicon films 34 ... Word line of memory cell part 35 ... Word line of select gate part 41 ... Area to form element isolation region 42 ... Area to form diffusion layer 43 ... Seed part 44 ... Area where element active area is to be formed 45 ... Contact portion

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/20 8122-4M 27/115

Claims (2)

[Claims] 1. A step of forming an insulating film having a plurality of openings on a single crystal semiconductor substrate; a step of forming an amorphous semiconductor film on the plurality of openings and the insulating film; A step of forming a single crystal semiconductor film by solid phase growth of an amorphous semiconductor film; and patterning the single crystal semiconductor film so that a position equidistant from two closest openings of the plurality of openings. And a step of arranging the element parts in a region substantially other than the direction perpendicular to the direction in which the two closest openings are connected to each other. 2. A step of forming an insulating film having a plurality of openings on a single crystal semiconductor substrate; a step of forming an amorphous semiconductor film on the plurality of openings and the insulating film; By removing a region of the amorphous semiconductor film including a position equidistant from the two closest openings among the openings, a groove portion is formed along a direction substantially perpendicular to a direction connecting the two closest openings. A step of forming a single crystal semiconductor film by solid phase growing the amorphous semiconductor film by heat treatment, and patterning the single crystal semiconductor film so that the plurality of openings are closest to each other. A method of manufacturing a semiconductor device, comprising: arranging element parts in regions other than positions equidistant from the two openings in a direction substantially perpendicular to a direction connecting the two closest openings.