JPH0795676B2 - Clock pulse generation circuit with duty adjustment circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock pulse generation circuit, and more particularly to a clock pulse generation circuit equipped with a circuit for adjusting the duty of a pulse and suitable for incorporating a data processing device.

[Background of the Invention]

A clock pulse generation circuit that is indispensable for controlling a digital device such as a data processing device is a typical circuit that requires the duty of a generated pulse to have a specified value. A typical configuration of a conventional clock pulse generation circuit is as shown in FIG. 3 (Hiroyuki Watanabe "Computer Design Technology [1]", CQ Publishing Company, 1973, 156-1).
(See page 58). The pulse oscillator 1 is composed of, for example, a crystal oscillator and an astable multivibrator driven by its output. As shown in FIG. 4, its output (4f) is frequency-divided by a flip-flop 2 to produce a duty (1 A pulse (2f) with 50% of the "high" level period to period)
Becomes Generally, it is difficult to obtain a pulse with a duty of 50% as an output of an oscillator such as an astable multivibrator in a high frequency region, and therefore the flip-flop 2 is placed. The output of flip-flop 2 is
Further, it is given to a flip-flop group (for example, a ring counter) 3, transformed into multi-phase clock pulses φ1, φ2, ▲ ▼, ▲ ▼ having a half frequency, and given to a controlled device (for example, a computer) 4. Each phase of this multiphase clock pulse has a duty of 50% and a phase difference of 1/4 period from each other, and its frequency is that of the pulse oscillator 1.
It is 1/4.

The disadvantage of this type of circuit is that it requires a pulse oscillator with a frequency four times the required clock frequency. In other words, the controlled device cannot operate at frequencies above 1/4 of the pulse oscillator. Therefore, if the pulse oscillator and the controlled device are composed of elements having the same upper limit frequency, the controlled device must settle for a speed that is 1/4 of the originally possible speed. Further, regarding such a high frequency signal, special consideration should be given to the influence of parasitic capacitance and the like, and further, it may induce noise inside the controlled device and cause a malfunction. is there.

Especially in a large scale integrated circuit, these problems have a great influence.

[Object of the Invention]

An object of the present invention is to provide a circuit that adjusts the duty of a pulse to a desired value without going through a frequency division operation, thereby eliminating the above problems associated with the presence of a high frequency pulse source in a clock pulse generation circuit. There is a solution.

[Outline of Invention]

The duty adjusting circuit according to the present invention has one of the rising edge and the falling edge of the input pulse in each of two stages which are complementary with respect to the phase of the signal (that is, opposite phases to each other, or a logical positive and negative relationship). A delay circuit for performing delay control for only the delay circuit and a control circuit for generating a voltage for controlling the time constant of each delay circuit. In this control circuit, the capacitor that generates the time constant control voltage is connected to the charging current source and the discharging current source via the switching circuit that operates according to the control signal, and the ratio of the characteristic currents of these current sources is It is set to a value corresponding to the predetermined duty that the final output pulse should have.

The switching circuit in each control circuit may be operated according to the level of the output pulse of the delay circuit which it controls,
Alternatively, the operation may be performed according to the logical combination of the input pulse of the first delay circuit and the output pulse of the second delay circuit.

Example of Invention

FIG. 1 shows a circuit for a preliminary explanation of the invention. The input pulse f _i drives the CMOS inverter 5, and the output of this inverter 5 is delayed by the delay circuit 6. The output of the delay circuit 6 passes through the CMOS inverter 7 again, the delay circuit 8, and becomes an output pulse f ₀ . The delay circuits 6 and 8 have the same structure and are composed of an N-channel MOS transistor T _r acting as a variable resistance and a capacitor C, and the time constant of T _r and C causes the main delay action. The input pulse f _i and the output ′ ₀ of the delay circuit 6 are complementary in terms of phase, that is, in a reverse phase relationship, and since the ′ ₀ and the output pulse f ₀ are also in reverse phase, the output pulse f ₀ is eventually Input pulse
It is in phase with f _i and delayed by the sum of the delay amounts of the delay circuits 6 and 8. One of the basic features of the present invention is that the two delay circuits are provided in the stages complementary with respect to the phase of the signal.

The use of delay circuits for the manipulation of pulses is well known per se, and delay circuits of the type mentioned above are also integrated because the delay time can be adjusted by controlling the gate voltage of their T _r . It is often used in circuits (see, for example, JP-A-58-191522). However, such a delay circuit, as shown in FIG. 2, the delay time t ₁ between the rising edge and the falling edge of the output pulse _"0 corresponding to that of the input pulse f _i, falling of f _i The problem is that the delay time t ₂ between an edge and the corresponding rising edge of ' ₀ is generally not equal (ie, the input and output have different duties). One of the causes of this phenomenon is that it is difficult to completely match the ON resistances of the P-channel MOS transistor and the N-channel MOS transistor forming the CMOS inverter 5 in the integrated circuit manufacturing technology. There is a difference in the resistance of the charging path and the discharging path.

Another cause is the nature of the MOS transistor T _r used as a resistor. That is, the source-drain resistance R _DS of the MOS transistor changes depending on the gate-source voltage V _GS , and in particular, when V _GS decreases and approaches the threshold value, R _DS rapidly increases. On the other hand, in the MOS transistor T _r which is an element of the delay circuit 6, the capacitor C
The electrode connected to acts as the source during either charging or discharging. In that case (in FIG. 1, when the output of the inverter 5 is at a high potential), V _GS gradually decreases as charging or discharging progresses, and thus R _DS gradually increases, so that the charging or discharging speed is increased. descend. This result appears as a delay time extension. But,
Such a phenomenon does not occur during the operation period in which the electrode connected to the capacitor C acts as the drain (when the output of the inverter 5 is low potential in FIG. 1). This causes a delay imbalance with respect to the rising and falling edges of the input pulse.

However, in the circuit shown in FIG. 1, by arranging the delay circuits in the two stages complementary with respect to the phase of the signal, the above-mentioned phenomenon is canceled and the delay times for the rising edge and the falling edge become the same. That is, the waveforms' ₀ and f in FIG.
_As shown in ₀ , since the second stage circuits 7 and 8 receive the pulse ′ ₀ having a phase opposite to that of f _i , the rising edge of f ₀ is t ₂ with respect to the falling edge of ′ ₀ . Be delayed and then ′ ₀
The trailing edge of f ₀ is delayed by t ₁ with respect to the leading edge of. As a result, the final output f ₀ has a delay of t ₁ + t _{2 on} both the rising edge and the falling edge with respect to the input f _i , and eventually the phase is different in the same duty.

By using a pair of delay circuits as described above, it is possible to obtain an output pulse of the same duty having a predetermined phase relationship (for example, 1/4 cycle delay) with the input pulse. In FIG. 1, the control circuit 9 receives the input pulse f _i and the output pulse f ₀ , detects the phase difference between them, and controls the gate voltage of the MOS transistors T _r of the delay circuits 6 and 8 according to the value. By doing so, the resistance values are changed to adjust the delay characteristics.

The present invention is different from this, in which the delay adjustment is performed by controlling only the delay time of either the rising edge or the falling edge in both delay circuits arranged at the above positions. .

FIG. 5 shows a duty adjusting circuit which is an embodiment of the present invention. This circuit receives an input pulse f _i having an arbitrary duty and generates an output pulse f ₀ of the same frequency having a predetermined duty (for example, 50%), and is arranged in stages complementary in phase. Pulse width adjustment circuit 1
3, 15 and control circuits 14, 16 for each of them. 17 to 20 are inverters. Since the circuits 13 and 15 and the circuits 14 and 16 have the same structure, respectively,
The illustration of the internal structure of 15 and 16 is omitted. However, the circuit
The symbols (a) to (d) in 13 and 14 and circuits 15 and 16 are
Points on the circuit corresponding to each other are shown.

The pulse width adjusting circuit 13 is a circuit that delays only the rising edge of the input pulse f _i , and its delay time is the control voltage.
It can be adjusted by V _G. The input pulse f _i is applied to the P-channel MOS transistor 21 and the N-channel MOS transistor 23.
Given to a CMOS inverter consisting of. P Channel MO
The drain of the S-transistor 21 is directly connected to the capacitor C _1, and the drain of the N-channel MOS transistor 23 is
It is connected to the capacitor C ₁ through the source / drain circuit of the N-channel MOS transistor 22 acting as a resistor. Source of N-channel MOS transistor 22
The drain resistance is controlled by a control voltage V _G applied to the gate of the control circuit 14 to adjust the delay time. The output ′ _{0 of the} circuit 13 is inverted by the inverter 17 to become f ′ ₀ , and this f ′ ₀ becomes the input of the control circuit 14 and, via the inverter 18, the pulse width adjusting circuit 15 of the next stage.
Becomes the input _i . The output f ″ ₀ of the pulse width adjusting circuit 15 in the next stage is inverted by the inverter 19 to become ₀ , and this ₀ becomes the input of the control circuit 16 and the inverter 2
It is inverted again at ₀ and becomes the final output f ₀ .

FIG. 6 is a waveform diagram for explaining the operation of the circuit of FIG. Referring to FIG. 6 (a), when the input pulse f _i changes from the high level to the low level, the P-channel MOS transistor 21 becomes conductive and the capacitor C ₁ is rapidly charged. Therefore, the delay time between the falling edge of the input pulse f _i and the corresponding falling edge of the output pulse f ′ ₀ of the inverter 17 is extremely small. However, when the input pulse f _i changes from the low level to the high level, the P-channel MOS transistor 21 becomes non-conductive, the N-channel MOS transistor 23 becomes conductive instead, and the charge of the capacitor C ₁ becomes N-channel.
It is discharged through the source / drain resistance of the MOS transistor 22. Therefore, the discharge is performed gently, and as a result, the rising edge of the output pulse f ′ ₀ of the inverter 17 is delayed by t _{1 with} respect to the corresponding rising edge of the input pulse f _i .

The control voltage V _G for adjusting this delay time is
This is the voltage on capacitor C ₂ at 14. Capacitor C
₂ is either charged from the constant current source 24 or discharged to the constant current source 27 through the resistor R having an appropriate value. These constant current sources are realized by utilizing the fact that the source / drain current of a MOS transistor is a function of the gate / source voltage. P-channel MOS transistor 25 and N-channel MOS
The transistor 26 receives the output pulse f ′ ₀ of the inverter 17 and constitutes a switching circuit for alternately connecting the charging constant current source 24 and the discharging constant current source 27 to the capacitor C ₂ . That, f 'during the period in _{which 0} is at the low level, and becomes conductive P-channel MOS transistor 25, to charge the capacitor C ₂ from the constant current source 24, f' during the period in _{which 0} is at the high level, N-channel The MOS transistor 26 becomes conductive, and the capacitor C ₂ is discharged to the constant current source 27. Therefore, the average charge of the capacitor C ₂ , that is, the control voltage V _G has a stronger tendency to decrease as the high level period of f ′ ₀ is longer than the low level period. Then, as the control voltage V _G decreases, the source / drain resistance of the N-channel MOS transistor 22 increases, and as a result, the rising edge delay time t ₁ increases,
High-level period of the output pulse f _'0 is reduced. That is, the pulse width adjusting circuit 13 acts in the high level period of the input pulse f _i , in other words, in the direction of reducing the duty,
The steady state is obtained when the duty output pulse f ′ _{0 in} which the charge amount and the discharge amount of the capacitor C ₂ are balanced in one cycle is obtained. Output pulse f'when the steady state is reached
The duty of ₀ is determined by the characteristic current values of the constant current sources 24 and 27. For example, if both are set to be equal, the duty of f ′ ₀ will be 50%.

However, this circuit 13 acts as a mere inverter for input pulses with a duty less than or equal to the duty obtained in the steady state. For example, as shown in FIG. 6 (b), when a short input pulse f _i of a high level period is applied, the charging period t _cn of the capacitor C ₂ is longer than the discharging period t _Dn , so the control voltage V _G
Gradually increases and finally reaches the power supply voltage of the constant current source 24, and the source / drain resistance of the N-channel MOS transistor 22 becomes sufficiently low. Further, if it has the same Deyutei the output pulse of the input pulse already a steady state, the control voltage V _G is sufficiently high, in a state in which no delay, charging and discharging are balanced. Therefore, in these cases, the delay function for the rising edge of the input pulse is substantially lost,
It's just like an inverter.

The structure and operation of the second-stage pulse width adjusting circuit 15 and its control circuit 16 itself are the same as those of the circuits 13 and 14. However,
The input _i of the circuit 15 is in antiphase with the input f _{i of the} circuit 13. Therefore, the circuit 15 works to increase the duty by delaying only the falling edge of the input pulse f _{i at the} first stage, contrary to the circuit 13.

The overall operation of the circuit of FIG. 5 will be described for the case where the duty of the output pulse f ₀ is adjusted to 50%. In this case, the specific current values of the constant current sources 24 and 27 in both control circuits 14 and 16 are set to the same value. FIG. 6A shows a case where the low level period of the input pulse f _i is extremely shorter than the high level period. In period T ₁ , an output pulse f ′ ₀ is obtained in which the rising edge of the input pulse f _i is delayed by t ₁ . At this time, since the low level period of the output pulse f ′ ₀ , that is, the charging period t _C1 of the capacitor C ₂ is shorter than the high level period, that is, the discharging period t _D1 , the voltage of the capacitor C ₂ in the next cycle T ₂ , that is, Control voltage V _G decreases and delay time
t ₂ becomes larger than t ₁ . This tendency continues until the period T ₄ is entered, and the delay time increases to t ₁ <t ₂ <t ₃ <t _4, and in the period T ₄ , the low level period t _C4 and the high level period of the output pulse f ′ ₀ are increased. t _D4 becomes equal. Here, charging / discharging of the capacitor C ₂ is in equilibrium, the delay time t ₅ in the cycle T ₅ is the same as t _4, and
Thereafter, this state is maintained, the output pulse f _'0 keeps 50% Deyutei.

During this period, the pulse width adjusting circuit 15 of the second stage is
_It receives an inverted signal of ₀ , which has a low level period longer than a high level period. Therefore, this circuit 15 functions as a mere inverter as described above.

On the contrary, FIG. 6B shows the case where the high level period of the input pulse f _i is extremely shorter than the low level period. in this case,
The pulse width adjusting circuit 13 at the first stage functions as a simple inverter as described above. However, the second stage pulse width adjustment circuit
The input _i of 15 corresponds to the input f _i in FIG. 6 (a). Therefore, this circuit 15 increases the delay with respect to the rising edge of the input pulse _i , that is, the falling edge of the input pulse f _i of the first stage, in the same manner as the circuit 13 described with reference to FIG. 6 (a). To the end of the duty
A 50% output pulse f ₀ is generated.

By selecting the ratio of the characteristic current values of the constant current sources 24 and 27 in the control circuits 14 and 16, the duty of the output pulse can be adjusted to a desired value.

FIG. 7 shows another embodiment of the present invention. This circuit can be used for both phase adjustment and duty adjustment, and can be used in place of the frequency divider 2 and flip-flop group 3 in FIG. The circuits 28 and 29 surrounded by the chain line have the same structure, so that the illustration of the latter internal structure is omitted, but the main corresponding points of both circuits are shown by the symbols (e) to (i). . Further, the portions 13 and 15 surrounded by the broken line in both circuits are the same as the pulse width adjusting circuit 13 in FIG. The control circuit portion for generating the control voltage V _G is essentially the same as the control circuit 14 in FIG. 5, except that the constant current sources 30 and 31 are provided in common to the circuits 28 and 29. The only difference is that the P-channel MOS transistor 32 and the N-channel MOS transistor 33 are added for initial setting. However, in this circuit, the signal for controlling the charge / discharge switching transistors 25 and 26 is the input pulse _fφ1 and its inverted signal ▲ ▼.
And a signal ▲ ▼, D _Ch1 , ▲ ▼, representing the phase difference between the output pulse f _φ2 and its inverted signal ▲ ▼.
It is D _Ch2 . The generation of these phase difference signals will be described later. Circuits 34 and 35 each consisting of two stages of inverters
Is inserted as a mere buffer. Inverter
36 and 37 are for obtaining inverted signals of the output pulse f _φ2 and the input pulse f _φ1 respectively.

Prior to the start of the operation, the initial setting pulse f _S is dropped to a low level for an appropriate time, and the P-channel MOS transistor 32 in both the circuits 28 and 29 is turned on to make the N-channel MOS transistor 32 conductive.
The transistor 33 is turned off. As a result, the capacitor C _{2 of} both circuits is sufficiently charged and the control voltage V _G has a high value. Therefore, in this state, circuits 13 and 15
As described with reference to FIG. 5, it functions as a simple inverter and does not exhibit the pulse width adjusting function. Initial setting pulse
When f _S becomes high level, the transistor 32 becomes non-conducting, the transistor 33 becomes conducting, and the capacitor formed by the constant current sources 30 and 31 becomes
C ₂ can be charged and discharged, and the adjustment operation is performed.

When the duty of the input pulse f _φ1 is 50%, the circuit of FIG. 7 basically functions as a phase adjusting circuit. The circuit 28 generates an output pulse _d1 in which only the rising edge of the input pulse f _φ1 is delayed by t _pd1 according to the value of the control voltage V _G , as shown in FIG. 8 (a). Similarly, circuit 29
As shown in FIG. 8 (b), only the rising edge of its input pulse (that is, the output pulse of the circuit 28) _d1 and _{hence the} falling edge of the input pulse f _{φ1 at} the first stage is delayed by t _pd2. Generate an output pulse _φ2 . By the way, since the constant current sources 30 and 31 are common to the circuits 28 and 29, the delay amounts t _pd1 and t _pd2 by both circuits are equal. _Therefore , the output pulse f _φ2 is the same as the input pulse f _φ1 as a whole t _pd1 (=
It is delayed by t _pd2 ), which results in changing the phase.

This delay amount, that is, the phase difference is controlled by controlling the charging / discharging of the capacitor C ₂ according to the phase difference between the input pulse and the output pulse. Therefore, the NAND circuit 38
Receives a _φ2 and f _.phi.1, as shown in FIG. 9, it generates the signal ▲ ▼ indicating the delay time t _f1 rising edge,
As a result, the charge path transistor 25 of the circuit 28 is driven, and the AND circuit 39 receives the signal f _φ2 and f _φ1, and the signal D indicating the time t _f2 from the rise of f _{φ2 to} the fall of f _φ1.
ch1 is generated, which causes discharge path transistor 2 of circuit 28 to
Drive 6 As a result, the circuit 28, like the circuits 13 and 14 in FIG. 5, adjusts the delay time t _f1 with respect to the rising edge of f _φ1 so that the charging and discharging of the capacitor C ₂ are balanced. If the characteristic current values of the constant current sources 30 and 31 are equal, t _f1
= T _f2 , and the rising edge of f _φ1 is delayed by 1/4 period.

On the other hand, the NAND circuit 40 receives f _φ2 and _{φ 1} and generates the signal ▲ ▼ indicating the delay time t _b1 of the falling edge, which drives the charge path transistor of the circuit 29, and AN
The D circuit 41 receives _φ2 and _φ1 and generates a signal D _ch2 indicating the time t _b2 from the rise of _{φ2 to} the fall of _φ1 and thereby drives the discharge path transistor of the circuit 29. As a result, as in the case of the circuit 28, the falling edge of f _φ1 is also delayed by 1/4 period.

As a result, when the constant current sources 30 and 31 have the same intrinsic current value, the output pulse f _φ2 is different from the input pulse f _φ1 .
It has a phase difference of 1/4 cycle. This phase difference is
It can be changed by changing the ratio of the characteristic current values of the constant current sources 30 and 31.

If the outputs of the circuits described above are combined by an appropriate logic circuit, the frequency multiplication function can be easily realized. The NOR circuit 42 and the AND circuit 43 are examples of that.
The former receives D _ch1 and D _ch2 and generates a pulse having a frequency twice that of f _φ1 , and the latter receives ▲ ▼ and ▲ ▼ to generate a pulse having a phase opposite to that of the pulse. In Deyutei 50% of the input pulse f _.phi.1, therewith the output pulse f _.phi.2
If the phase difference is 1/4 cycle, the duty of the multiplied pulse is also 50%.

The circuit of FIG. 7 also functions as a duty adjusting circuit. For example, if the constant current values of the constant current sources 30 and 31 are set to be equal, as is clear from the above description of the phase adjustment operation, t _f1 and t _f2 are equal, and t _b1 and t _b2 are equal, this rising edge of f _.phi.2 occurs at the center of the high-level period of f _.phi.1, and the falling edge of the f _.phi.2 is meant to occur at the center of the low level period of f _.phi.1. It was but connexion, as shown in FIG. 10, regardless of the Deyutei of the input pulse f _.phi.1, high-level period of the output pulse f _.phi.2 is equal to 1/2 period, Deyutei of the output pulse f _.phi.2 50% Becomes

Generally, the ratio of t _f1 to t _{f2 and} the ratio of t _b1 to t _b2 are constant current source 31
Is equal to the ratio of the intrinsic current values of 30 and, therefore, f
the position of the rising edge of f _.phi.2 at high level period of _.phi.1, the position of the falling edge of the f _.phi.2 at low level period of f _.phi.1 are both corresponding to the ratio of the specific current value of the constant current source 30 and 31 . As a result, except when the current of f _φ1 is 50% (in this case, only the phase adjustment is performed as described above), the ratio of the high level period and the low level period of f _φ2 is:
It depends on the ratio of the characteristic current values of the constant current sources 30 and 31.

Similar results can be obtained by using circuits for delaying only the falling edge of the input pulse as the circuits 13 and 15 in the embodiments of FIGS. 5 and 7. Also, it goes without saying that the transistor used may be replaced by another type or type.

〔The invention's effect〕

According to the present invention, the duty can be accurately adjusted to a desired value for a pulse without requiring a frequency dividing operation, and as a result, various clock pulse generating circuits, for example, a clock pulse generating circuit in a data processing device. In, the various problems caused by the existence of the high frequency pulse source can be solved at once, and it is particularly useful when the data processing device is formed as an integrated circuit.

[Brief description of drawings]

1 is a circuit diagram for preliminary explanation of the present invention, FIG. 2 is a waveform diagram of the circuit of FIG. 1, FIG. 3 is a block diagram of a conventional clock pulse generation circuit, and FIG. 4 is FIG. FIG. 5 is a circuit diagram of one embodiment of the present invention, FIG. 6 is a waveform diagram of the circuit of FIG. 5, and FIG. 7 is a circuit diagram of another embodiment of the present invention. Figures 10 through 10 are waveform diagrams for the circuit of Figure 7. 5,7 ... inverter circuit, 6,8 ... delay circuit, 9 ... delay control circuit, 13, 15 ... rising edge delay circuit, 14, 16 ... delay control circuit, C ₂ ... control voltage generating capacitor, 24, 27, 30, 31 ... Constant current source, 25, 26 ... Switching transistor.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takaki Noguchi 1-280 Higashi Koigakubo, Kokubunji, Tokyo Inside Hitachi Central Research Laboratory (72) Inventor Keijiro Shindo 1-280 Higashi Koigakubo, Kokubunji, Tokyo Hitachi, Ltd. Central Research Laboratory (72) Inventor Minoru Ishii 1-280 Higashi Koigakubo, Kokubunji City, Tokyo Hitachi Research Laboratory Central Research Laboratory

Claims (6)

[Claims] 1. A duty adjusting circuit for converting an incoming pulse into a pulse having a predetermined duty at the same frequency as the duty adjusting circuit, the duty adjusting circuit comprising: a first and a second complementary to each other with respect to a phase of a signal. First and second delay circuits that are respectively provided in the stages and perform delay control only for one of the rising edge and the falling edge of the input pulse, and control the delay amounts of the first and second delay circuits, respectively. And a first control circuit, wherein each of the first and second delay circuits has a time constant circuit whose time constant value changes according to an external control voltage. Each of the control circuits is a switching circuit that switches a capacitor for applying the external control voltage, current sources for charging and discharging the capacitor, and connection between the capacitor and the current sources according to a control signal. The a, clock pulses generating circuit ratio of specific current of the charging and discharging current source is set to a value corresponding to the predetermined Deyutei, it is characterized. 2. The method according to claim 1, wherein
The clock pulse generating circuit is characterized in that the control signals for controlling the switching circuits in the first and second control circuits are outputs of the first and second delay circuits, respectively. 3. The method according to claim 1, wherein
The clock pulse generating circuit is characterized in that the control signal for controlling each switching circuit in the second control circuit is a logical combination of the input of the first delay circuit and the output of the second delay circuit. 4. The claim according to any one of claims 1 to 3, wherein the predetermined duty is 50% and the intrinsic currents of the charging and discharging current sources are set to the same value. A clock pulse generation circuit characterized in that 5. A clock pulse generation circuit according to any one of claims 1 to 4, wherein both the P-channel MOS transistor and the N-channel MOS transistor are included as constituent elements. 6. A clock pulse generation circuit for a data processing device according to any one of claims 1 to 5. Description: