JPH1174786A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce time till the operation stabilization of a PLL by providing a logic circuit which receives the output of phase comparator and the output of a flip-flop and operates and adjusting a potential fluctuation speed of a voltage control circuit. SOLUTION: If a leading edge of a source CLK is before the leading edge of a feedback CLK, a Pch (up) signal outputs L from the rise of the source CLK till the leading edge of the feedback CLK. Further, a D type flip-flop is a trailing edge operation of the source CLK and when the Pch (up) signal is L till the trailing edge, a Q output N21P becomes L. When the L output and a Pch (up) signal line are L, a Pch type MOS gate of a 2nd charge pump circuit 2 is turned on and accelerates a voltage increase speed of a voltage control circuit 5. When a PLL becomes a stable operation, an L period of the Pch (up) signal becomes short.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (Phase Locked Loop) control circuit used in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Next, the technical background of the invention will be described with reference to FIGS. FIG. 7 shows a part of a conventional PLL control circuit. In FIG. 7, 1
Is a charge pump generation circuit. The charge pump circuit 1 has four Pch type MOS gates and four Nch type M gates.
It consists of an OS gate. The first Pch-type MOS gate has a source terminal connected to the power supply line, a gate terminal connected to the output terminal of the Pch-side current limiting potential generating circuit, and a drain terminal connected to the second Pch-type.
It is connected to the source of the type MOS gate. The gate terminal of the second Pch type MOS gate is connected to the Pch side output terminal of the phase comparison circuit, and the drain is connected to one end of the voltage control circuit 5. Third Pch type MOS gate and fourth Pch type MOS gate
The connection between the P-channel MOS gates is the same as the connection between the first P-channel MOS gate and the second P-channel MOS gate. The first N-channel MOS gate has a source terminal connected to the ground line, a gate terminal connected to the output terminal of the Nch-side current limiting potential generating circuit, and a drain terminal connected to the second N-channel MOS transistor.
Connected to the source terminal of OS gate. The gate terminal of the second N-channel MOS gate is the output terminal on the N-channel side of the phase comparison circuit, and the drain terminal is the voltage control circuit 5.
To one end. The connection between the third Nch-type MOS gate and the fourth Nch-type MOS gate is the same as the connection between the first Nch-type MOS gate and the second Nch-type MOS gate. The voltage control circuit 5 includes a resistor and a capacitor. One end of the voltage control circuit 5 is connected to one end of a resistor, and the other end is connected to one end of a capacitor. The other end of the capacitor is connected to a ground line. In the example of the conventional circuit, two P-channel MOS gates and four N-channel MOS gates are used.
Although the example of the stage parallel circuit has been described, the number of stages may be arbitrarily connected.

Next, the operation will be described with reference to the waveforms of FIG. Pch side current limiting potential generating circuit and Nch
A first Pch-type MOS gate, a third Pch-type MOS gate,
The amount of source-drain current flowing through the first N-channel MOS gate and the third N-channel MOS gate is limited to a certain amount. The Pch (up) signal line is connected to a source clock (hereinafter, referred to as a source clock).
It becomes “L” from the rising edge of the source CLK to the rising edge of the return clock (hereinafter referred to as the return CLK). Further, the Nch (Down) signal line becomes “H” from the rising edge of the return ring CLK to the rising edge of the source clock. This Pch (u
During the “L” period of p) or the “H” period of Nch (Down), the Pch side of the charge pump circuit 2 and N
The channel side is turned on. By this ON state, the potential of the voltage control circuit NVCO5 rises as shown in FIG.
Or descend.

[0004]

As described above, in the conventional circuit, it is impossible to adjust the amount of potential rise or fall per unit time in the voltage control circuit. However, there is a problem that the size becomes larger.

According to the present invention, by providing a logic circuit for adjusting the potential change speed of the voltage control circuit, it is possible to adjust the potential rise amount or the potential fall amount per unit time in the voltage control circuit. It tries to solve the problem.

[0006]

According to a first aspect of the present invention, a semiconductor integrated circuit compares a signal phase between a source clock and a return clock, and derives an output according to the phase difference. A charge pump circuit that receives an output of the phase comparison circuit and derives an output corresponding to the output of the phase comparison circuit; and receives an output of the charge pump circuit and derives an output of a potential level corresponding to the output of the charge pump circuit. And a voltage control circuit for controlling
An L circuit, comprising: a flip-flop that operates in response to the output of the phase comparison circuit and the source clock; and a logic circuit that operates in response to the output of the phase comparison circuit and the output of the flip-flop. According to another aspect of the present invention, the potential change speed of the voltage control circuit is adjusted by an output of a logic circuit.

In the semiconductor integrated circuit of the second invention,
Receives the source clock and the return clock, and outputs Pc
A phase comparison circuit having h (up) and Nch (Down) signal lines is provided, and a part of a Pch (up) or Nch (Down) signal line connected to a gate electrode of a charge pump circuit constituting a PLL circuit is replaced with a Pch The side is Pc
The h (up) signal line is connected to the D terminal of the D-type flip-flop, the source clock signal line is connected to the falling edge T terminal,
Reset signal line to R terminal, Q terminal output line to 2-input OR
One input terminal of the gate circuit and the other terminal are Pch (up)
The output signal line of the 2-input OR gate circuit is connected to the Pch gate terminal of the charge pump circuit,
On the side, the Nch (Down) signal line is connected to the D terminal of the D-type flip-flop, the return clock signal signal line is connected to the falling edge T terminal, the reset signal line is connected to the S terminal,
The Q terminal output line is connected to one input terminal of a two-input AND gate circuit, the other end is connected to an Nch (Down) signal line, and the output signal line of the two-input AND gate circuit is connected to an Nch gate terminal of a charge pump circuit. It is.

[0008] In the semiconductor integrated circuit of the third invention,
Receives the source clock and the return clock, and outputs Pc
a phase comparison circuit having h (up) and Nch (Down) signal lines, and a part of a Pch (up) or Nch (Down) signal line connected to a gate electrode of a charge pump generation circuit constituting a PLL circuit; On the Pch side,
The Pch (up) signal line is at the falling edge T terminal of the first D-type flip-flop, the power supply line is at the D terminal, the reset signal is at the R terminal, and the Q terminal is one of the first two-input AND gate circuits. An output terminal of the first two-input AND gate circuit is connected to one input terminal of the two-input OR gate circuit, and a Pch (up) signal line is connected to the other input terminal of the two-input OR gate circuit. End of charge pump circuit P
connected to the gate terminal on the ch side, and the Nch side is connected to the Nch (Do
wn) the signal line to the rising edge T terminal of the second D-type flip-flop, the power supply line to the D terminal, the reset signal line to the R terminal, and the Q terminal to the first two-input AND.
The other input terminal of the gate circuit, the output terminal is the input terminal of the inverter circuit, the output terminal is one input terminal of the second two-input AND gate circuit, and the Nch (Down) signal line is the second input terminal.
And the output terminal is connected to the Nch side gate terminal of the charge pump circuit.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. First, a basic configuration which is a premise of an embodiment of the present invention will be described with reference to a circuit diagram of FIG. 1 and a waveform diagram of FIG. FIG. 1 is an overall configuration diagram. In FIG. 1, 1 is a first charge pump circuit, 2 is a second charge pump circuit, 3 is a phase comparison circuit, 4 is a current limiting potential generation circuit, and 5 is a voltage control circuit NVCO.

The first charge pump circuit 1 has four P
It consists of a ch-type MOS gate and four Nch-type MOS gates. The first Pch-type MOS gate has a source terminal connected to the power supply line, a gate terminal connected to the output terminal of the Pch-side current limiting potential generating circuit, and a drain terminal connected to the source of the second Pch-type MOS gate. The gate terminal of the second Pch type MOS gate is connected to the Pch side output terminal of the phase comparison circuit, and the drain is connected to one end of the voltage control circuit 5.
Third Pch MOS gate and fourth Pch MO
The connection of the S gate is the same as the connection of the first Pch type MOS gate and the second Pch type MOS gate, respectively.

The first N-channel MOS gate has a source terminal connected to the ground line, a gate terminal connected to the output terminal of the N-channel current limiting potential generating circuit, and a drain terminal connected to the source terminal of the second N-channel MOS gate. Is done. 2nd Nch
The gate terminal of the type MOS gate is connected to the Nch-side output terminal of the phase comparison circuit, and the drain terminal is connected to one end of the voltage control circuit 5. The connection between the third Nch-type MOS gate and the fourth Nch-type MOS gate is the first
And the connection between the N-channel MOS gate and the second N-channel MOS gate.

The voltage control circuit 5 comprises a resistor and a capacitor. One end of the voltage control circuit 5 is connected to one end of a resistor, and the other end is connected to one end of a capacitor. The other end of the capacitor is connected to a power supply line.

In the example of this embodiment, four P
Although an example of a two-stage parallel circuit including a ch-type MOS gate and four Nch-type MOS gates has been described, the number of stages may be arbitrarily connected.

The difference between the second charge pump circuit 2 and the conventional circuit is that the second charge pump circuit 2 is between the Pch (up) signal line and the Pch type MOS gate circuit, and between the Nch (Down) signal line and Nc.
The point is that a resistor is connected between the h-type MOS gate circuits.

Next, the operation will be described with reference to the waveform diagram of FIG. When the PLL enters a stable operation state, Pch (u
p) The "L" period of the signal line is shortened. While the “L” period is long, the Pch gates of the first charge pump circuit 1 and the second charge pump circuit 2 can be in the ON state, but if the “L” period is short, the second charge pump The circuit 2 does not turn on.

Due to the decrease of the "L" period, the potential rising speed of the voltage control circuit NVCO5 becomes slow. Here, the operation on the Pch (up) side has been described.
On the (Down) side, the "H" period of the Nch (up) signal line is shortened, and the same operation is performed.

Since the speed at which the potential of the voltage control circuit NVCO5 rises and falls becomes slower, the PLL return loop CL
K jitter can be reduced. Further, it is possible to reduce the time required for the stable operation of the PLL.

The first embodiment is configured as follows using a logic circuit instead of the resistor in the basic configuration circuit shown in FIG.

A detailed configuration including a logic circuit according to the first embodiment of the present invention will be described with reference to the circuit of FIG. 3 and the waveform diagram of FIG. FIG. 3 is a detailed configuration diagram including a logic circuit. In FIG. 3, 2 is a second charge pump circuit, 5 is a voltage control circuit NVCO, 21 and 2
2 is a D-type flip-flop, 23 is a 2-input OR gate circuit, and 24 is a 2-input AND gate circuit.

The D-type flip-flop 21 has a falling edge T terminal connected to the source clock signal line and a D terminal connected to Pc.
h (up) signal line, R terminal to RESET signal line, Q
The terminal is connected to one input terminal of the two-input OR gate circuit 23. The other input terminal of the two-input OR gate circuit 23
Connected to Pch (up) signal line. The output line of the two-input OR gate circuit 23 is connected to the P of the second charge pump circuit 2.
Connected to the ch gate terminal.

The D-type flip-flop 22 has a falling T terminal connected to the return ring CLK signal line and a D terminal connected to the Nch (D
own) The S terminal is connected to the signal line, and the Q terminal is connected to the RESET signal line.
A terminal is connected to one input terminal of 24 two-input AND gate circuits. The other input terminal of the two-input AND gate circuit 24 is connected to an Nch (Down) signal line. The output line 24 of the two-input AND gate circuit is connected to the Nch gate terminal of the second charge pump circuit 2.

Next, the operation will be described with reference to the waveform diagram of FIG. First, assuming that the rising edge of the source CLK is before the rising edge of the return ring CLK, the Pch (up) signal outputs “L” from the rising of the source CLK to the rising edge of the return ring CLK.

Further, the D-type flip-flop 31 operates in the falling edge of the source CLK. When the Pch (up) signal is "L" until this falling edge,
The Q output N21P of the D-type flip-flop 31 becomes "L". When the “L” output and the Pch (up) signal line are “L”, the Pch type MOS gate of the second charge pump circuit 2 is turned on, and the voltage rising speed of the voltage control circuit 5 is increased.

Next, when the PLL becomes stable, Pch
Since the “L” period of the (up) signal is shortened, a two-input OR
The output signal N23P of the gate circuit 23 does not become "L". That is, the voltage rising speed of the voltage control circuit 5 becomes slow. The same applies to the operation on the Nch side.

The slower voltage rising speed of the voltage control circuit 5 has the effect of reducing the jitter of the PLL return loop CLK. Further, there is an effect that the time required until the stable operation of the PLL is shortened. In particular, the first embodiment
Then, while providing flip-flops 21 and 22,
Since the two-input OR gate circuit 23 and the two-input AND gate circuit 24 are provided to adjust the potential change speed of the voltage control circuit 5, by appropriately setting their operation characteristics, the jitter reduction effect and the jitter reduction effect can be improved. The operation stabilizing effect can be accurately realized.

Embodiment 2 FIG. A detailed configuration including a logic circuit according to the second embodiment of the present invention will be described with reference to the circuit of FIG. 5 and the waveform diagram of FIG. FIG. 5 is a detailed configuration diagram including a logic circuit. In FIG. 5, 31 and 32 are D
A type flip-flop, 33 is a 2-input AND gate circuit, 34 is a 2-input OR gate circuit, 35 is an inverter gate circuit, and 36 is a 2-input AND gate circuit.

The D-type flip-flop 31 has a falling edge T terminal on a Pch (up) signal line, a D terminal on a power supply line, an R terminal on a RESET signal line, and a Q terminal on a first two-input AND gate circuit 33. Is connected to one of the input terminals. The output terminal of the first two-input AND gate circuit 33 is connected to one input terminal of the two-input OR gate circuit 34. 2
The other input terminal of the input OR gate circuit 34 is Pch (u
p) Connected to signal line. The output line of the two-input OR gate circuit 34 is connected to the PchMOS gate terminal of the second charge pump circuit 2.

The D-type flip-flop 32 has a rising T terminal connected to an Nch (Down) signal line, a D terminal connected to a power supply line, an R terminal connected to the RESET terminal, and a Q terminal connected to the first two-input AND gate circuit 33. Is connected to the other input terminal. The output terminal of the first two-input AND gate circuit 33 is connected to the input terminal of the inverter gate circuit 35. The output terminal of the inverter gate circuit 35 is a second two-input AND
The gate circuit 36 is connected to one input terminal.

The other input terminal of the second two-input AND gate circuit 36 is connected to a Pch (Down) signal line. The output terminal of the second two-input AND gate circuit 36 is connected to the N-channel MOS gate terminal of the second charge pump circuit 2.

Next, the operation will be described with reference to the waveform diagram of FIG. First, when the PLL is not performing a stable operation, the Pch (up) signal line repeats “L” and “H”. Due to the repetition of the “L” and “H”, the T terminal of the D-type flip-flop 31 repeats the “L” and “H” inputs, so that the Q terminal changes from “L” to “H”. Q
The "H" output of the terminal remains at "H" unless initialized by the reset operation of the R terminal.

Next, when the PLL approaches stable operation, Nch
If the (Down) signal line changes from “L” to “H”, the Q terminal of the D-type flip-flop 32 becomes “L”.
From "L" to "H". As a result, the output terminal of the first two-input AND gate circuit 33 changes from "L" to "H".

When the output of the output terminal of the first two-input AND gate circuit 33 becomes "H", the PchMOS gate and the NchMOS gate of the second charge pump circuit 2 are turned off, and the voltage of the voltage control circuit 5 rises. , The lowering speed can be reduced.

In the course of the PLL stable operation, P
If the operation is not stabilized in the order of “L” of ch (up) and “H” of Nch (Down), but becomes stable only by “L” of Pch (up), the PchM of the second charge pump circuit
The OS gate and the NchMOS gate can be turned on. When the operation becomes stable in such a state, the PLL
This is the time when the return loop CLK is already in a state with little jitter.

The slowing down of the voltage rising speed of the voltage control circuit 5 has the effect of reducing the jitter of the PLL return loop. Further, there is an effect that the time required until the stable operation of the PLL is shortened. In particular, in the second embodiment,
Flip-flops 31 and 32 are provided, and a two-input OR gate circuit 34 and a two-input AND gate circuit 3
3 and 36 are provided to adjust the potential fluctuation speed of the voltage control circuit 5. By properly setting these operation characteristics, the jitter reduction effect and the operation stabilization effect can be accurately realized. Can be.

[0035]

According to the first aspect of the present invention, there is provided a flip-flop which operates in response to the output of the phase comparator and the source clock, and operates in response to the output of the phase comparator and the output of the flip-flop. Is provided to adjust the speed of voltage fluctuation of the voltage control circuit. By appropriately setting these operating characteristics, the effect of reducing the jitter of the PLL return clock can be realized accurately and the operation of the PLL can be stabilized. Can be reliably achieved.

According to the second aspect of the present invention, the flip-flop which operates in response to the output of the phase comparator and the source clock is provided, and the two-input OR gate which operates in response to the output of the phase comparator and the output of the flip-flop is provided. Circuit and a two-input AND gate circuit are provided to adjust the potential change speed of the voltage control circuit.
By properly setting these operating characteristics, the PLL
The effect of reducing the jitter of the return clock can be realized accurately, and the PL
The time required for stabilizing the operation of L can be reliably reduced.

According to the third invention, the first and second flip-flops which operate in response to the output of the phase comparison circuit and the source clock are provided, and the first and second flip-flops are provided.
First two-input AND gate circuit which operates upon receiving the output of the flip-flop, and a two-input OR gate circuit and a second two-input AND gate circuit which operates upon receiving the output of the phase comparison circuit and the output of the flip-flop Is provided to adjust the speed of voltage fluctuation of the voltage control circuit. By appropriately setting these operating characteristics, the effect of reducing the jitter of the PLL return clock can be realized accurately and the operation of the PLL can be stabilized. Can be reliably achieved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a basic configuration according to an embodiment of the present invention.

FIG. 2 is a waveform chart showing an operation of a basic configuration circuit according to one embodiment of the present invention.

FIG. 3 is a circuit diagram showing a semiconductor integrated circuit according to one embodiment of the present invention;

FIG. 4 is a waveform chart showing an operation of the circuit according to the embodiment of the present invention.

FIG. 5 is a circuit diagram showing a semiconductor integrated circuit according to another embodiment of the present invention.

FIG. 6 is a waveform chart showing an operation of a circuit according to another embodiment of the present invention.

FIG. 7 is a circuit diagram showing a conventional semiconductor integrated circuit.

FIG. 8 is a waveform chart showing an operation in a conventional semiconductor integrated circuit.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 first charge pump circuit, 2 second charge pump circuit, 3 phase comparison circuit, 4 current limiting potential generation circuit, 5 voltage control circuit, 21, 22D type flip-flop, 23 2-input OR gate circuit, 24
2-input AND gate circuit, 31, 32 D-type flip-flop, 33 2-input AND gate circuit, 342
Input OR gate circuit, 35 inverter gate circuit, 3
6 2-input AND gate circuit.

Claims (3)

[Claims] 1. A phase comparison circuit for comparing signal phases of a source clock and a return clock and deriving an output corresponding to the phase difference, receiving an output of the phase comparison circuit, and receiving an output of the phase comparison circuit. A charge pump circuit that derives a corresponding output, and a voltage control circuit that receives the output of the charge pump circuit and derives an output of a potential level corresponding to the output of the charge pump circuit.
In a circuit configuration, a flip-flop that operates in response to an output of the phase comparison circuit and a source clock, and a logic circuit that operates in response to an output of the phase comparison circuit and an output of the flip-flop are provided. A semiconductor integrated circuit, wherein a potential change speed of the voltage control circuit is adjusted by an output of the circuit. 2. Receiving a source clock and a return clock,
A phase comparison circuit having Pch (up) and Nch (Down) signal lines as outputs, and a Pch connected to a gate electrode of a charge pump circuit constituting a PLL circuit
(Up) or part of the Nch (Down) signal line,
On the Pch side, a Pch (up) signal line is connected to a D terminal of a D-type flip-flop, a source clock signal line is connected to a falling edge T terminal, a reset signal line is connected to an R terminal, and a Q terminal output line is a 2-input OR gate. One input terminal of the circuit, the other end is connected to a Pch (up) signal line, the output signal line of the two-input OR gate circuit is connected to a Pch gate terminal of a charge pump circuit, and the Nch side is an Nch (Down) signal. Line D
The D terminal of the type flip-flop, the return clock signal signal line to the T terminal of the falling edge, the reset signal line to the S terminal, the Q terminal output line to one input terminal of the two-input AND gate circuit, and the other. 2. The semiconductor integrated circuit according to claim 1, wherein an end is connected to an Nch (Down) signal line, and an output signal line of the two-input AND gate circuit is connected to an Nch gate terminal of a charge pump circuit. Receiving a source clock and a return clock;
A phase comparison circuit having Pch (up) and Nch (Down) signal lines as outputs, and Pc connected to a gate electrode of a charge pump generation circuit constituting a PLL circuit
A part of the h (up) or Nch (Down) signal line is reset. On the Pch side, the Pch (up) signal line is reset to the falling edge T terminal of the first D type flip-flop, and the power supply line is reset to the D terminal. Signal to R terminal, Q terminal to 1st
Is connected to one input terminal of the two-input AND gate circuit of
The output terminal of the 2-input AND gate circuit is connected to one input terminal of the 2-input OR gate circuit, and the Pch (up) signal line is connected to the 2 input OR gate circuit.
The input terminal is connected to the other input terminal of the input OR gate circuit, the output terminal is connected to the Pch side gate terminal of the charge pump circuit, and the Nch side is connected to the Nch (Down) signal line to the rising edge T terminal of the second D type flip-flop. The power supply line to the D terminal, the reset signal line to the R terminal, the Q terminal to the other input terminal of the first two-input AND gate circuit, the output terminal to the input terminal of the inverter circuit, and the output terminal to the 2 2 inputs A
Nch (Down) is connected to one input terminal of the ND gate circuit.
A semiconductor integrated circuit having a signal line connected to the other input terminal of the second two-input AND gate circuit and an output terminal connected to an Nch-side gate terminal of the charge pump circuit.