JPH0795563B2 - パスゲートマルチプレクサレシーバ集積回路 - Google Patents
パスゲートマルチプレクサレシーバ集積回路Info
- Publication number
- JPH0795563B2 JPH0795563B2 JP2411551A JP41155190A JPH0795563B2 JP H0795563 B2 JPH0795563 B2 JP H0795563B2 JP 2411551 A JP2411551 A JP 2411551A JP 41155190 A JP41155190 A JP 41155190A JP H0795563 B2 JPH0795563 B2 JP H0795563B2
- Authority
- JP
- Japan
- Prior art keywords
- pass gate
- integrated circuit
- transistor
- field effect
- channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
- H10D89/711—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using bipolar transistors as protective elements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/90—Masterslice integrated circuits
- H10D84/998—Input and output buffer/driver structures
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US471893 | 1990-01-29 | ||
| US07/471,893 US5036215A (en) | 1990-01-29 | 1990-01-29 | Pass gate multiplexer receiver circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04114465A JPH04114465A (ja) | 1992-04-15 |
| JPH0795563B2 true JPH0795563B2 (ja) | 1995-10-11 |
Family
ID=23873406
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2411551A Expired - Lifetime JPH0795563B2 (ja) | 1990-01-29 | 1990-12-18 | パスゲートマルチプレクサレシーバ集積回路 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US5036215A (en:Method) |
| EP (1) | EP0440331A2 (en:Method) |
| JP (1) | JPH0795563B2 (en:Method) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5200907A (en) * | 1990-04-16 | 1993-04-06 | Tran Dzung J | Transmission gate logic design method |
| US5111069A (en) * | 1990-08-27 | 1992-05-05 | Dallas Semiconductor Corporation | Layout of integrated circuit with very large transistors |
| JP3375659B2 (ja) * | 1991-03-28 | 2003-02-10 | テキサス インスツルメンツ インコーポレイテツド | 静電放電保護回路の形成方法 |
| US5519355A (en) * | 1992-11-19 | 1996-05-21 | At&T Global Information Solutions Company | High speed boundary scan multiplexer |
| US5453719A (en) * | 1993-12-17 | 1995-09-26 | Nec Corporation | Oscillator circuit generating oscillation signal responsive to one of resonant element and external clock signal |
| US5543650A (en) * | 1995-01-12 | 1996-08-06 | International Business Machines Corporation | Electrostatic discharge protection circuit employing a mosfet device |
| US5815354A (en) * | 1997-03-21 | 1998-09-29 | International Business Machines Corporation | Receiver input voltage protection circuit |
| US6028758A (en) * | 1998-01-16 | 2000-02-22 | Vantis Corporation | Electrostatic discharge (ESD) protection for a 5.0 volt compatible input/output (I/O) in a 2.5 volt semiconductor process |
| US6219812B1 (en) * | 1998-06-11 | 2001-04-17 | Sun Microsystems, Inc. | Apparatus and method for interfacing boundary-scan circuitry with DTL output drivers |
| US6380022B1 (en) * | 2000-04-20 | 2002-04-30 | Hewlett-Packard Company | Method for creating a useful biopolar junction transistor from a parasitic bipolar junction transistor on a MOSFET |
| US6362653B1 (en) | 2001-02-06 | 2002-03-26 | International Business Machines Corporation | High voltage tolerant receivers |
| KR100468787B1 (ko) * | 2003-05-02 | 2005-01-29 | 삼성전자주식회사 | 래치-업(Latch-up)에 의한 전류 흐름을 방지할 수있는 반도체 장치 |
| US8230281B2 (en) * | 2009-04-13 | 2012-07-24 | Altera Corporation | Techniques for boundary scan testing using transmitters and receivers |
| US8482029B2 (en) * | 2011-05-27 | 2013-07-09 | Infineon Technologies Austria Ag | Semiconductor device and integrated circuit including the semiconductor device |
| US11211342B1 (en) * | 2020-07-21 | 2021-12-28 | Taiwan Semiconductor Manufacturing Company Ltd. | Multiplexer cell and semiconductor device having camouflage design, and method for forming multiplexer cell |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4286173A (en) * | 1978-03-27 | 1981-08-25 | Hitachi, Ltd. | Logical circuit having bypass circuit |
| US4763020B1 (en) * | 1985-09-06 | 1997-07-08 | Ricoh Kk | Programmable logic device having plural programmable function cells |
| JPS62220879A (ja) * | 1986-03-22 | 1987-09-29 | Hitachi Ltd | 半導体装置 |
| US4710649A (en) * | 1986-04-11 | 1987-12-01 | Raytheon Company | Transmission-gate structured logic circuits |
| JP2679046B2 (ja) * | 1987-05-22 | 1997-11-19 | ソニー株式会社 | メモリ装置 |
| JPS63300529A (ja) * | 1987-05-29 | 1988-12-07 | Nec Corp | 半導体集積回路 |
| US4755696A (en) * | 1987-06-25 | 1988-07-05 | Delco Electronics Corporation | CMOS binary threshold comparator |
| JPH0196573A (ja) * | 1987-10-08 | 1989-04-14 | Matsushita Electron Corp | 集積回路 |
| JPH01130554A (ja) * | 1987-11-17 | 1989-05-23 | Fujitsu Ltd | 静電保護回路 |
| JPH0671203B2 (ja) * | 1987-12-23 | 1994-09-07 | 株式会社東芝 | 論理回路 |
-
1990
- 1990-01-29 US US07/471,893 patent/US5036215A/en not_active Expired - Fee Related
- 1990-12-18 JP JP2411551A patent/JPH0795563B2/ja not_active Expired - Lifetime
-
1991
- 1991-01-04 EP EP91300070A patent/EP0440331A2/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| EP0440331A3 (en:Method) | 1994-02-02 |
| EP0440331A2 (en) | 1991-08-07 |
| US5036215A (en) | 1991-07-30 |
| JPH04114465A (ja) | 1992-04-15 |
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