JPH0795562B2 - Design method of integrated circuit by building block method - Google Patents

Description

The present invention relates to a method of designing an integrated circuit by a building block method in which a wiring area of the integrated circuit is reduced.

[Prior Art] As one method for designing a semiconductor integrated circuit (hereinafter referred to as LSI) using a computer, a building block method is adopted. FIG. 4 is a schematic diagram showing the layout of a functional block D designed by this building block method. A logic circuit pattern is formed in the logic circuit block 3, and the logic circuit block row 10 is formed by arranging the logic circuit blocks 3 continuously in one row. The logic circuit block rows 10 are arranged in parallel with each other at a predetermined interval, and the respective logic circuit blocks 3 are appropriately connected by the inter-logic circuit block wiring 11. The inter-block wiring 11 includes a polysilicon wiring 4 (solid line), a first metal wiring 5 (broken line) and a second wiring.
The metal wiring 6 (one-dot chain line) of FIG. The layout of the logic circuit blocks 3 in each functional block and the wiring between them are determined by a computer.

In the conventional LSI designing method adopting the building block method, first, the logic circuit block 3 is properly arranged and wired by the building block method described above. Next, as shown in FIG. 5, the functional blocks D, E, F, etc. configured in this way are arranged, and the functional blocks are wired by the inter-functional block wiring 12. The inter-functional block wiring 12 is provided with the area outside the functional blocks as its wiring area. In this way, the LSI
Is designed.

[Problems to be Solved by the Invention] However, in the above-described conventional method for designing an integrated circuit by the building block method, only the logic circuit inter-block wiring 11 is wired in the functional block D, and the inter-functional block wiring 12 is The area outside the functional block is wired as the wiring area. Therefore, there is a problem that a large wiring area is required for wiring between the functional blocks, the wiring between the functional blocks becomes long, and the operation speed is slowed down.

The present invention has been made in view of such problems,
An object of the present invention is to provide a method of designing an integrated circuit by the building block method, which can reduce the wiring area of the integrated circuit of the building block method and can increase the operating speed of the integrated circuit.

[Means for Solving Problems] A method of designing an integrated circuit by a building block method according to the present invention is a floor plan corresponding to shapes and arrangements of a plurality of functional blocks constituting the integrated circuit and wiring between them. And a step of designing a layout of logic circuits in each of the functional blocks and wiring between the logic circuits by a building block method including signal wiring not used in the functional blocks, and Arranging the blocks based on the floor plan, and connecting the functional blocks to each other by utilizing unused signal wirings in the functional blocks.

[Operation] In the present invention, first, the shape and arrangement of the functional blocks and the floor plan for wiring between them are determined.
Next, the logic circuits in the functional block are arranged and wired by the building block method, and at this time, the signal wiring (passage wiring) not used in the functional block is also designed. Then, the respective functional blocks are arranged based on the floor plan, and wiring between the functional blocks is performed by utilizing the unused signal wiring in the functional blocks. As a result, not only the layout of logic circuits and the wiring between them, but also the wiring between functional blocks can be designed to be included in the functional blocks as much as possible, and the wiring area between functional blocks outside the functional blocks can be minimized. Becomes

Embodiments Embodiments of the present invention will be described below with reference to the accompanying drawings. 1 to 3 are schematic views showing a method of designing an integrated circuit by a building block method according to an embodiment of the present invention in the order of steps. First, as shown in FIG. 1, the shapes and arrangements of the functional blocks 1, A, B, C in the integrated circuit of the building block method and the floor plan for the wiring paths 2, a, b, c between the functional blocks are determined. . The functional blocks 1, A, B, C are determined, for example, in a shape and an arrangement capable of forming an integrated circuit with a minimum area. Further, the inter-functional-block wirings 2, a, b, c, d that connect the functional blocks 1, A, B, C to each other are also determined in consideration of the number of wirings and the wiring area. The inter-functional block wirings a and b are passing wirings that pass through the functional block A.

Next, as shown in FIG. 2, the layout and wiring of the logic blocks in each functional block are designed by computer calculation by the building block method. FIG. 2 is a schematic diagram specifically showing the layout of the functional block A configured by this design. According to this design method, the logic circuit blocks 3 are arranged to form the logic circuit block row 8. The logic circuit blocks 3 are connected to each other by inter-logic circuit block wiring 9 formed by a building block method. In this embodiment, when the wiring 9 between the logic circuit blocks is formed by this building block system, the passing wirings a and b that connect the functional blocks B and C through the functional block A are also wired by the same process. To do. The inter-functional-block wirings a and b passing through the functional block A are not wirings directly related to the logical operation of the functional block A. Further, in the figure, the wavy line is a section where the boundary of the logic circuit block 3 and the inter-block wirings a and b overlap each other, and this part is shown by a wavy line in order to distinguish the two. Further, the inter-logic circuit block wiring 9 and the inter-functional block wiring 2 (a, b, c, d) designed by the computer are a multi-layer formed by the first metal wiring 5, the second metal wiring 6 and the polysilicon wiring 4. The structure is wired.

Next, as shown in FIG. 3, the functional blocks A, B, and C thus formed are arranged based on the floor plan shown in FIG. 1, and, for example, the functional block B and the functional block C are arranged.
And are connected using the passing wirings a and b formed in the functional block A. The wiring between other functional blocks is also a through wiring (not used for the circuit function) provided in the functional block through which the wiring between the functional blocks passes based on the wiring route determined by the floor plan shown in FIG. wiring)
Use to connect.

In the integrated circuit thus formed, the area outside the functional blocks necessary for the wiring between the functional blocks is as small as possible.
In FIG. 3, the passing wirings a and b of the functional block A are shown.
May actually be formed by bending, but the illustration is shown by a straight line for simplification.

[Effects of the Invention] As described above, according to the present invention, when designing each functional block by arranging and wiring the logic circuit blocks between the functional blocks according to the building block method, the functional block is not used in the functional block. Since the wiring is also included in the design, the wiring between the functional blocks can also be formed within the functional block by connecting the functional blocks using this passing wiring. The wiring area can be significantly reduced. Therefore, according to the present invention, the wiring between the functional blocks can be shortened, so that the operating speed of the integrated circuit can be increased and the size of the integrated circuit can be reduced.

[Brief description of drawings]

1 to 3 are schematic diagrams showing a method of designing an integrated circuit by a building block method according to an embodiment of the present invention in the order of steps, FIG. 4 is a schematic diagram showing a layout of a conventional functional block, and FIG. It is a schematic diagram which shows the integrated circuit by the conventional building block system. 1, A to F; functional block, 2, 12, a to d; wiring between functional blocks, 3; logic circuit block, 4; polysilicon wiring, 5; first
Metal wiring, 6; second metal wiring, 8, 10; logic circuit block row, 9, 11; wiring between logic circuit blocks

Claims (1)

[Claims] 1. A step of determining a floor plan corresponding to shapes and arrangements of a plurality of functional blocks forming an integrated circuit and wiring between them, and arrangement of logic circuits in each of the functional blocks and the logic circuit thereof. A process of designing wiring between each other by a building block method including signal wiring not used in the functional block, and arranging the functional block based on the floor plan and unused signals in the functional block A step of connecting the functional blocks to each other using wiring, and a method of designing an integrated circuit by a building block method.