JPH0795076A - Digital signal processing circuit - Google Patents

Abstract

PURPOSE:To obtain the digital signal processing circuit with a small circuit scale and having a bit number extension function not causing rinsing. CONSTITUTION:An analog signal is converted into an N-bit digital signal by an A/D converter 30. A signal processing circuit 31 applies prescribed processing to an output of the A/D converter 30. An N-bit time series signal 41 being an output of the signal processing circuit 31 is given to a difference detection circuit 32. The difference detection circuit 32 detects a difference between preceding and succeeding time series signals 41 to provide an output of a predetermined selection signal. A selector 33 selects an auxiliary signal 42 whose weight is smaller than N-bit to be added to the time series signal 41 based on the kind of the selection signal. An adder 35 adds the auxiliary signal 42 to the time series signal 41 to provide an (N+M)-bit time series signal 44. The time series signal 44 is converted into an analog signal by a D/A converter 38 through a signal processing circuit 37.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing circuit for digitally performing video signal processing.

[0002]

2. Description of the Related Art In recent years, with the progress of digital signal processing technology, digital signal processing has become the mainstream of video signal processing. However, not all signal processing is performed digitally, so an analog-digital converter (AD converter) or a digital-analog converter (DA) is used.
Converter is required.

A clearer image can be obtained as the number of bits of the digital signal is larger. However, currently, mainly processing of about 8 bits is performed due to restrictions such as circuit scale and price.

In particular, the AD converter is
It is difficult to increase the number of bits. Therefore, the number of bits of the AD converter limits the total number of bits of the digital signal processing circuit.

Therefore, the output of the N-bit AD converter is set to N
A circuit that expands to + M bits and improves image quality deterioration due to bit resolution is required. FIG. 9 shows an example of the circuit. This circuit is a circuit for expanding an 8-bit digital signal into a 10-bit digital signal.
The mechanism will be briefly explained.

The analog input signal is converted into an 8-bit digital signal in the AD converter 10. The 8-bit digital signal is subjected to various kinds of processing in the signal processing circuit 11.

The output signal 21 of the signal processing circuit 11
The low-pass frequency component is extracted by the low-pass filter 12, and becomes a digital signal 22 having a total of 10 bits of an integer part of 8 bits and a decimal part of 2 bits.

In the adder 13, the 10-bit digital signal 22 is subtracted from the output signal 21 of the signal processing circuit 11, and a 10-bit high frequency component is output. The output signal 23 of the adder 13 is input to the coring circuit 14. The coring circuit 14 rounds the fractional part of the 10-bit output signal 23 to obtain an 8-bit integer part digital signal 24.

The signal 24 is an 8-bit high frequency component. Integer part 8-bit digital signal 24
Is added to the output signal 22 of the low pass filter 12 in the adder 15.

As a result, from the adder 15, a 10-bit digital signal 25 in which the number of bits of the low frequency component is expanded while the high frequency component is held is obtained. The digital signal 25 is subjected to various kinds of processing in the signal processing circuit 16. The output signal 26 of the signal processing circuit 16 is converted into an analog signal in the DA converter 17.

However, in the above-mentioned digital signal processing circuit, the characteristics of the digital signal processing circuit vary depending on the characteristics of the low pass filter 12. Therefore, in order to obtain practical characteristics, it is necessary to use a filter with about 5 taps, which has a drawback of increasing the circuit scale.

Further, when the level of the output signal 21 of the signal processing circuit 11 suddenly changes, the low pass filter 12 inevitably causes some ringing (the waveform is disturbed before and after the change point). is there.

[0013]

As described above, in the conventional digital signal processing circuit, the characteristic of the digital signal processing circuit changes depending on the characteristic of the low-pass filter, and in order to obtain a practical characteristic, 5 taps are required. It is necessary to use a filter of a certain degree, and there is a drawback that the circuit scale becomes large. Further, when the level of the output signal of the signal processing circuit suddenly changes, there is a drawback that the low pass filter causes some ringing.

The present invention has been made to solve the above-mentioned drawbacks, and an object thereof is a gradation improving circuit which has a small circuit scale and does not cause ringing even when the output signal level of a signal processing circuit suddenly changes. That is, it is to provide a digital signal processing circuit having a bit number expanding function.

[0015]

In order to achieve the above object, a digital signal processing circuit of the present invention comprises an analog-digital converter for converting an analog signal into an N-bit digital signal and an output of the analog-digital converter. A first difference that detects a difference between values before and after a certain N-bit time-series signal and that generates an auxiliary signal having a smaller weight than N bits to be added to the N-bit time-series signal
Means, second means for adding the auxiliary signal to the N-bit time-series signal to obtain an N + M-bit signal, and an N + M-bit digital signal output from the second means as an analog signal. And a digital-to-analog converter for converting into a signal.

The first means detects the difference between the values before and after the N-bit time-series signal output from the first signal processing circuit, and outputs a predetermined selection signal, and the difference detecting circuit. A selector for outputting an auxiliary signal having a weight smaller than N bits to be added to the N-bit time-series signal based on a selection signal, and the second means includes the N-bit time-series signal and the selector. The delay circuit adjusts the timing of the auxiliary signal, and an adder that adds the auxiliary signal to the N-bit time-series signal and outputs an N + M-bit time-series signal.

[0017]

According to the above construction, the N-bit digital signal can be expanded to the N + M-bit digital signal to obtain a smooth output waveform. Moreover, ringing does not occur at the change point of the level of the digital time-series signal as in the conventional case. Further, there is no deterioration of high frequency components. Further, the difference detection circuit and the selector do not increase the circuit scale.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The digital signal processing circuit of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows a digital signal processing circuit according to the first embodiment of the present invention. This circuit is a circuit for expanding an 8-bit digital signal into a 10-bit digital signal.

The analog input signal is sent to the data converter 1 / T in the AD converter 30 which operates with a clock having a period T.
Is converted into an 8-bit digital time series signal. In addition, the 8-bit digital signal is sent to the signal processing circuit 3
At 1, various kinds of processing are performed.

The output signal 41 of the signal processing circuit 31 is input to the difference detection circuit 32. The difference detector 32 operates as follows. Input signal 4 of the difference detection circuit 32
1 for every time T, A (0), A (1), ... A (n),
(However, A (n) is an 8-bit digital signal at time nT and takes a value from 0 to 255.) A digital time series signal that changes.

Then, B (0) = A (n) -A (n-1) (1) B (1) = A (n + 1) -A (n) (2) is calculated.

As a result, if B (0) = 0 and B (1) = 1, a +1/4 selection signal is output. If B (0) = 1 and B (1) = 0, a -1/4 selection signal is output.

If B (0) = 0 and B (1) = − 1, a −1/4 selection signal is output. If B (0) = − 1 and B (1) = 0, a +1/4 selection signal is output. Further, when B (0) and B (1) are combinations other than the above four combinations, the ± 0 selection signals are output.

These selection signals are input to the selector 33. The selector 33 outputs an auxiliary signal having a smaller weight than 8 bits to be added to the 8-bit digital time series signal according to the type of the selection signal. This auxiliary signal is
It becomes +1/4 for the +1/4 selection signal, -1/4 for the -1/4 selection signal, and ± 0 for the ± 0 selection signal.

The auxiliary signal 42 is input to the adder 35. The 8-bit digital time series signal 41 output from the signal processing circuit 31 is input to the adder 35 via the delay circuit 36. In the adder 35, the auxiliary signal 42 is added to the digital time series signal (A (n)) 41.
As a result, the output signal 44 of the adder 35 becomes a 10-bit digital time series signal in quarter steps.

The output signal 44 of the adder 35 is subjected to various kinds of processing by the signal processing circuit 37. Further, the output signal of the signal processing circuit 37 is converted into an analog signal in the DA converter 38.

A specific example of the operation of the digital signal processing circuit according to the first embodiment of the present invention will be described with reference to FIGS. Note that FIG. 2 shows the time and the digital signal 41.
It shows the relationship between the levels. FIG. 3 shows the relationship between time and the level of the digital signal 44.

Consider a case where the level of the digital signal 41 changes to A (0), A (1), ... A (7) every time T. First, consider the digital signal A (1). The level of the digital signal A (1) is 49. The level of A (0) is 49, and the level of A (2) is
50. Therefore, using the equations (1) and (2), B (0) = 0 and B (1) = 1 are obtained, and therefore the difference detection circuit 32 outputs the +1/4 selection signal. Therefore, in the adder 35, the level +1/4 of the auxiliary signal 42 is added to the level 49 of the digital signal A (1), and the level of the digital signal 44 becomes 49 + 1/4.

Next, the digital signal A (2) will be examined. The level of the digital signal A (2) is 50. The level of A (1) is 49, and the level of A (3) is 50. Therefore, using the above equations (1) and (2), B (0) = 1 and B (1) = 0 are obtained, so that the difference detection circuit 32 outputs a -1/4 selection signal. Therefore, in the adder 35, the digital signal A (2)
Of the auxiliary signal 42 is added to the level 50 of the digital signal 44, and the level of the digital signal 44 becomes 50-1 / 4.

Similarly, digital signals A (3) ... A
Also for (6), when a predetermined auxiliary signal is added, the digital signal 44 becomes 1 in 1/4 steps as shown in FIG.
It becomes a 0-bit digital time series signal, and the waveform becomes smoother than that of the 8-bit digital signal 41.

FIGS. 4 and 5 show the operation of the digital signal processing circuit of the present invention when the level of the digital time-series signal changes suddenly (when it changes by 2 or more). Note that FIG. 4 shows the relationship between time and the level of the digital signal 41. FIG. 5 shows the time and digital signal 44.
It shows the relationship between the levels.

Now, it is assumed that the level of the digital signal 41 changes every time T, A (10), A (11), ... A (14). First, digital signal A (11)
Consider. The level of the digital signal A (11) is 49. The level of A (10) is 49, A
The level of (12) is 52. Therefore, the above (1)
Using equations (2) and B (0) = 0, B (1) =
Since 3 is obtained, the difference detection circuit 32 outputs a ± 0 selection signal. Therefore, the adder 35 determines that the digital signal A
The level 49 of (11) is output as it is.

Next, the digital signal A (12) will be examined. The level of the digital signal A (12) is 52. The level of A (11) is 49, A (13)
Is 52. Therefore, using the above equations (1) and (2), B (0) = 3 and B (1) = 0 are obtained, so the difference detection circuit 32 outputs a ± 0 selection signal. Therefore, the adder 35 outputs the digital signal A (1
The level 52 of 2) is output as it is.

Similarly, for the digital signal A (13), B (0) = 0, B (1) =-2, and A (1
For 4), B (0) =-2 and B (1) = 0. Therefore, the auxiliary signal is 0, and as shown in FIG. 5, the digital signal 44 is a time-series signal with no ringing at the level change point and no deterioration of high frequency components.

As described above, in the digital signal processing circuit of the present invention, in the digital time series signal 41, signals of the same level (for example, A (2) and A (3) in FIG. 2) are 2 signals.
The auxiliary signal (+1/4, -1/4) is generated only when the difference between the level of the signal and the level of other signals continuous to the signal continues for one or more times, and is ± 1. It is designed to get you. When the above condition is not satisfied, the auxiliary signal (0) is generated, so that the high frequency component is not deteriorated and ringing does not occur at the change point of the level of the digital signal.

The present invention is not limited to the above embodiment, but digital signal processing for expanding an N (N is an arbitrary natural number) bit digital signal into an N + M (M is an arbitrary natural number) bit digital signal. It can be applied to circuits. Therefore, another embodiment of the present invention will be described below.

FIG. 6 shows a digital signal processing circuit according to the second embodiment of the present invention. This circuit
This is a circuit for expanding an 8-bit digital signal into a 9-bit digital signal.

The analog input signal is sent to the data converter 1 / T in the AD converter 30 which operates with a clock having a period T.
Is converted into an 8-bit digital time series signal. In addition, the 8-bit digital signal is sent to the signal processing circuit 3
At 1, various kinds of processing are performed.

The output signal 41 of the signal processing circuit 31 is input to the difference detection circuit 32. The difference detector 32 operates as follows. Input signal 4 of the difference detection circuit 32
1 for every time T, A (0), A (1), ... A (n),
(However, A (n) is an 8-bit digital signal at time nT and takes a value from 0 to 255.) A digital time series signal that changes.

Then, B (n) = A (n + 1) -A (n) (3) is calculated.

As a result, if B (n) = 1, then +1
Output a / 2 selection signal. If B (n) =-1, then a -1/2 selection signal is output. If B (n) is a combination other than the above two combinations, a ± 0 selection signal is output.

These selection signals are input to the selector 33. The selector 33 outputs an auxiliary signal having a smaller weight than 8 bits to be added to the 8-bit digital time series signal according to the type of the selection signal. This auxiliary signal is
It becomes +1/2 for the +1/2 selection signal, -1/2 for the -1/2 selection signal, and ± 0 for the ± 0 selection signal.

The auxiliary signal 42 is input to the adder 35. The 8-bit digital time series signal 41 output from the signal processing circuit 31 is input to the adder 35 via the delay circuit 36. In the adder 35, the auxiliary signal 42 is added to the digital time series signal (A (n)) 41.
As a result, the output signal 44 of the adder 35 becomes a 1 / 2-step 9-bit digital time-series signal.

The output signal 44 of the adder 35 is subjected to various kinds of processing by the signal processing circuit 37. Further, the output signal of the signal processing circuit 37 is converted into an analog signal in the DA converter 38.

A specific example of the operation of the digital signal processing circuit according to the second embodiment of the present invention will be described with reference to FIGS. 7 and 8. Note that FIG. 7 shows time and digital signal 41.
It shows the relationship between the levels. FIG. 8 shows the relationship between time and the level of the digital signal 44.

Now, it is assumed that the level of the digital signal 41 changes to A (0), A (1), ... A (7) every time T. First, consider the digital signal A (3). The level of the digital signal A (3) is 50. The level of A (4) is 51. Therefore,
Since B (3) = 1 is obtained by using the above equation (3), the difference detection circuit 32 outputs a +1/2 selection signal. Therefore, in the adder 35, the digital signal A (3)
Level +1/2 of the auxiliary signal 42 is added to the level 50 of, and the level of the digital signal 44 becomes 50 + 1/2.

Next, the digital signal A (4) will be examined. The level of the digital signal A (4) is 51. The level of A (5) is 51. Therefore,
Since B (4) = 0 is obtained by using the above equation (3), the difference detection circuit 32 outputs a ± 0 selection signal. Therefore, in the adder 35, the level 0 of the auxiliary signal 42 is added to the level 51 of the digital signal A (4), and the level of the digital signal 44 becomes 51 which is the same as the level of the digital signal 41.

Similarly, digital signals A (0) ... A
When (2), A (5), and A (6) are also added with predetermined auxiliary signals, as shown in FIG.
Becomes a 1 / 2-step 9-bit digital time-series signal, and has a smoother waveform than the 8-bit digital signal 41.

When the level of the digital time-series signal changes abruptly (when it changes by 2 or more), there is no ringing at the level change point, as in the first embodiment.
It becomes a time-series signal without deterioration of high frequency components.

The mechanism will be briefly described with reference to FIGS. 4 and 5. It is assumed that the level of the digital signal 41 is changing to A (10), A (11), ... A (14) every time T. First, the digital signal A (1
Consider 1). The level of the digital signal A (11) is 49. The level of A (12) is 52
Is. Therefore, using the above equation (3), B (11)
= 3 is obtained, the difference detection circuit 32 outputs ± 0 selection signals. Therefore, the adder 35 outputs the level 49 of the digital signal A (11) as it is.

Next, the digital signal A (12) will be examined. The level of the digital signal A (12) is 52
Is. Also, the level of the digital signal A (13) is
52. Therefore, using the above equation (3), B (1
Since 2) = 0 is obtained, the difference detection circuit 32 outputs ± 0 selection signals. Therefore, the adder 35 outputs the level 52 of the digital signal A (12) as it is.

Similarly, B (13) =-2 for the digital signal A (13) and B (14) = 0 for A (14). Therefore, the auxiliary signal is 0, and as shown in FIG. 5, the digital signal 44 is a time-series signal with no ringing at the level change point and no deterioration of high frequency components.

[0053]

As described above, the digital signal processing circuit of the present invention has the following effects.
In a digital time-series signal, a predetermined auxiliary signal is added to the digital time-series signal only when the condition that the difference between the level of a certain signal and the levels of other signals continuous to that signal is ± 1 is satisfied. I am configuring.

As a result, the N-bit digital signal can be expanded to the N + M-bit digital signal and a smooth output waveform can be obtained. Moreover, ringing does not occur at the change point of the level of the digital time-series signal as in the conventional case. Further, there is no deterioration of high frequency components. Furthermore, the difference detection circuit and the selector are the adder 2
Since it can be configured with a single unit, 10 flip-flops, and about 10 gates other than the above, the circuit scale is not increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing a digital signal processing circuit according to a first embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the circuit of FIG.

FIG. 3 is a time chart for explaining the operation of the circuit of FIG.

FIG. 4 is a time chart for explaining the operation of the circuits of FIGS. 1 and 6.

5 is a time chart for explaining the operation of the circuits of FIGS. 1 and 6. FIG.

FIG. 6 is a block diagram showing a digital signal processing circuit according to a second embodiment of the present invention.

7 is a time chart for explaining the operation of the circuit of FIG.

FIG. 8 is a time chart for explaining the operation of the circuit of FIG.

FIG. 9 is a block diagram showing a conventional digital signal processing circuit.

[Explanation of symbols]

 10, 30 ... AD converter, 11, 16, 31, 37 ... Signal processing circuit, 12 ... Low-pass filter, 13, 15, 35 ... Adder, 14 ... Coring circuit, 17, 38 ... DA converter, 32 ... Difference detection circuit, 33 ... Selector, 36 ... Delay circuit.

Claims (2)

[Claims] 1. An analog-digital converter for converting an analog signal into an N-bit digital signal, and a difference between values before and after an N-bit time-series signal output from the analog-digital converter is detected, and the result is detected. First means for generating an auxiliary signal having a smaller weight than N bits to be added to the N-bit time-series signal, and the auxiliary signal is added to the N-bit time-series signal to obtain an N + M-bit signal. And a digital-analog converter for converting an N + M-bit digital signal output from the second means into an analog signal. 2. A difference detecting circuit for detecting a difference between values before and after an N-bit time-series signal output from the first signal processing circuit, and outputting a predetermined selection signal. ,
A selector for outputting an auxiliary signal having a weight smaller than N bits to be added to the N-bit time-series signal based on the selection signal;
A delay circuit for adjusting the timing of the bit time series signal and the auxiliary signal, and an adder for adding the auxiliary signal to the N bit time series signal and outputting an N + M bit time series signal. The digital signal processing circuit according to claim 1, wherein: