JP3093800B2 - Digital-to-analog converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital / analog converter for converting digital data into analog data.

[0002]

2. Description of the Related Art When digital data is converted into analog data, if the digital input data is conventionally n bits, a digital / analog converter having a bit input of n bits (hereinafter referred to as a DA converter) is used. Is going.

[0003]

However, when n-bit digital data is converted into analog data by an n-bit DA converter, when the input digital code changes, spikes must not originally occur at the output side. There is a problem that glitch noise occurs. In particular,
In the half value of FS (full scale), as shown in FIG.
The maximum glitch noise occurs when the MSB is switched to 00. This is because the current has been flowing from the constant current source through the n-1 current paths in the DA converter, but the current digital code changes sharply to one current path, and the impedance of the internal signal line is reduced. This is because the constant current source fluctuates due to a transient change.

As described above, when glitch noise occurs, for example, in an image processing apparatus which converts digital image data into analog image data, performs required processing on the analog image data, and displays an image on a monitor, a screen is used. When displaying a gradual change in luminance over the entire screen, there is a problem that interdigital noise occurs on the screen and image quality is degraded.

As a method for reducing the occurrence of such glitch noise, there has been conventionally known a method in which an LPF (low-pass filter) is provided on the analog output side to thereby remove high-frequency noise and reduce glitch noise. ing. However, in the method using the LPF, even if the noise in the signal line on the output side can be reduced, the band of the analog data is limited by the LPF. There is a problem that can not be obtained.

As another method, a method of shifting the sampling timing of analog data so that glitch noise does not occur is known, but in this case, there is a problem that a hardware configuration becomes complicated and expensive.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and has as its object to provide a digital-to-analog converter capable of effectively reducing glitch noise with a simple and inexpensive configuration. I do.

[0008]

According to the present invention, there is provided a digital-to-analog converter having a digital-to-analog converter for converting digital input data into analog data. Has a bit input of n + 1 bits or more, supplies the digital input data to the upper n bits of the digital-to-analog converter excluding the lower 1 bit, and changes the digital input data according to a change in the digital input data. When the current path of the n current paths of the analog converter is switched to one,
A digital code for supplying a current to the lower one bit input of the analog converter is supplied.

[0009]

As described above, for a digital-to-analog converter having n + 1 or more bit inputs, the digital input data is supplied to the upper n bits of the digital-to-analog converter excluding the lower 1 bit. In the case where one of the n current paths of the digital-to-analog converter is switched to one in response to a change in the digital input data, a current is supplied to the lower one bit input of the digital-to-analog converter. By supplying digital code and converting digital input data to analog data,
Glitch noise can be effectively reduced with a simple and inexpensive configuration.

[0010]

FIG. 1 is a conceptual diagram of the present invention. This digital-to-analog (DA) converter uses a DA converter 1 having, for example, an (n + 1) -bit bit input for n-bit digital input data. The n + 1th bit of the input data and the (n-1) th bit of the input data are the nth bit on the input side of the DA converter 1, so that n bits of the digital input are supplied to the n bits of the DA converter 1 excluding the lower 1 bit. The n bits of input data are connected to a digital code generation circuit 2 such as a comparator or a parity generator. In this digital code generation circuit 2, for example, when the MSB of input data changes from logic 0 to logic 1, logic 1 Otherwise, a digital code of logic 0 is output and supplied to the remaining lower 1 bit of the DA converter 1.

According to the configuration of FIG. 1, when the n-bit input data changes from 011..11 to 100..00 and the MSB changes from logic 0 to logic 1, the (n + 1) -bit bit of the DA converter 1 The input is changed from 011... 110 to 100... 001 as shown in FIG.
The logic of the + 1st bit and the first bit becomes 1, and the current path is divided into two in the DA converter 1. Therefore, the change in the internal impedance is smaller than in the case of switching to a single current path as in the related art, so that the fluctuation of the current source is suppressed, and the glitch noise can be effectively reduced. In this case, DA
The lower 2 bits of the converter 1 correspond to the lower 1 bits (LSB) of the digital input data, and the minimum resolution of the input data is determined by the lower 2 bits of the DA converter 1. Changes within the minimum resolution and have no adverse effect on the resolution.

FIG. 3 shows a first embodiment of a DA converter according to the present invention.
It is a block diagram showing an example. This DA converter is
The 8-bit digital input data is converted into analog data using a 9-bit DA converter 3. The 8-bit digital input data is supplied to the second to ninth lower bits of the DA converter 3 and to the comparator 4. The comparator 4 is configured to output a digital code of logic 1 when the input data is 10000000 and to output a digital code of logic 0 otherwise, and supplies the output to the remaining lower 1 bit of the DA converter 3.

With this configuration, when the 8-bit digital input data becomes 10000000, the digital code of the comparator 4 becomes 1 and the input data of the 9-bit DA converter 3 becomes 100000001. Will be split into two. Therefore, the change of the internal impedance in the DA converter 3 at this time can be reduced, and the fluctuation of the current source can be suppressed, so that the glitch noise can be effectively reduced.

FIG. 4 shows a second embodiment of the DA converter according to the present invention.
It is a block diagram showing an example. This DA converter is
Parity generator 5 instead of comparator 4 in FIG.
When the digital input value 1 input from the parity generator 5 is an odd number, a digital code of a logical value 1 is generated when the digital input value is an odd number, and a digital code of a logical value 0 is generated otherwise. The bit is supplied.

According to this embodiment, the logical value of the lower 1 bit of the 9-bit DA converter 3 is 1 not only when the 8-bit digital input data becomes 10000000 but also when it becomes 0100000, for example. Therefore, glitch noise can be effectively reduced over the entirety of 8-bit digital input data.

In the above-described embodiment, the digital input data is 8 bits. However, the number of bits of the input data is not limited to 8 bits, and the present invention can be effectively applied to 4 bits, 16 bits, and the like. can do. As described above, according to the above-described embodiment, the n-bit digital input data is converted to the input value of the remaining lower bits based on the n-bit digital input data by using a DA converter having n + 1 or more bit inputs. To convert the analog data into analog data, without limiting the band of analog data as in the case of using an LPF, and using a complicated and expensive configuration such as shifting the sampling timing of analog data. Glitch noise can be effectively reduced without taking it, and it can be made simple and inexpensive.

[0017]

According to the present invention, for a digital-to-analog converter having a bit input of n + 1 bits or more,
Supplying the digital input data to the upper n bits of the digital-to-analog converter excluding the lower 1 bit;
In the case where one of the n current paths of the digital-to-analog converter is switched to one in response to a change in the digital input data, a current is supplied to the lower one bit input of the digital-to-analog converter. Since a digital code is supplied to convert digital input data into analog data, glitch noise can be effectively reduced with a simple and inexpensive configuration.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram of the present invention.

FIG. 2 is a diagram illustrating the operation of FIG.

FIG. 3 is a block diagram showing a first embodiment of a DA converter according to the present invention.

FIG. 4 is a block diagram showing a second embodiment.

FIG. 5 is a diagram for explaining a conventional technique.

[Explanation of symbols]

 Reference Signs List 1 DA converter 2 Digital code generation circuit 3 DA converter 4 Comparator 5 Parity generator

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 1/08 H03M 1/66

Claims (1)

(57) [Claims] 1. A digital / digital converter having a digital / analog converter for converting digital input data into analog data.
In the analog conversion apparatus, the digital-to-analog converter has a bit input of n + 1 bits or more, and supplies the digital input data to a higher-order n-bit input of the digital-to-analog converter excluding a lower one bit; The digital input device responds to a change in the digital input data.
When the current path is switched to one of the n current paths of the analog converter, a digital code for supplying a current to the lower one bit input of the digital / analog converter is supplied. A digital-to-analog converter characterized by the following.