JPH0795025A - Abnormality detecting circuit for digital periodic signal - Google Patents

Abstract

PURPOSE:To constitute the circuit so that abnormality of plural kinds of digital periodic signals can be detected by a simple constitution, and also, an adjusting part scarcely exists. CONSTITUTION:To period/phase operating means 21-23, plural digital periodic signals CLK1-CLK3 having a specific relation to a frequency and/or a phase are inputted, and by operating the frequency and/or the phase of those signals, plural period/phase operating signals OP1-OP3 to which a significant level period whose frequency is equal is overlapped are outputted, at a normal time. A comparing means 3 detects the coincidence of plural period/phase operating signals by an overlap of the significant level period. Since the overlap of the significant level period is generated periodically, a discriminating means 4 utilizes this fact, and discriminates and outputs the fact in the case abnormality is generated in one or more digital periodic signals, based on a detecting signal DET from the comparing means.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital periodic signal abnormality detection circuit, and is particularly suitable for application to an apparatus using a plurality of synchronizing digital periodic signals having specific relationships in frequency and phase. .

[0002]

2. Description of the Related Art In an electronic exchange system or an electronic computer system, in practice, a plurality of types of synchronizing digital periodic signals (typically clock signals) that define the processing timings of the components are used instead of one type. I am using the one. Such various types of digital periodic signals have a relationship of frequencies having an integer ratio, or a relationship of differing in phase by a predetermined phase difference even if the frequencies are the same.

When only one type of digital periodic signal is disturbed, if the frequency is disturbed or the phase relationship with other digital periodic signals is disturbed, some or all components of the system malfunction. Detection of abnormalities in such digital periodic signals
When entrusted to the abnormality detection part of the component activated by the malfunction,
Malfunction time becomes long and the adverse effects of abnormalities spread over a wide range, and in the worst case, the system also goes down.

Therefore, generally, the electronic exchange system and the electronic computer system are provided with a dedicated abnormality detecting circuit for detecting an abnormality of the digital periodic signal.

Conventionally, there is a system in which such an abnormality detection circuit for a digital periodic signal is provided separately for each type of digital periodic signal, and there is a reference digital period used for forming another digital periodic signal. In some systems, only an abnormality detection circuit for signals is provided.

Conventionally, there are roughly two types of internal configurations of abnormality detection circuits. First, the stop of the oscillation of the digital periodic signal is detected by a timer using a retrigger type mono-multivibrator circuit or the like. Second,
Whether or not the digital periodic signal to be detected has a predetermined relationship with the reference digital periodic signal is input to the phase comparison circuit by directly dividing or dividing one of the two signals and using the phase difference output. Then, it is detected.

[0007]

However, in a system provided only with an abnormality detection circuit for a reference digital periodic signal, if the reference digital periodic signal is normal, it is very likely that the other digital periodic signals are also normal. Although it is based on the fact that there are many cases, it is natural that only digital periodic signals other than the reference become abnormal.In this case, it is not possible to cope with it, and there is a risk of system down etc. Is.

On the other hand, such a problem does not directly occur in the system in which the abnormality detection circuit for the digital periodic signal is separately provided for each type of digital periodic signal. However, if the internal configuration of each abnormality detection circuit employs a configuration that monitors the oscillation stop time, even if there is a digital periodic signal in which the frequency and the phase of other signals are disturbed, Since this is not an oscillation stop, this abnormality cannot be detected, and there is still a risk that the system will go down.

In this way, a digital periodic signal abnormality detection circuit is provided for each type of digital periodic signal,
It is preferable that the internal configuration of each abnormality detection circuit is such that abnormality is detected using a reference digital periodic signal. However, such an abnormality detection circuit having an internal configuration has a complicated configuration and requires an initial adjustment because it is based on a relationship with a reference digital periodic signal, and has such a drawback. Circuits must be prepared for all signals.

As a result, the abnormality detection structure of the digital periodic signal is enormous and complicated when viewed from the whole system,
Moreover, there is an inconvenience that adjustment work is required.

The present invention has been made in consideration of the above points, and is capable of detecting abnormalities of a plurality of types of digital periodic signals with a simple structure and detecting abnormalities of digital periodic signals having few adjustment points. It is an attempt to provide a circuit.

[0012]

In order to solve such a problem, according to the present invention, a plurality of digital periodic signals having a specific relationship in frequency and / or phase are input, and at least one or more digital periodic signal frequencies and / or Outputs from the cycle / phase operation means that operates a phase and outputs a plurality of cycle / phase operation signals corresponding to each input digital cycle signal, in which significant level periods of equal frequency overlap. Comparing means for detecting the coincidence of the cycle and phase of all the cycle / phase operation signals, and when one or more digital cycle signals are abnormal based on the detection signals from this comparing means. And a discriminating means for discriminating and outputting the digital periodic signal.

Here, based on the logic level of each cycle / phase operation signal at the timing when the discriminating means discriminates an abnormality,
It is preferable to further include an abnormal signal specifying signal forming means for forming a signal specifying the abnormal digital periodic signal.

[0014]

In the present invention, the abnormality of a plurality of digital periodic signals is not detected individually, but if there is even one abnormality from the overall relation of a plurality of digital periodic signals, it is detected. This simplifies the configuration and reduces the number of adjustment points.

A plurality of digital periodic signals having a specific relationship with frequency and / or phase are input to the period / phase operating means, and the frequency and / or phase of at least one or more digital periodic signals are operated, and the significant levels with equal frequencies are input. A plurality of period / phase operation signals corresponding to the respective input digital periodic signals with overlapping periods are output. Therefore, the plurality of cycle / phase operation signals from the cycle / phase operation means have the same frequency and the significant level periods overlap if all the input digital cycle signals are normal, while the abnormal cycle signals are abnormal. If there is, it does not overlap with the significant level period of the period / phase operation signal corresponding to the digital periodic signal. The comparison means detects the coincidence of a plurality of period / phase manipulation signals by overlapping the significant level periods. Since the above-mentioned overlap of the significant level periods periodically occurs in the discriminating means, this is utilized, and when one or more digital periodic signals have an abnormality based on the detection signal from the comparing means It is determined and output.

From the above, it is not possible to specify which digital periodic signal is abnormal. Therefore, it is preferable to further include an abnormal signal specifying signal forming means for forming a signal for specifying the abnormal digital periodic signal based on the logic level of each cycle / phase operation signal at the timing when the determining means determines that the abnormality is present.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (A) First Embodiment A first embodiment of a digital periodic signal abnormality detection circuit according to the present invention will be described in detail below with reference to the drawings. Here, FIG. 1 is a block diagram showing a schematic configuration of the abnormality detection circuit of the first embodiment, and shows a case where there are three digital periodic signals.

In FIG. 1, the digital periodic signal abnormality detection circuit 1 of this embodiment is arranged so that the digital periodic signals CLK1, CLK2, CLK3 for controlling the periods and phases of the input digital periodic signals CLK1, CLK2, CLK3.
Corresponding to the period / phase operation circuits 21 and 22,
23, a comparison circuit 3 for detecting the coincidence of the cycle and phase of the cycle / phase operation signals OP1, OP2, OP3 output from the cycle / phase operation circuits 21, 22, 23, and the detection from the comparison circuit 3. It is composed of a discrimination circuit 4 which discriminates the occurrence of an abnormality based on the signal DET.

Here, the three types of input digital periodic signals CLK1, CLK2 and CLK3 are synchronized, and if the respective frequencies are f1, f2 and f3, then f1: f2 is between the frequencies. : F3 = l: m: n (l, m, n are integers).

The respective digital periodic signals CLK1, CLK2, CLK3 having such a relationship are given to the corresponding period / phase operation circuits 21, 22, 23. Each of the cycle / phase manipulation circuits 21, 22 and 23 has a counter circuit 21.
a, 22a, 23a and decoder circuits 21b, 22b,
It is constituted by a cascade connection of 23b.

If each of the counter circuits 21a, 22a, 23a is an L-adic, M-adic, N-adic counter circuit, the cycle of the counter value L, M, N also has a relation of 1: m: n. Each of the counter circuits 21a, 22a, and 23a is reset by being supplied with a reset signal RST from the outside, and then input digital cycle signals CLK1, CLK2, and CLK3.
Is counted, and when the counter value becomes L, M, N, the count value is automatically cleared, and such counting operation is repeated.

Count values from the corresponding counter circuits 21a, 22a, 23a are given to the respective decoder circuits 21b, 22b, 23b. Each decoder circuit 21b, 2
2b and 23b are normal digital periodic signals CLK1 and C
When LK2 and CLK3 are input, output signals (decode signal: cycle / phase operation signal) OP1, OP2 and OP3 from these decoder circuits 21b, 22b and 23b.
The input count value is decoded so that the period of taking the significance level of 1 is overlapped completely or partially and in the narrowest possible period (for example, the period of the digital periodic signal having the shortest period).

Such counter circuits 21a, 22a,
Each cycle / phase operation is performed through the frequency dividing operation and the phase adjusting operation by 23a and the decoder circuits 21b, 22b, and 23b (including the case of adjusting the phase by selecting the rising edge or the falling edge of the counter circuit). Period / phase operation signal O output from the circuits 21, 22 and 23
P1, OP2, OP3 are normal digital periodic signals CL
When K1, CLK2, and CLK3 are input, the frequencies are equal and the significance level periods overlap in a narrow period.

The frequency dividing operation has not only the function of aligning the cycles (frequency), but also the function of expanding the phase shift caused by not having a predetermined relationship on the absolute time axis.

In the case of this embodiment, the significant levels of the respective cycle / phase operation signals OP1, OP2, OP3 are all at the H level, and therefore the AND circuit is applied as the comparison circuit 3. The comparison circuit 3 uses the normal digital periodic signal C
When LK1, CLK2, and CLK3 are input, the period / phase operation signals OP1, OP2, and OP3 that overlap are taken out of the significant level period, and the significant detection signal DET is output only during the overlap period. Therefore, when the normal digital period signals CLK1, CLK2, and CLK3 are continuously input, the detection signal from the comparison circuit 3 having a narrow significant level period at a period equal to that of each period / phase operation signal OP1, OP2, and OP3. DET is repeatedly output.

In the case of this embodiment, the discrimination circuit 4 is, for example, a retrigger type monomultivibrator circuit. The period in which the determination circuit 4 holds the output by one trigger is, for example, the normal digital period signals CLK1 and CLK.
2, about 1.1 times the cycle of the detection signal DET when CLK3 is input. Therefore, the discrimination circuit 4
Is a digital periodic signal CLK1 when the detection signal DET coming after being reset by an external reset signal RST lacks a pulse with its original period.
~ Outputs an abnormal output signal ERR indicating an abnormality of CLK3.

The detection signal DET, which is the output from the comparison circuit 3, has a non-significant level that is not originally present when an abnormality occurs, but since the detected signal is a digital periodic signal such as a clock signal, The level cannot be determined in synchronization with a clock signal or the like. for that reason,
For example, there is a need for the determination circuit 4 configured by a retrigger type mono-multivibrator circuit for determining an abnormality based on the time change of the detection signal DET from the comparison circuit 3.

FIG. 2 shows a normal digital periodic signal CLK1.
2 shows a timing chart of each part in FIG. 1 when ˜CLK3 is input. In FIG. 2, the frequency of the digital periodic signals CLK1, CLK2, CLK3 is 1: m:
There is a relationship of n = 2: 1: 1, and the digital periodic signal CLK
The phase 0 of 1 matches the phases π / 2 and 3π / 2 of the digital periodic signal CLK2, and the digital periodic signal CLK3 lags behind the digital periodic signal CLK2 having the same frequency by π / 2.

Here, each counter circuit 21a, 22a,
23a, hexadecimal, ternary, which satisfy the relationship of 2: 1: 1,
A ternary counter circuit (rising trigger type) is applied. From the above-mentioned phase relationship, for example, the decoder circuit 21b that decodes the count values "4" and "5" is applied, and the decoder circuits 22b and 23b that decode the count value "2" are applied. To be done.

As described above, each counter circuit 21a,
22a and 23a are reset signals RST shown in FIG.
2 (b), after being reset after being given
Corresponding digital periodic signal CL shown in (c) or (d)
Whenever K1, CLK2, and CLK3 are given, FIG.
The count value is updated like the number attached to (b), (c) or (d). In the case of FIG. 2, since the digital periodic signals CLK1, CLK2, and CLK3 are normal, that is, the frequency and the phase have a predetermined relationship with the other digital periodic signals, the decoder circuits 21b and 22b.
2b and 23b, as shown in FIG. 2 (e), (f) or (g), the period / phase operation signal OP having the same frequency (period) and overlapping in a period having a narrow significant level period.
1, OP2, OP3 are output. As a result, as shown in FIG. 2H, the comparison circuit (AND circuit) 3 also outputs the detection signal DET having a frequency equal to the frequency (cycle) thereof and having a narrow significant level period. As a result, the discrimination circuit 4 is repeatedly retriggered at a predetermined cycle,
As shown in FIG. 2 (i), the abnormal output signal ERR is always normal (L level).

FIG. 3 shows three kinds of digital periodic signals CLK1 to CLK3 which should be in the predetermined relationship described with reference to FIG.
Of these, a timing chart of each part when the digital periodic signal CLK1 becomes abnormal is shown. The abnormality in FIG. 3 is an abnormality in which the frequency becomes low (the cycle becomes long).

Each of the counter circuits 21a, 22a and 23a is once reset by being supplied with the reset signal RST shown in FIG. 3 (a), and then the corresponding digital circuit shown in FIG. 3 (b), (c) or (d). Periodic signals CLK1, CLK2, C
Each time LK3 is given, the count value is updated like the numbers added to FIG. 3 (b), (c) or (d).
In the case of FIG. 3, since the frequency of the digital periodic signal CLK1 is slower than normal, only the counting operation of the counter circuit 21a becomes slower than normal, so that the operation by the decoder circuit 21b also becomes slower than normal. As a result, even when the other decoder circuits 22b and 22c output the period / phase operation signals OP2 and OP3 of significant levels in an overlapping manner as shown in FIGS. As shown in FIG. 3 (e), the period / phase operation signal OP1 having an insignificant level is output. At this time, the comparison circuit (AND circuit) 3
Outputs a non-significant level detection signal DET (missing a significant pulse), as shown in FIG. Discrimination circuit (eg, retrigger type mono-multivibrator circuit) 4
Does not change to a significant level (retrigger) before a predetermined period of holding the output from the time of the previous trigger, so as shown in FIG. 3I, the abnormal output signal ERR becomes abnormal (H Level).

The abnormal output signal ERR indicating such an abnormal state is latched by, for example, a latch circuit and is given to a device such as a display device corresponding to the occurrence of an abnormal condition.

As described above, according to the first embodiment,
Anomaly detection configuration is designed by detecting the abnormality of even one of the input digital periodic signals by the unified configuration instead of individually detecting the abnormality of each input digital periodic signal. It can be as simple as shown in FIG. Further, the configuration for aligning the cycle and phase information of a plurality of digital cycle signals is also composed of a counter circuit and a decoder circuit, and adjustment is not necessary or can be performed easily. Further, instead of detecting abnormality of other digital periodic signals with reference to one digital periodic signal, all digital periodic signals can be handled in the same manner.

Next, a second embodiment of the present invention will be described in detail with reference to the drawings. FIG. 4 is a block diagram showing the configuration of the second embodiment, which is the same as FIG.
Corresponding reference numerals are attached.

The digital periodic signal abnormality detection circuit 1A of the second embodiment is provided with a configuration capable of specifying a digital periodic signal relating to an abnormality in addition to the configuration of the first embodiment.

Such a specific configuration is the inverter circuits 51, 52, 53 and the AND circuits 61, 62, 63 provided corresponding to the respective digital periodic signals CLK1, CLK2, CLK3.

Each inverter circuit 51, 52, 53 inverts the period / phase manipulation signals OP1, OP2, OP3 output from the corresponding period / phase manipulation circuit 21, 22, 23, and corresponding AND circuits 61, 62. , 63, and each AND circuit 61, 62, 63 takes the logical product of the inverted period / phase operation signal and the abnormality detection signal ERR to clarify the digital periodic signal in which an abnormality has occurred. , ERR2, ERR3 are output.

The maximum trigger interval at which the discriminating circuit (for example, the retrigger type mono-multivibrator circuit) 4 maintains the output level is set to the normal digital period signals CLK1 and CLK.
2. If the selection is made slightly longer (for example, about 1.1 times) than the cycle of the detection signal DET when CLK3 is input,
As shown in FIG. 3 described above, at the timing when the abnormality detection signal ERR changes to a significant level indicating an abnormality, the cycle / phase operation signal (OP1) corresponding to the digital cycle signal (CLK1) in the abnormal state is different from other signals. Often they have different non-significant L levels. Therefore, the above-described inverter circuits 51, 52, 53 and the AND circuit 6
1, 62 and 63, the abnormal signal specifying signals ERR1 and E that can almost specify the digital periodic signal in the abnormal state.
RR2 and ERR3 can be obtained.

Since the abnormality detection signal ERR and the period / phase operation signals OP1, OP2, OP3 are not synchronized, the abnormality signal specifying signals ERR1, ERR2, ER are used.
The accuracy of R3 is not so high.

According to the second embodiment, with a simple structure,
It is possible to obtain the same effect as that of the first embodiment in that it is possible to detect abnormalities of a plurality of types of digital periodic signals, and that there is almost no need for adjustment points, and it is possible to specify the digital periodic signals related to abnormalities to some extent. Obtainable.

The digital periodic signal to be detected by the anomaly according to the present invention is not limited to the use for synchronization, and the duty ratio is 5 as shown in FIGS. 2 and 3.
It is not limited to 0%. Furthermore, the number of digital periodic signals related to abnormality detection is not limited to three, and may be two or four or more.

The system in which the circuit of the present invention can be used is not limited to the exchange system or the computer system, and may be a system having another digital processing configuration such as a television receiver.

In the above embodiment, the period / phase operating circuit is provided for each digital periodic signal. However, the same operation as described above can be performed even if the period / phase is not operated to the comparator circuit 3. For digital periodic signals capable of performing various operations, the corresponding period / phase manipulation circuit can be omitted.

The details of the comparison circuit 3 and the discrimination circuit 4 are not limited to those in the above embodiment. The logical operation configuration of the comparison circuit 3 changes in each cycle depending on the selection of the significant level side of the phase operation signal. The discriminating circuit 4 may also discriminate the periodicity of the detection signal DET based on the original oscillation clock signal from the crystal oscillation circuit.

[0046]

As described above, according to the present invention, a plurality of digital periodic signals are input, the frequencies and / or phases of at least one digital periodic signal are manipulated, and significant level periods having the same frequency are overlapped. Cycle / phase operating means for outputting a plurality of cycle / phase operating signals, comparing means for detecting the coincidence of cycles and phases of all cycle / phase operating signals output from the cycle / phase operating means, and this comparing means Since it is provided with a determination means for determining that one or more digital periodic signals have an abnormality based on the detection signal from, the abnormality of a plurality of types of digital periodic signals is detected with a simple configuration. In addition, it is possible to realize a digital periodic signal abnormality detection circuit that has few adjustment points.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment.

FIG. 2 is a timing chart of each part of the first embodiment in a normal state.

FIG. 3 is a timing chart of each part when an abnormality occurs in the first embodiment.

FIG. 4 is a block diagram showing a configuration of a second embodiment.

[Explanation of symbols]

CLK1 to CLK3 ... Digital periodic signals, 21 to 23 ...
Period / phase operation circuit, 21a to 23a ... Counter circuit,
21b to 23b ... Decoder circuit, 3 ... Comparison circuit, 4 ... Determination circuit, 51-53 ... Inverter circuit, 61-63 ... AND circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G06F 1/04 302 Z 11/00 310 J

Claims (2)

[Claims] 1. A plurality of digital periodic signals having a specific relation to frequency and / or phase are input, at least one or more digital periodic signals are manipulated in frequency and / or phase, and significant level periods having the same frequency overlap each other. The period / phase operating means that outputs a plurality of period / phase operating signals corresponding to each digital periodic signal and the period and phase of all the period / phase operating signals output from the period / phase operating means. It is characterized in that it comprises a comparing means for detecting, and a judging means for judging and outputting the abnormality when one or more digital periodic signals are abnormal based on the detection signal from the comparing means. Abnormality detection circuit for digital periodic signals. 2. An abnormal signal specifying signal forming means for forming a signal for specifying an abnormal digital periodic signal based on the logical level of each cycle / phase operation signal at the timing when the judging means has judged that the abnormality has occurred. An abnormality detection circuit for a digital periodic signal according to claim 1, characterized in that.