JP2606569B2 - Frame pulse output monitoring circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output monitoring circuit for monitoring an abnormal output of a plurality of frame pulse generation circuits in a circuit using a plurality of clock signals and frame pulse signals inside a transmission device or the like.

[0002]

2. Description of the Related Art A conventional frame pulse output monitoring circuit will be described with reference to FIG.

A conventional frame pulse output monitoring circuit is composed of (n + 1) types (n) output from a clock generation circuit 40.
Performs an output abnormality monitoring by counting the period of the frame pulse by a timer circuit 41-0~41-n for each of the frame pulse signal P ₀ to P _n a positive integer).

When the output result of the timer circuits 41-0 to 41-n is input to the logic circuit 42, if any of the frame pulses is abnormal, the output of the corresponding timer circuit is changed from low level to high level. The logic circuit changes to the level, and an alarm signal is output from the logic circuit.

The above-described conventional frame pulse output monitoring circuit requires one circuit (mono multivibrator circuit or the like) for detecting a frame pulse abnormality for one frame pulse signal line. Therefore, when monitoring a plurality of types of frame pulse signals, the number of monitoring circuits corresponding to the number of frame pulse signal lines is required, and the circuit scale becomes extremely large.

On the other hand, a clock pulse monitoring circuit aimed at reducing the circuit scale is disclosed in, for example, Japanese Patent Application Laid-Open No. 61-281.
No. 766. Simply put, this clock pulse monitoring circuit is a synchronization detection circuit that continuously detects the time at which all types of clock pulses are simultaneously detected, and the periodicity of the detection signal obtained by the synchronization detection circuit. And a periodicity inspection circuit for inspecting.

This clock pulse monitoring circuit needs to assume that a plurality of types of clock pulses are obtained from a common source oscillator by frequency division. Then, based on the principle that a least common multiple of the period of a plurality of kinds of clock pulses When t _a, it is possible to detect all of the clock pulses at the same time every time t _a.

[0008]

However, since this clock pulse monitoring circuit merely inputs a plurality of types of clock pulses to an AND gate to perform simultaneous detection, it detects abnormalities such as a phase shift. Is effective, but has the following disadvantages.

That is, even if one kind of clock pulse among the plural kinds of clock pulses has an abnormality such as a missing pulse or a continuous interruption, it cannot be detected.

It is therefore an object of the present invention to provide a clock pulse monitoring circuit which is effective not only in reducing the circuit scale but also in detecting an abnormality other than an abnormality such as a phase shift.

[0011]

Means for Solving the Problems In order to solve the problems described above, the frame pulse output monitoring circuit of the present invention, another
In a circuit for generating and outputting frame pulse signals having the same cycle and different phases from the 0th to the nth (n is a positive integer), all outputs of the 0th to the nth frame pulse signals are input. A counter circuit that counts the number of outputs of all other frame pulses based on the phase of one frame pulse among the 0th to nth frame pulse signals, and outputs a pulse signal when a predetermined calculated value is reached; And a timer circuit for counting the period of the pulse signal output from the counter circuit and determining whether or not a predetermined time is satisfied.

The counter circuit receives all outputs of the 0th to nth frame pulse signals as inputs (n +
1) A (n + 1) -ary counter that repeats counting, and a decode that decodes the contents of the n-th count of the (n + 1) -ary counter and outputs the pulse signal when the (n + 1) -th frame pulse is input from the start of counting. A timer circuit comprising a mono-multivibrator circuit for monitoring a cycle of the pulse signal from the decode circuit.

[0013]

Next, an embodiment of a frame pulse output monitoring circuit according to the present invention will be described with reference to FIG. FIG.
FIG. 2 is a block diagram of an embodiment of a frame pulse output monitoring circuit according to the present invention. Clock generation circuit 10 for generating (n + 1) kinds of frame pulse signals P _{0 to} P _n having different phases
Are output to the counter circuit 11. The counter circuit 11 counts (n + 1) pulses from the phase of one frame pulse out of the (n + 1) frame pulse signals as a counting base point, and (n + 1) total pulses of (n + 1) frame pulse signals When it is confirmed that is input, a pulse signal is output. Since the pulse signal output from the counter circuit 11 is synchronized with the cycle of the input frame pulse signal, the cycle is counted by the timer circuit 12, and when the cycles do not match, it is determined that there is an abnormality and an alarm is issued. Generate a signal.

FIG. 2 shows an example of a circuit block in the case where there are three types of frame pulse signals, and an operation time chart thereof is shown in FIG.

The circuit block shown in FIG. 2 will be described below. This block diagram shows a case where there are three types of frame pulse signals having different phases. In this case, n is 2. The ternary counter 21 is a counter that counts the pulse inputs of three frame pulse signals P ₀ , P ₁ , and P _{2 having} different phases. The ternary counter 21 is initialized by the input of the frame pulse signal P ₀ , and receives other frame pulse signals. It counts up for each pulse input of P ₁ and P ₂ , stops counting when it counts 3, and holds the count contents. Decode circuit 22
Decodes the content immediately before the third count of the ternary counter 21, that is, “2”, and outputs a pulse signal in this state at the time of input of the third frame pulse.
The mono-multi vibrator circuit 23 includes a decoding circuit 22
Is a circuit for monitoring the period of the pulse signal. FIG. 3 is FIG.
4 is a time chart showing an operation state of each part of the circuit block diagram of FIG.

As is apparent from this specific example, generally,
When targetting (n + 1) types of frame pulse signals P _{0 to} P _n, the ternary counter 21 is an (n + 1) -base counter, and the decode circuit 22 is an n- (n + 1) -base counter.
The count value may be decoded to output a pulse signal when the (n + 1) th frame pulse is input.

[0017]

As described above, the present invention counts the pulses of all the other frame pulse signals starting from the phase of one frame pulse signal among a plurality of frame pulse signals and reaches a predetermined count value. Then, a monitoring circuit is configured by a counter circuit that generates and outputs a pulse signal, and a timer circuit that counts the period of the output pulse signal of the counter circuit and determines whether a predetermined time is satisfied. On the other hand, there is an effect that the output monitoring circuit can be miniaturized, and even if the number of outputs of the frame pulse increases, it can be configured with the minimum number of circuits. In addition, if any one of the plurality of frame pulse signals has a missing pulse or a continuous interruption, it can be detected as abnormal.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a multiple frame pulse output monitoring circuit of the present invention.

FIG. 2 is a circuit block diagram illustrating an example of an output monitoring circuit according to the present invention.

FIG. 3 is a time chart illustrating an operation state of the output monitoring circuit of FIG. 2;

FIG. 4 is a block diagram showing one embodiment of a conventional clock output monitoring circuit.

[Explanation of symbols]

 Reference Signs List 10 clock generation circuit 11 counter circuit 12 timer circuit

Claims (2)

(57) [Claims] 1. The 0th to the nth (n) having the same period as each other.
Is a positive integer) and outputs all the outputs of the 0th to nth frame pulse signals, and outputs all the outputs of the 0th to nth frame pulse signals. The number of outputs of all other frame pulses is counted based on the phase of one frame pulse among them, and when a predetermined count value is reached, a counter circuit that outputs a pulse signal and a period of the pulse signal output from the counter circuit are counted. A frame pulse output monitoring circuit, comprising: a timer circuit for determining whether a predetermined time is satisfied. 2. The frame pulse output monitoring circuit according to claim 1, wherein the counter circuit receives all outputs of the 0th to nth frame pulse signals as inputs and repeats (n + 1) counts. , The (n +
1) a decoding circuit that decodes the contents of the n-th count of the binary counter and outputs the pulse signal when the (n + 1) th frame pulse is input from the start of counting, and the timer circuit A frame pulse output monitoring circuit comprising a monomultivibrator circuit for monitoring a period of the pulse signal.