JPH04306930A - Clock fault detector - Google Patents

Abstract

PURPOSE:To quickly and surely detect clock interrupt and clock fluctuation by deciding the state of a clock depending whether or not the number of times of occurrence of clock state changes extracted from a transmission line is contained within a period of a reference clock in a terminal equipment. CONSTITUTION:Frequency dividers 11, 12 frequency-divide a clock CK1 extracted from a transmission line and a reference clock CK2 in a terminal equipment to output CKA, CKB. The CKB is inputted to a timing generator 61 and used for a reference of a reset pulse and a timing pulse. Counters 21, 22 count the number of leading edges and the number of trailing edges of the CKA between adjacent reset pulses and they are added by an adder 31, which outputs the sum as the number of times N1 of state changes of the CKA. If frequencies of the CKA, CKB are let to be fA, fB, then the relation of N2<=N1(N2+1) is established, where N2 is a natural number having relations of N2.fB<=2.fA <(N2+1).fB. A comparator 41 outputs an error signal in the case of N1>(N2+1) and a comparator 42 outputs an error signal in the case of N1<N2. The error signal is used for a reference of an error flag output EF by a discriminator 51.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock abnormality detector used for detecting a clock stabilization state when a terminal device is powered on and detecting a clock disconnection when a transmission line is disconnected.

0002

2. Description of the Related Art A clock disconnection detection circuit is used to detect an abnormality in a clock when a reference clock in a terminal is synchronized with a clock extracted from a transmission path. In this way, the beat frequency between the clock extracted from the transmission path and the reference clock in the terminal device is determined, and the beat frequency is counted and compared to detect an abnormality.

0003

[Problem to be Solved by the Invention] In the conventional method, if two clocks are not in an integral multiple relationship with each other, it is necessary to detect the beat frequency after dividing the frequency to the greatest common divisor of both clocks. Therefore, the detection cycle becomes long, making it difficult to detect clock interruptions, significant jitter, etc. early and reliably.

[0004] The present invention aims to improve this problem and to provide a means for quickly and reliably detecting clock interruptions and clock fluctuations.

[0005]

[Means for Solving the Problems] The clock abnormality detector of the present invention is a clock abnormality detector for a terminal device that synchronizes a reference clock in the terminal device with a clock extracted from the transmission path. Extracted clock (C
The output CKA (
Using the frequency fA) and the output CKB (frequency fB) obtained by dividing the other by the frequency division ratio M2 (however, M1, M2
is any natural number satisfying 2・fA > fB), CK
A counter 1 that counts and outputs the rising edge of CKA and is reset by a reset pulse, a counter 2 that counts and outputs the falling edge of CKA and is reset by the reset pulse, and the outputs of the counter 1 and counter 2. an adder that adds the sum N1 and outputs the sum N1, the output N1 of the adder, and the value N2 (however, N2
is N2・fB <2・fA <(N2 +1)・f
N1 < N2
a comparator 1 that detects and outputs the output N1 of the adder;
and (N2 +1), detects and outputs N1>(N2 +1), and inputs the outputs and timing pulses of the comparators 1 and 2 to determine the state of the clock and indicate the state. A determiner that outputs a flag and a CKB
The present invention is characterized by comprising a timing generator that takes in the reset pulse and the timing pulse.

[0006] Furthermore, the clock anomaly detector of the present invention uses the output N1 of the adder and a certain natural number N3 (however, N3
is, the fractional part M of 2・fA /fB is M<0.5
If N3 = (N2 +1), if M>0.5 then N3 =
Comparator 3 that compares N2 ) and detects N1 = N3
If the output of the comparator 3 is N1 ≠ N3 at the timing of the timing pulse outputted by the timing generator, the counter 2 counts up, and if N1 = N3, the counter 2 is reset, and at the timing of the timing pulse, the comparator 3
When the output of counter 2 is N1 = N3, the output of counter 2 is N4
Compare (K-1) (where K is K<1 when M<0.5
/M<(K+1), when M>0.5, K<1/(M-0.
5) <(K+1), a natural number), and N4 <(K-1)
), the comparator 4 compares N4 and K, and N
A comparator 5 that detects >K, and a determiner that determines the state of the clock from the outputs and timing pulses of the comparators 1, 2, 4, and 5, and outputs a flag indicating the state. characterized by having

[0007]

Embodiment FIG. 1 is a block diagram showing a first embodiment of the present invention.

[0008] The frequency dividers 11 and 12 each have a frequency of 1/M1.
, 1/M2, which divides the frequencies of CK1 and CK2 and outputs CKA and CKB. this house,
CKB becomes an input to the timing generator 61 and serves as a reference for reset pulses and timing pulses. On the other hand, C
KA becomes a clock for counters 21 and 22.

A counter 21 counts and outputs the number of rising edges of CKA between adjacent reset pulses, and a counter 22 counts and outputs the number of falling edges.

The outputs of the counters 21 and 22 are sent to the adder 3
1 and output as the number N1 of state changes of CKA between adjacent reset pulses.

Here, the reset pulse interval is CKB
Since it is determined by the frequency of , when the frequencies of CKA and CKB are respectively fA and fB, N2 ・
For a natural number N2 such that fB <2·fA <(N2 +1)·fB, the relationship N2 <N1 (N2 +1) holds true. Comparators 41 and 42 are N1 and N
2 satisfies this relationship. If N1 > (N2 + 1), the comparator 42 determines whether N1 satisfies this relationship.
If 1<N2, an error signal is output.

The error signal is taken into the determiner 51 and serves as a reference for the error flag output EF. If CKA is higher than the original frequency or CKB is lower than the original frequency, N1 > (N2 + 1) and the comparator 41 outputs an error signal, so EF outputs an error signal. Conversely, if CKA is lower than the original frequency or CKB is higher than the original frequency, N1 < N2,
Since comparator 42 outputs an error signal, EF outputs an error signal.

[0013] Here, consider the temporal change in the output of the comparator. Immediately after the reset pulse, counters 21 and 2
2 is in a reset state, so N1 = 0. Therefore, since N1 <N2, the comparator 42 outputs an error signal. Each time a change in the state of CKA occurs, either counter 21 or 22 counts up, and therefore N1 also increases by one. Then, when N1 = N2, the error output of the comparator 42 stops, and the stopped state continues until the next reset pulse. That is, the fact that the comparator 42 outputs an error signal is a phenomenon that occurs every time a reset signal is generated due to the operation of the circuit, and as such does not have a one-to-one correspondence with an abnormality in the clock. Therefore, the abnormality determination of N1 <N2 needs to be performed in synchronization with the timing pulse immediately before the end of one cycle of CKB, that is, immediately before the next reset pulse.

On the contrary, the comparator 41 calculates that N1 >(N2 +
1) is detected, an error signal is output, but this state is based on the definition of N1 and N2: N2 < N1 < (N
2 + 1), this cannot occur as long as CKA and CKB are in a normal state. Furthermore, N1 > (N2
One of the causes of +1) is the possibility that CKB is disconnected, and in this case, no timing pulse is generated. Therefore, for abnormality determination in the case of N1 > (N2 +1), the EF needs to output an error signal at the time when the comparator 41 outputs the error signal, regardless of the timing pulse.

FIG. 2 is an example of a timing chart of the first embodiment.

The outputs of the comparator and determiner are shown when the frequency of CKB changes with respect to CKA (101) at a certain frequency.

(a) shows the case where the original frequency relationship exists, and shows CKB (111) and its corresponding timing pulse (121) and reset pulse (131). (b) is a case where the frequency of CKB (112) is higher than normal, and the timing pulse (122)
) when N1 < N2, the error signal output (142) of the comparator 42 becomes 'H' level, so the determiner 51 determines that the clock is abnormal and outputs the error flag (152). becomes 'H' level. (c) is a case where the frequency of CKB (113) is lower than normal, and when N1 > (N2 +1), the comparator 4
1's output (163) becomes 'H' level, and the determiner 51
determines that the clock is abnormal and outputs an error flag (153
) becomes 'H' level.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

In this embodiment, the CK between timing pulses is
M is the fraction of the number of state changes of A (M is 2・fA/
(equal to the fractional part of fB) is used to improve the accuracy of clock abnormality detection. That is, if M<0.5, K<
Considering a natural number K such that 1/M<(K+1), the number of state changes of CKA between adjacent timing pulses is (N2 +1) because the timing pulse is K.
or once out of (K+1) times, M>0.5
In the case of , considering a natural number K such that K<1/(M-0.5)<(K+1), the number of state changes of CKA between adjacent timing pulses is N2 times. occurs once out of K or (K+1) times.

In addition to the circuit of the first embodiment, the actual circuit includes the output N1 of the adder 36 and the natural number N3 (however, N3
is a comparator 48 that compares (N2 + 1) when M<0.5 and N2 when M>0.5, and the output of the comparator 48 goes to 'H' level (N1) at the falling edge of the timing pulse.
=N3), and counts up when it is at the 'L' level, and when the output of the comparator 48 is at the 'H' level at the falling edge of the timing pulse, the output of the counter 76 is N5. and (K-1), and outputs an error signal if N4 <(K-1); and a comparator 78, which compares N4 and K and outputs an error signal if N4 > K. The condition for determining clock abnormality is that the comparator 77 is used as an input to the determiner 56.
and 78 outputs are added.

FIG. 4 is an example of a timing chart of the second embodiment.

The figure shows changes in the outputs of the comparator and determiner when the frequency of CKA changes with respect to a timing pulse (301) generated from CKB of a certain frequency. (a) shows the case where CKA (311) is at the original frequency, and the output (321) of the comparator 48 repeats 'H' level and 'L' level every other time at the falling edge of the timing pulse. There is. In (b), CKA (312
) is higher than normal, the output of comparator 48 (3
22) becomes 'H' level twice in a row at the falling edge of the timing pulse, the value N4 of the counter 76
= 0, N4<(K-1) holds true, the output (332) of the comparator 77 outputs an error signal, and the error flag output (352) of the determiner 56 also becomes 'H' level. Become. In (c), since the frequency of CKA (313) is higher than normal, the output N4 of the counter 76 becomes N4 =
3, N4 > K (because K = 2), so the error output (343) of the comparator 78 becomes 'H' level, and at the same time, the output (353) of the determiner 56 also becomes 'H' level. Become.

[0023]

[Effects of the Invention] As described above, according to the configuration of the clock abnormality detector of the present invention, it is possible to detect clock abnormalities that are not related to integral multiples in a short time, or to detect clock stability. This has the effect of greatly contributing to early start-up of the device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram showing a timing chart for explaining the operation of the circuit in FIG. 1;

FIG. 3 is a block diagram showing another embodiment of the present invention.

FIG. 4 is a diagram showing a timing chart for explaining the operation of the circuit in FIG. 3;

[Explanation of symbols]

11, 12, 16, 17 Frequency divider 21, 22, 26, 27 Counter 31, 36 Adder 41, 42, 46, 47, 48 Comparator 51, 56
Determiner 41, 42, 46, 47, 48 Comparator 51, 56
Determiner 61, 66 Timing generator 76, 77 Detector 101, 311, 312, 313 CKA 111, 1
12,113 CKB 121,122,123,301 Timing pulse 131,132,133 Reset pulse 142
Comparator 1 output 152, 153 Determiner output (EF: error flag)
163 Comparator 2 output 321, 322, 323 Comparator 3 output 332 Comparator 4 output 343 Comparator 5 output

Claims (2)

[Claims] Claim 1: In a clock abnormality detector for a terminal device that synchronizes a reference clock in the terminal device with a clock extracted from the transmission path, the clock (CK1) extracted from the transmission path and the reference clock in the terminal device are used. (CK2
) is divided by the frequency division ratio M1.
A (frequency fA) and the output CKB (frequency fB) obtained by dividing the other by the frequency division ratio M2 (however, M1
, M2 is any natural number that satisfies 2・fA > fB)
, a counter 1 that counts and outputs the rising edge of CKA and is reset by a reset pulse, a counter 2 that counts and outputs the falling edge of CKA and is reset by the reset pulse, and a counter 1 and a counter 2 that count and output the rising edge of CKA and are reset by the reset pulse. an adder that adds the outputs and outputs the sum N1; the output N1 of the adder; and the value N2 (where N2 is N2 ・fB < 2 ・fA < (N2 + 1) ・fB
a comparator 1 that compares N1 < N2 (any natural number that satisfies) and outputs the result; and a comparator 1 that compares the output N1 of the adder with (N2 + 1) and detects and outputs N1 > (N2 + 1). 2, a determiner that inputs the outputs and timing pulses of the comparators 1 and 2, determines the state of the clock, and outputs a flag indicating the state; and a determiner that takes in CKB and generates the reset pulse and timing pulse. A clock anomaly detector comprising a timing generator. [Claim 2] In the clock abnormality detector of Claim 1, the output N1 of the adder and a certain natural number N3 (N3 is such that the decimal part M of 2·fA /fB is such that M<
If 0.5, N3 = (N2 +1), if M>0.5, N
3 = N2) and detects N1 = N3, and the output of the comparator 3 at the timing of the timing pulse output from the timing generator is N1 ≠ N3.
If N1 = N3, the counter 2 counts up, and if N1 = N3, it resets. When the output of the comparator 3 is N1 = N3 at the timing of the timing pulse, compare the output N4 of the counter 2 with (K-1) (however, K is When M<0.5, K
<1/M<(K+1), when M>0.5, K<1/(M-
0.5) < (K + 1)), and N4 < (K
-1), a comparator 5 that compares N4 and K and detects N4 > K, and outputs and timings of the comparators 1, 2, 4, and 5. A clock abnormality detector characterized by having a determiner that determines the state of a clock from pulses and outputs a flag indicating the state.