JPH0794664A - Lead frame and semiconductor device employing it - Google Patents
Lead frame and semiconductor device employing itInfo
- Publication number
- JPH0794664A JPH0794664A JP5237763A JP23776393A JPH0794664A JP H0794664 A JPH0794664 A JP H0794664A JP 5237763 A JP5237763 A JP 5237763A JP 23776393 A JP23776393 A JP 23776393A JP H0794664 A JPH0794664 A JP H0794664A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- semiconductor device
- inner lead
- insulating member
- bonding wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、リードフレームおよび
それを用いた半導体装置、特に、多ピン形樹脂モールド
パッケージ用のリードフレームおよびそれを用いた半導
体装置に適用して有効な技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame and a semiconductor device using the same, and more particularly to a technique effective when applied to a lead frame for a multi-pin type resin mold package and a semiconductor device using the same. is there.
【０００２】[0002]
【従来の技術】半導体装置用のリードフレームにおいて
は、ペレットの新規設計に伴い、リードフレームも専用
設計で開発している。これは、半導体装置のリードフレ
ームが多ピン化するにしたがってインナリード先端のピ
ッチが狭くなるので、ボンディングワイヤが隣接するイ
ンナリードと接触するのを防止するためである。2. Description of the Related Art In a lead frame for a semiconductor device, a lead frame has been developed with a dedicated design in accordance with a new design of pellets. This is to prevent the bonding wires from coming into contact with the adjacent inner leads because the pitch of the inner lead tips becomes narrower as the lead frame of the semiconductor device has more pins.
【０００３】[0003]
【発明が解決しようとする課題】ところが、このペレッ
ト毎によるリードフレームの専用設計であると、ペレッ
トが新規設計となる場合は、リードフレームも新規設計
しなければならず、そのために、製品開発が長期化して
しまい、また、リードフレームの製品開発費も増加して
しまう。However, when the lead frame is designed exclusively for each pellet, if the pellet is a new design, the lead frame must also be newly designed, which results in product development. This leads to a longer period of time, and lead frame product development costs also increase.
【０００４】本発明の目的は、ボンディングワイヤと隣
接するインナリードフレームとの接触を防止することに
よって、リードフレームを共通化できる構造のリードフ
レームおよびそれを用いた半導体装置を提供することに
ある。It is an object of the present invention to provide a lead frame having a structure in which the lead frame can be shared by preventing the contact between the bonding wire and the adjacent inner lead frame, and a semiconductor device using the same.
【０００５】本発明の前記並びにその他の目的と新規な
特徴は、本明細書の記述および添付図面から明らかにな
るであろう。The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
【０００６】[0006]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下のとおりである。Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.
【０００７】すなわち、本願の１つの発明は、半導体チ
ップの組立に用いられるリードフレームにおいて、イン
ナリードの端部の少なくとも上面に、絶縁部材を固着す
ることにより、絶縁部材を、インナリードとボンディン
グワイヤとの間に介設したものである。That is, according to one invention of the present application, in a lead frame used for assembling a semiconductor chip, an insulating member is fixed to at least an upper surface of an end portion of the inner lead so that the insulating member is bonded to the inner lead and a bonding wire. It was installed between and.
【０００８】また、本願の他の発明は、絶縁部材が、複
数のインナリードの端部を覆うように延在されたテープ
状または枠状の絶縁部材からなるものである。In another invention of the present application, the insulating member is a tape-shaped or frame-shaped insulating member extending so as to cover the end portions of the plurality of inner leads.
【０００９】さらに、本願の他の発明は、インナリード
の端部の厚さが、前記インナリードがボンディングされ
る部分よりも薄く成形されているものである。Further, according to another invention of the present application, the thickness of the end portion of the inner lead is formed thinner than the portion to which the inner lead is bonded.
【００１０】[0010]
【作用】上記のような構成の半導体装置によれば、ボン
ディングワイヤと隣接するインナリードの接触を絶縁部
材が防止するために、リードフレームを新規に設計開発
しなくても、従来のリードフレームを使用することがで
きる。According to the semiconductor device having the above-described structure, the insulating member prevents the contact between the bonding wire and the inner lead adjacent to the bonding wire, so that the conventional lead frame can be manufactured without newly designing and developing the lead frame. Can be used.
【００１１】それにより、リードフレームの新たな設計
開発が不要となり、設計開発期間の短縮および設計開発
費の削減ができる。This eliminates the need for new design and development of the lead frame, shortening the design and development period and reducing the design and development cost.
【００１２】また、同じリードフレームを複数の半導体
装置に使用できるので、リードフレームの原価低減を行
うことができる。Since the same lead frame can be used for a plurality of semiconductor devices, the cost of the lead frame can be reduced.
【００１３】[0013]
【実施例】以下、本発明の実施例を詳細に説明する。EXAMPLES Examples of the present invention will be described in detail below.
【００１４】（実施例１）図１（ａ）は、本発明の実施
例１によるＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇ
ｅ）形の半導体装置の要部の平面図、（ｂ）は、本発明
の実施例１によるＱＦＰ形の半導体装置の要部の断面図
である。(Embodiment 1) FIG. 1A shows a QFP (Quad Flat Pack) according to a first embodiment of the present invention.
FIG. 3B is a plan view of an essential part of an e) type semiconductor device, and FIG. 1B is a sectional view of an essential part of a QFP type semiconductor device according to the first embodiment of the present invention.
【００１５】本実施例１において、半導体チップ１を搭
載するためのリードフレーム２は、複数のリードで構成
されているインナリード２ａや半導体チップ１のボンデ
ィング位置であるダイパッド２ｂ等が形成され、それら
のパターンが数個以上連結された金属製のリボン構造よ
りなるものである。In the first embodiment, the lead frame 2 for mounting the semiconductor chip 1 is formed with an inner lead 2a composed of a plurality of leads, a die pad 2b which is a bonding position of the semiconductor chip 1, and the like. The pattern is composed of a metal ribbon structure in which several patterns are connected.
【００１６】このリードフレーム２は、前記パターンを
形成するための原画であるマスクをもとにエッチングを
行い、不要な金属部分を腐食させることによって成形す
る。The lead frame 2 is formed by etching based on a mask which is an original image for forming the pattern and corroding unnecessary metal parts.
【００１７】そして、前記インナリード２ａの端部に、
例えば、ポリイミド系樹脂で形成された絶縁部材３が、
所定の幅で、ポッティングまたはコーティングされる。At the end of the inner lead 2a,
For example, the insulating member 3 formed of a polyimide resin is
It is potted or coated with a predetermined width.
【００１８】次に、前記リードフレーム２上に、半導体
チップ１をボンディングした後、前記半導体チップ１上
に形成された電極であるボンディングパッド１ａとイン
ナリード２ａとを、ボンディングワイヤ４によって電気
的に接続する。Next, after the semiconductor chip 1 is bonded onto the lead frame 2, the bonding pad 1a, which is an electrode formed on the semiconductor chip 1, and the inner lead 2a are electrically connected by the bonding wire 4. Connecting.
【００１９】それにより、本実施例１においては、ボン
ディングワイヤ４とインナリード２ａとの間に絶縁部材
３が介設されることになるので、ボンディングワイヤ４
が隣接する他のインナリード２ａと接触しても、絶縁部
材３によって電気的に絶縁され、ショートすることがな
くなる。As a result, in the first embodiment, since the insulating member 3 is provided between the bonding wire 4 and the inner lead 2a, the bonding wire 4
Even when the other comes into contact with another adjacent inner lead 2a, it is electrically insulated by the insulating member 3 and is not short-circuited.
【００２０】また、図１（ｂ）に示すように、絶縁部材
３が支点となることによって、ボンディングワイヤ４の
張力が増すので、ワイヤループの直進性が向上し、ボン
ディングワイヤ４のたるみを減少することができる。Further, as shown in FIG. 1B, since the insulating member 3 serves as a fulcrum to increase the tension of the bonding wire 4, the straightness of the wire loop is improved and the slack of the bonding wire 4 is reduced. can do.
【００２１】（実施例２）図２（ａ）は、本発明の実施
例２によるＱＦＰ形の半導体装置の要部の平面図、
（ｂ）は、本発明の実施例２によるＱＦＰ形の半導体装
置の要部の断面図である。(Embodiment 2) FIG. 2A is a plan view of a main portion of a QFP type semiconductor device according to Embodiment 2 of the present invention.
(B) is a sectional view of an essential part of a QFP type semiconductor device according to a second embodiment of the present invention.
【００２２】本実施例２においては、図２（ａ）に示す
ように、リードフレーム２をエッチングにより加工成形
する。その後、複数のリードで形成されるインナリード
２ａの端部を、たとえば、ポリイミド系樹脂により形成
されたテープ状の絶縁部材３ａで覆うように延在して設
ける。In the second embodiment, as shown in FIG. 2A, the lead frame 2 is processed and formed by etching. After that, the end portion of the inner lead 2a formed of a plurality of leads is provided so as to extend so as to be covered with a tape-shaped insulating member 3a formed of, for example, a polyimide resin.
【００２３】それにより、本実施例２においても、ボン
ディングワイヤ４とインナリード２ａとの間に絶縁部材
３ａが介設されることになるので、ボンディングワイヤ
４が隣接する他のインナリード２ａと接触しても、絶縁
部材３ａによって電気的に絶縁され、ショートすること
がなくなる。As a result, also in the second embodiment, since the insulating member 3a is interposed between the bonding wire 4 and the inner lead 2a, the bonding wire 4 comes into contact with another adjacent inner lead 2a. Even if it does, it is electrically insulated by the insulating member 3a, and it will not short-circuit.
【００２４】また、この場合においても、図２（ｂ）に
示すように、テープ状の絶縁部材３ａが支点となること
によって、ボンディングワイヤ４の張力が増すので、ワ
イヤループの直進性が向上し、ボンディングワイヤ４の
たるみを減少することができる。Also in this case, as shown in FIG. 2B, since the tape-shaped insulating member 3a serves as a fulcrum, the tension of the bonding wire 4 increases, so that the straightness of the wire loop is improved. The slack of the bonding wire 4 can be reduced.
【００２５】テープ状の絶縁部材３ａの固着方法として
は、絶縁部材３ａの片面に予め接着材を塗布し、熱圧着
等でインナリード２ａの先端部に固着する方法や、イン
ナリード２ａの先端部に予め接着材を塗布しておき、そ
の後テープ状の絶縁部材３ａを固着する方法等がある。As a method of fixing the tape-shaped insulating member 3a, an adhesive material is applied to one surface of the insulating member 3a in advance and the tape is fixed to the tip of the inner lead 2a by thermocompression bonding or the tip of the inner lead 2a. There is a method in which an adhesive material is applied in advance and then the tape-shaped insulating member 3a is fixed.
【００２６】（実施例３）図３（ａ）は、本発明の実施
例３によるＱＦＰ形の半導体装置の要部の平面図、
（ｂ）は、本発明の実施例３によるＱＦＰ形の半導体装
置の要部の断面図である。(Embodiment 3) FIG. 3A is a plan view of a main portion of a QFP type semiconductor device according to Embodiment 3 of the present invention.
(B) is a sectional view of an essential part of a QFP type semiconductor device according to a third embodiment of the present invention.
【００２７】本実施例３においては、図３（ａ）に示す
ように、リードフレーム２をエッチングにより加工成形
する。その後、複数のリードで形成されるインナリード
２ａの端部を、たとえば、ポリイミド系樹脂により形成
された枠状の絶縁部材３ｂによって覆うように、また
は、図４（ａ）に示すようにコーナリード部のみ延在し
て設ける。In the third embodiment, as shown in FIG. 3A, the lead frame 2 is processed and formed by etching. After that, the end portion of the inner lead 2a formed of a plurality of leads is covered with, for example, a frame-shaped insulating member 3b formed of a polyimide resin, or as shown in FIG. Only the part is extended.
【００２８】この枠状の絶縁部材３ｂおよびコーナリー
ド部のみに貼りつけた絶縁部材３ｃの固着方法として
は、絶縁部材３ｂ，３ｃの片面に予め接着材を塗布し、
熱圧着等でインナリード２ａの先端部に固着する方法
や、インナリード２ａの先端部に予め接着材を塗布して
おき、その後絶縁部材３ｂ，３ｃを固着する方法等があ
る。As a method of fixing the frame-shaped insulating member 3b and the insulating member 3c attached only to the corner lead portions, an adhesive is applied in advance on one surface of each of the insulating members 3b and 3c.
There are a method of fixing to the tip end portion of the inner lead 2a by thermocompression bonding, a method of applying an adhesive material to the tip end portion of the inner lead 2a in advance, and then fixing the insulating members 3b and 3c.
【００２９】それにより、本実施例３においても、ボン
ディングワイヤ４とインナリード２ａとの間に枠状の絶
縁部材３ｂまたは絶縁部材３ｃが介設されることになる
ので、ボンディングワイヤ４が隣接する他のインナリー
ド２ａと接触しても、枠状の絶縁部材３ｂまたは絶縁部
材３ｃによって電気的に絶縁され、ショートすることが
なくなる。As a result, also in the third embodiment, the frame-shaped insulating member 3b or insulating member 3c is provided between the bonding wire 4 and the inner lead 2a, so that the bonding wire 4 is adjacent to the bonding wire 4. Even if it contacts another inner lead 2a, it is electrically insulated by the frame-shaped insulating member 3b or the insulating member 3c, and is not short-circuited.
【００３０】また、この場合においても、図３（ｂ），
図４（ｂ）に示すように、枠状の絶縁部材３ｂまたは絶
縁部材３ｃが支点となることによって、ボンディングワ
イヤ４の張力が増すので、ワイヤループの直進性が向上
し、ボンディングワイヤ４のたるみを減少することがで
きる。Also in this case, as shown in FIG.
As shown in FIG. 4B, since the frame-shaped insulating member 3b or the insulating member 3c serves as a fulcrum, the tension of the bonding wire 4 increases, so that the straightness of the wire loop is improved and the slack of the bonding wire 4 is increased. Can be reduced.
【００３１】（実施例４）図５（ａ）は、本発明の実施
例４によるＱＦＰ形の半導体装置の要部の平面図、
（ｂ）は、本発明の実施例４によるＱＦＰ形の半導体装
置の要部の断面図である。(Embodiment 4) FIG. 5A is a plan view of a main portion of a QFP type semiconductor device according to Embodiment 4 of the present invention.
(B) is a sectional view of an essential part of a QFP type semiconductor device according to a fourth embodiment of the present invention.
【００３２】本実施例４においては、図５（ａ）に示す
ように、リードフレーム２をエッチングにより加工成形
した後、複数のリードで形成されるインナリード２ａの
端部２ｃをエッチングの１種であるハーフエッチや圧力
をかけることによって成形するコイニング等によって所
定の薄さに形成する。In the fourth embodiment, as shown in FIG. 5A, after the lead frame 2 is processed and formed by etching, the end portion 2c of the inner lead 2a formed by a plurality of leads is a kind of etching. It is formed to have a predetermined thickness by half-etching or coining for forming by applying pressure.
【００３３】それにより、本実施例４においては、図５
（ｂ）に示すように、インナリード２ａの端部２ｃの厚
さが、インナリード２ａのボンディングポイントよりも
薄く形成されているので、ボンディングワイヤ４が隣接
する他のインナリード２ａと接触を防止することがで
き、ショートすることがなくなる。As a result, in the fourth embodiment, as shown in FIG.
As shown in (b), since the thickness of the end portion 2c of the inner lead 2a is formed thinner than the bonding point of the inner lead 2a, the bonding wire 4 is prevented from coming into contact with another adjacent inner lead 2a. You can do it, and you will not be short-circuited.
【００３４】以上、本発明者によってなされた発明を実
施例に基づき説明したが、本発明は前記実施例に限定さ
れるものでなく、その要旨を逸脱しない範囲で種々変更
可能であることはいうまでもない。The invention made by the present inventor has been described above based on the embodiments. However, the present invention is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. There is no end.
【００３５】たとえば、インナリード２ａの絶縁につい
ては、前記実施例以外のものでもよく、インナリード２
ａの端部を薄く成形した後に、前記インナリード２ａの
端部に、絶縁部材３，テープ状の絶縁部材３ａ，枠状の
絶縁部材３ｂまたは絶縁部材３ｃを固着させてもよい。For example, the insulation of the inner lead 2a may be other than that of the above-mentioned embodiment.
After thinly molding the end portion of a, the insulating member 3, the tape-shaped insulating member 3a, the frame-shaped insulating member 3b, or the insulating member 3c may be fixed to the end portion of the inner lead 2a.
【００３６】[0036]
【発明の効果】本発明によって開示される発明のうち、
代表的なものによって得られる効果を簡単に説明すれ
ば、以下のとおりである。Of the inventions disclosed by the present invention,
The following is a brief description of the effects obtained by the typical ones.
【００３７】（１）本発明によれば、ボンディングワイ
ヤとインナリードとがショートすることを防止すること
ができるので、リードフレームを新規に設計開発しなく
ても良く、従来のリードフレームを使用することができ
る。(1) According to the present invention, it is possible to prevent a short circuit between the bonding wire and the inner lead. Therefore, it is not necessary to newly design and develop the lead frame, and the conventional lead frame is used. be able to.
【００３８】（２）また、上記（１）により、本発明で
は、リードフレームの新たな設計開発が不要となり、設
計開発期間の短縮および設計開発費の削減ができる。(2) Further, according to the above (1), in the present invention, it is not necessary to newly design and develop the lead frame, so that the design and development period can be shortened and the design and development cost can be reduced.
【００３９】（３）さらに、同じリードフレームを複数
の半導体装置に使用できるので、リードフレームの原価
低減が行える。(3) Further, since the same lead frame can be used for a plurality of semiconductor devices, the cost of the lead frame can be reduced.
【図１】（ａ）は、本発明の実施例１によるＱＦＰ形の
半導体装置の要部の平面図、（ｂ）は、本発明の実施例
１によるＱＦＰ形の半導体装置の要部の断面図である。1A is a plan view of a main part of a QFP type semiconductor device according to a first embodiment of the present invention, and FIG. 1B is a sectional view of a main part of a QFP type semiconductor device according to a first embodiment of the present invention. It is a figure.
【図２】（ａ）は、本発明の実施例２によるＱＦＰ形の
半導体装置の要部の平面図、（ｂ）は、本発明の実施例
２によるＱＦＰ形の半導体装置の要部の断面図である。2A is a plan view of a main part of a QFP type semiconductor device according to a second embodiment of the present invention, and FIG. 2B is a cross-sectional view of the main part of a QFP type semiconductor device according to a second embodiment of the present invention. It is a figure.
【図３】（ａ）は、本発明の実施例３によるＱＦＰ形の
半導体装置の要部の平面図、（ｂ）は、本発明の実施例
３によるＱＦＰ形の半導体装置の要部の断面図である。3A is a plan view of a main part of a QFP type semiconductor device according to a third embodiment of the present invention, and FIG. 3B is a cross-sectional view of the main part of a QFP type semiconductor device according to a third embodiment of the present invention. It is a figure.
【図４】（ａ）は、本発明の実施例３によるＱＦＰ形の
半導体装置の要部の平面図、（ｂ）は、本発明の実施例
３によるＱＦＰ形の半導体装置の要部の断面図である。4A is a plan view of a main part of a QFP type semiconductor device according to a third embodiment of the present invention, and FIG. 4B is a cross-sectional view of the main part of a QFP type semiconductor device according to a third embodiment of the present invention. It is a figure.
【図５】（ａ）は、本発明の実施例４によるＱＦＰ形の
半導体装置の要部の平面図、（ｂ）は、本発明の実施例
４によるＱＦＰ形の半導体装置の要部の断面図である。5A is a plan view of a main part of a QFP type semiconductor device according to a fourth embodiment of the present invention, and FIG. 5B is a cross-sectional view of the main part of a QFP type semiconductor device according to the fourth embodiment of the present invention. It is a figure.
１ 半導体チップ １ａ ボンディングパッド ２ リードフレーム ２ａ インナリード ２ｂ ダイパッド ２ｃ 端部 ３ 絶縁部材 ３ａ テープ状の絶縁部材 ３ｂ 枠状の絶縁部材 ３ｃ 絶縁部材 ４ ボンディングワイヤ 1 Semiconductor Chip 1a Bonding Pad 2 Lead Frame 2a Inner Lead 2b Die Pad 2c End 3 Insulation Member 3a Tape Insulation Member 3b Frame Insulation Member 3c Insulation Member 4 Bonding Wire
フロントページの続き (72)発明者 大野 浩 東京都小平市上水本町５丁目22番１号 株 式会社日立マイコンシステム内Front Page Continuation (72) Inventor Hiroshi Ohno 5-22-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Hitachi Microcomputer System Co., Ltd.
Claims (4)
フレームにおいて、インナリードの端部の少なくとも上
面に絶縁部材を設けたことを特徴とするリードフレー
ム。1. A lead frame used for assembling a semiconductor chip, wherein an insulating member is provided on at least an upper surface of an end portion of the inner lead.
ドの端部を覆うように延在されたテープ状または枠状の
絶縁部材からなることを特徴とする請求項１記載のリー
ドフレーム。2. The lead frame according to claim 1, wherein the insulating member is a tape-shaped or frame-shaped insulating member extending so as to cover the end portions of the plurality of inner leads.
フレームにおいて、インナリードの端部の厚さが、前記
インナリードのボンディングされる部分よりも薄く成形
されていることを特徴とするリードフレーム。3. A lead frame used for assembling a semiconductor chip, characterized in that the thickness of the end portion of the inner lead is formed thinner than the portion to which the inner lead is bonded.
ームを用いて構成されたことを特徴とする半導体装置。4. A semiconductor device comprising the lead frame according to claim 1, 2, or 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5237763A JPH0794664A (en) | 1993-09-24 | 1993-09-24 | Lead frame and semiconductor device employing it |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5237763A JPH0794664A (en) | 1993-09-24 | 1993-09-24 | Lead frame and semiconductor device employing it |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0794664A true JPH0794664A (en) | 1995-04-07 |
Family
ID=17020090
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5237763A Pending JPH0794664A (en) | 1993-09-24 | 1993-09-24 | Lead frame and semiconductor device employing it |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0794664A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009224726A (en) * | 2008-03-18 | 2009-10-01 | Powertech Technology Inc | Col semiconductor package |
-
1993
- 1993-09-24 JP JP5237763A patent/JPH0794664A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009224726A (en) * | 2008-03-18 | 2009-10-01 | Powertech Technology Inc | Col semiconductor package |
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