JPH0794546A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device in which the size of substrate is prevented from increasing even if the number of bonding pads increases. CONSTITUTION:A plurality of pad forming regions 8 are formed at a predetermined interval on the outer periphery of a semiconductor substrate 1. A pressure protective layer 45 for a P-type region is formed in the pad forming region 8. A first electrode layer 47 is formed on the upper face of the semiconductor substrate 1 through an insulation layer 46. An insulation layer 48 is formed on the upper face of the electrode layer 47 and a part thereof, exposing through a window 49, provides a bonding pad 9a. A second electrode layer 50 is formed on the insulation layer 48 and an exposed part of the electrode layer 50 provides a bonding pad 9b. A third electrode layer 52 formed on the electrode layer 50 through an insulation layer 51 provides a bonding pad 9c.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an arrangement structure of bonding pads for bonding which are formed on the periphery of a semiconductor substrate.

Various internal circuits provided in an internal cell region of a semiconductor device are connected to bonding pads via input / output circuits, respectively. With the recent increase in the density of the internal cell region, the number of internal circuits that can be formed in the internal cell region has increased, and the number of bonding pads has also increased accordingly. The size of the semiconductor substrate depends on the number of bonding pads, and as the number of pads increases, the size of the substrate also increases. Therefore, it is necessary to arrange the bonding pads so that the size of the substrate can be prevented from increasing.

[0003]

2. Description of the Related Art FIG. 5 shows a conventional semiconductor device. An internal cell region 82 for forming various internal circuits is provided in the center of the semiconductor substrate 81. An input / output cell region 84 is set around the internal cell region 82, and an input / output circuit 85 connected to each of the internal circuits is provided in the input / output cell region 84. Further, a pad formation region 86 is set around the input / output cell region 84. In the pad formation region 86, a plurality of bonding pads 87 for bonding corresponding to each input / output circuit 85.
And each bonding pad 87 is connected to each input / output circuit 85. Therefore, a data signal is externally input to the internal circuit via the bonding pad 87 and the input / output circuit 85.

[0004]

By the way, in recent years, the number of internal circuits that can be formed in the internal cell region 82 has increased due to the high density of the internal cell region 82, and in response to this, the input / output circuit 85 and the bonding pad 87. The number of is increasing. However, in the conventional semiconductor device, many bonding pads 87 are formed on the same wiring layer on the substrate 81. As shown in FIG. 6, it is impossible to make the distance between the bonding pads 87 smaller than the predetermined distance α due to the design rule. The spacing α determines the arrangement of the bonding pads 87, and if the number of the bonding pads 87 increases, the pad formation region 86 also increases accordingly.

Therefore, a wasted space 90 is formed between the internal cell area 82 and the input / output cell area 84 on the substrate 81.
However, there is a problem that the size of the substrate 81 is increased due to the increase in the number of bonding pads 87 due to the high density of the internal circuit 83.

The present invention has been made to solve the above problems, and an object of the present invention is to increase the number of bonding pads in response to higher density of internal circuits provided on a semiconductor substrate. Another object of the present invention is to provide a semiconductor device capable of preventing the substrate from becoming large.

[0007]

In order to achieve the above object, the present invention provides a semiconductor device in which a large number of bonding pads are formed on the outer peripheral edge of a semiconductor substrate, and a plurality of pad formation regions are formed on the semiconductor substrate. It is formed with a predetermined interval. A plurality of bonding pads are provided in different wiring layers in each pad formation region.

[0008]

In each pad formation region, the plurality of bonding pads are formed on different wiring layers and are not formed on the same plane. Therefore, it is not necessary to consider a predetermined interval in the design rule between the bonding pads of each wiring layer, and the bonding pads can be arranged close to each other. Therefore, even if the number of bonding pads increases due to the high density of the internal circuit, the bonding pads are compactly provided in the pad formation region, and the semiconductor substrate is prevented from increasing in size.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment embodying the present invention will be described below with reference to FIGS.
It will be described with reference to FIG. As shown in FIG. 4, an internal cell region 2 is provided in the center of a square N-type semiconductor substrate 1, and a large number of internal circuits are formed in the internal cell region 2. Further, a pair of power supply cell circuits 4a and 4b are formed on each outer side of the internal cell region 2. The power supply cell circuits 4a and 4b are connected to a wiring layer (not shown) of the internal circuit 3. Further, power supply pads 5a and 5b connected to the power supply cell circuits 4a and 4b are formed outside the power supply cell circuits 4a and 4b, respectively.

Input / output cell regions 6 are provided on both sides of the power supply cell circuits 4a and 4b along the internal circuit 3, and the input / output cell regions 6 are connected to the internal circuit 3. A plurality of 7 are formed. I / O cell area 6
A pad forming region 8 is provided on the outer side (outer end side of the substrate 1) along the input / output circuit 7. Three bonding pads 9a to 9c are formed in the pad formation region 8, and the bonding pads 9a to 9c are different from each other.
The two input / output circuits 7 are respectively connected.

Next, the configurations of the input / output circuit 7 and the bonding pads 9a-9c will be described in detail with reference to FIGS.
Since the input / output circuit 7 has the same configuration,
Only the configuration of one input / output circuit 7 will be described.

FIG. 1 is a layout diagram of the bonding pads 9a to 9c and the input / output circuit 7, and FIG.
An electric circuit diagram of the input / output circuit 7 is shown in FIG. Board 1
A first P-type region 10 is formed in the input / output cell region 6. The substrate 1 and the P-type region 10 form a pair of protection diodes D1 and D2. The second P-type region 1 corresponding to the P-type region 10 is formed on the substrate 1.
A pair of 1a, 11b and a first N-type region 12a, 12b is formed. The N-type regions 12a and 12b
The third P-type regions 13a, 13b and the second N
A pair of mold regions 14a and 14b are formed.
The N-type substrate 1 and the respective regions 10, 11a, 11b, 12
Electrical insulation from a, 12b, 13a, 13b, 14a, 14b is maintained by an insulating layer (not shown).

The P-type region 10 has a contact hole 16
Is connected to the first aluminum wiring 17 via. or,
The aluminum wiring 17 is connected to the first polysilicon wiring 19 through the contact hole 18. The polysilicon wiring 19 is provided between the P-type regions 11a and 11b and between the N-type regions 12a and 12b.

Therefore, the P-type MOS transistor 20 is formed by the P-type regions 11a and 11b and the polysilicon wiring 19.
The N-type regions 12a and 12b and the polysilicon wiring 19 form an N-type MOS transistor 21. The P and N type MOS transistors 20, 2
1 constitutes a first inverter circuit 23.

The P-type region 11a is connected to the first power supply wiring 25 through a pair of contact holes 24,
It is the source of the P-type MOS transistor 20. The N-type region 12a is connected to the second power supply wiring 27 via the contact hole 26 and serves as the source of the N-type MOS transistor 21.

The P-type region 11b is connected to the second aluminum wiring 29 through a pair of contact holes 28, and P
The drain of the type MOS transistor 20. The N-type region 12b is connected to the aluminum wiring 29 through the contact hole 30, and the N-type MOS transistor 2
It is the drain of 1. The aluminum wiring 29 and the aluminum wiring 17 are formed on the same plane.

The aluminum wiring layer 29 has a contact hole 31.
It is connected to the second polysilicon wiring 32 via. The polysilicon wiring 32 is provided between the P-type regions 13a and 13b and the N-type regions 14a and 14b.

The P-type regions 13a and 13b and the polysilicon wiring 32 form a P-type MOS transistor 33, and the N-type regions 14a and 14b and the polysilicon wiring 32 form an N-type MOS transistor 34. Then, the P and N type MOS transistors 33, 3
The second inverter circuit 35 is constituted by 4.

The P-type region 13a is connected to the fourth power supply wiring 37 through the pair of contact holes 36 and serves as the source of the P-type MOS transistor 33. The N-type region 14a is connected to the fourth power supply wiring 39 via the contact hole 38 and serves as the source of the N-type MOS transistor 34.

The P-type region 13b is connected to the third aluminum wiring 41 through a pair of contact holes 40, and P
The drain of the MOS transistor 33. The N-type region 14b is connected to the aluminum wiring 41 through the contact hole 42, and the N-type MOS transistor 3
It is the drain of 4. The aluminum wiring 41 is formed on the same plane as the aluminum wiring 17 and is connected to each internal circuit of the internal cell region 2.

As shown in FIGS. 1 and 2, a pressure protection layer 45 in a P-type region corresponding to the pad formation region 8 is formed on the substrate 1 below the bonding pads 9a to 9c. The pressure protection layer 45 is the bonding pad 9a.
It is intended to prevent adverse effects on the substrate 1 due to the pressing force and heat when wires (not shown) are bonded to 9c.

On the upper surface of the substrate 1, polysilicon wiring 19,
A first insulating layer 46 is formed to cover the upper surface of 32.
An electrode layer 47 is formed on the upper surface of the pressure protection layer 45 via the insulating layer 46. The electrode layer 47 is formed on the same plane as the aluminum wiring layers 17, 29 and 41. A second insulating layer 48 is formed on the upper surface of the electrode layer 47. Then, a window 49 is formed in the second insulating layer 48 in the substantially central portion of the pressure protection layer 45, and the electrode layer 4 is formed.
7 is exposed, and the exposed portion is the bonding pad 9
It is a.

The second electrode layer 5 is formed on the insulating layer 48.
0 is formed. A third insulating layer 51 is formed on the electrode layer 50 on the right side of FIG. Left electrode layer 50
Is exposed, and the exposed electrode layer 50 serves as the bonding pad 9b.

Further, an electrode layer 52 is formed on the insulating layer 51. The electrode layer 52 serves as the bonding pad 9c. The bonding pad 9a is connected to the P-type region 10 via a contact hole 53. The bonding pad 9b is connected to the fourth aluminum wiring 55 formed on the same plane as the electrode layer 47 through the contact hole 54, and the aluminum wiring 55 is connected to the P-type region 10 through the contact hole 56. Has been done.

Further, the bonding pad 9c is connected through a contact hole 57 to a fifth aluminum wiring 58 formed in the same first wiring layer as the electrode layer 47.
The aluminum wiring 58 is connected via a contact hole 59 to a sixth aluminum wiring 60 formed on the same plane as the electrode layer 47. Further, the aluminum wiring 60 is connected to the P-type region 10 via the contact hole 61. Therefore, the bonding pads 9a to 9c are respectively connected to the input / output circuit 7 through the P-type region 10 having a resistance component.

A bonding wire (not shown) is bonded to the bonding pads 9a-9c,
The bonding pads 9a-9c are connected to an external circuit. Therefore, for example, a data signal from the outside is input to a predetermined internal circuit in the internal cell region 2 via the bonding pads 9a to 9c and the input / output circuit 7.

The first to third electrode layers 47, 50, 52 constituting the bonding pads 9a-9c are insulated by the first to third insulating layers 46, 48, 51. Further, a window 49 which forms the bonding pad 9a is formed by exposing a part of the first and second electrode layers 47 and 50.

Therefore, the first to third electrode layers 47, 50,
52 are formed on different wiring layers, but are not formed on the same plane when viewed conversely. Therefore, as shown in FIG. 1, it is not necessary to provide a predetermined interval according to the design rule between the bonding pads 9a to 9c.
a to 9c can be brought close to each other.

Therefore, the arrangement of the bonding pads 9a-9c formed in the pad formation region 8 can be made compact. As a result, the bonding pads 9a to 9c can be compactly formed in the pad formation region 8 without forming a useless space in the substrate 1 even if the internal cell region 2 is increased in density and the number of internal circuits that can be configured increases. can do.

In the present embodiment, the pad formation region 8 has three bonding pads 9a-9c. The number of bonding pads in the pad formation region 8 is not limited to this, and two or more bonding pads are formed in the pad formation region 8 by alternately stacking electrode layers and insulating layers. It is also possible.

[0031]

As described in detail above, according to the present invention, a plurality of pad formation regions are formed on a semiconductor substrate at a predetermined interval, and a plurality of bonding pads are formed in different wiring layers in each pad formation region. . Therefore, since the respective bonding pads can be arranged in close proximity to each other in a compact manner, even if the number of the bonding pads increases as the internal cell region becomes denser, it is possible to suppress the size increase of the semiconductor substrate and reduce the size of the semiconductor device. There is an excellent effect that the cost increase can be suppressed.

[Brief description of drawings]

FIG. 1 is a layout diagram of a bonding pad and an input / output circuit formed in a pad formation region and an input / output cell region.

FIG. 2 is a sectional view taken along line AA in FIG.

FIG. 3 is an electric circuit diagram of an input / output circuit.

FIG. 4 is a layout diagram in which an internal circuit, an input / output circuit, and a bonding pad are formed on a substrate.

FIG. 5 is a layout diagram in which an internal circuit, an input / output circuit, and a bonding pad are formed on a conventional substrate.

FIG. 6 is an explanatory diagram showing that the spacing between bonding pads formed on a conventional substrate is restricted.

[Explanation of symbols]

 1 Semiconductor Substrate 8 Pad Forming Area 9a, 9b, 9c Bonding Pad

Claims (1)

[Claims] 1. A semiconductor device having a large number of bonding pads (9a, 9b, 9c) formed on the outer peripheral edge of a semiconductor substrate (1), wherein a plurality of pad formation regions (8) are formed on the semiconductor substrate (1). And a plurality of bonding pads are formed in different wiring layers in each pad formation region (8).