JPH0794173B2 - Printer controller - Google Patents

Description

The present invention relates to a printer control device for inputting input data such as character code information from an external device such as a host computer and visually outputting dot-form bitmap data. It is a thing.

[Prior Art] FIG. 4 shows a circuit configuration example of a conventional printer of this type.

In FIG. 4, text data 121 including character codes and form codes sent from the host computer or the like.
The input data such as is received by the input control unit 101 and then temporarily stored in the page memory 102. Next, the individual code information of the text data 121 stored in the page memory 102 is sequentially read by the main control unit 103 from the beginning.

The main control unit 103 converts the character code information read from the page memory 102 into dot pattern information by the document pattern generation unit 104, and writes this into the bitmap memory 105. The document pattern generation unit 104 is a conversion table that associates a character code with a dot pattern corresponding to this character code.

Next, of the dot pattern information stored in the bitmap memory 105, the character information for one scanning line is stored in the scan buffer 406. The scan buffer 406 includes double buffers 406a and 406b, and one of the double buffers, for example, 406a is the read control unit 40.
While being read by 8, the main controller 103 stores dot pattern information for the next scanning line in the other double buffer, for example, 406b.

Next, the dot pattern information in the form of parallel signals read from the scan buffer 406 by the read control unit 408 is parallel-serial converted into the form of serial signals by the parallel-serial converter 407, and then sent to the printing mechanism and printed. It Examples of this printing mechanism include a laser beam type and an inkjet type.

[Problems to be Solved by the Invention] However, in the conventional device as described above, after the dot information is written in the bitmap memory 102 in a predetermined amount, for example, in page units, the bitmap memory 102 is written.
In the method of reading the dot information from the 102, a buffer memory 406 must be provided in the subsequent stage of the bitmap memory 102 in addition to the bitmap memory 102 in order to synchronize with the timing of dot printing of the printing mechanism.

Further, in order to increase the throughput of the main control unit 103, an IC called a direct memory access controller (DMA controller) that can read dot information from the bitmap memory 102 at a higher speed than the arithmetic processing speed of the main control unit 103. The circuit must be used for the read controller 408.

Therefore, the conventional printer has the following drawbacks.

(1) As the memory capacity of the buffer 406, the memory capacity of the data for one scanning line corresponding to the maximum paper size that can be handled by the printing mechanism is required, and the memory capacity becomes large.

(2) To increase the scanning speed, a static random access memory (SRAM) that does not require a refresh operation must be used as the buffer 406, which increases the manufacturing cost of the buffer memory 406.

Therefore, an object of the present invention is to eliminate such drawbacks, read dot information directly from a bitmap memory without using the scan buffer 406, and enable high-speed printing to reduce the manufacturing cost of the printer. It is to provide a printer control device capable of performing the above.

[Means for Solving the Problems] In order to achieve such an object, the present invention provides a generation unit that generates bitmap data from input data input from the outside, and the bitmap generated by the generation unit. A storage unit for storing data, a latch unit for latching a predetermined amount of bitmap data read from the storage unit, and a parallel-serial conversion of the predetermined amount of bitmap data latched by the latch unit for printer By the conversion means for outputting to the engine, and by the end of the output of the predetermined amount of bitmap data in the conversion means, the next predetermined amount of bitmap data is read from the storage means and latched by the latch means. And control means for transferring map data to the converting means.

[Operation] According to the present invention, the predetermined amount of bitmap data latched by the latching device is parallel-serial converted and output to the printer engine until the output of the predetermined amount of bitmap data is completed. The bit map data of is read from the storage means and latched by the latch means, and then the bit map data is transferred to the conversion means.
Bitmap memory (storage means) that was required in the past
Since an intermediate buffer memory between the printer and the printing mechanism unit is not necessary and the reading / writing time for this buffer memory is shortened, high-speed printing is possible.

Embodiments Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows the basic configuration of an embodiment of the present invention.

In FIG. 1, the same parts as those in FIG. 4 are designated by the same reference numerals, and detailed description thereof will be omitted.

106 is a direct memory access (DMA) control unit,
The dot pattern read address stored in the bit map memory 105 is designated.

An integrated circuit called a DMA controller can be used for the direct memory access control unit 106. 107 is a timing control unit as a control means for supplying a signal instructing operation timing to each component in addition to the direct memory access control unit 106. The main control unit 103 corresponds to the writing unit, and the pattern generation unit 104 corresponds to the converting unit.

A latch circuit 108 latches the dot pattern read from the bitmap memory 105. Reference numeral 109 is a serial converter for parallel-serial converting the dot pattern output from the latch circuit 108.

FIG. 2 shows a specific circuit configuration example of the timing control unit 107, the latch circuit 108, and the parallel-serial converter 109 shown in FIG.

In FIG. 2, 201 is an oscillator that generates a synchronization signal (VDCK) 231 that serves as a reference for the operation timing of each component. Reference numeral 202 denotes a counter 2A that counts 16 dots, counts the synchronization signal generated by the oscillator 201, outputs a signal of level “H” from the Q terminal when the count result becomes “8”, and the count result becomes “16”. Becomes "L" level signal
To While the Q terminal output is at level "H", the dot pattern is read from the bitmap memory 105.

Reference numeral 203 denotes a counter 2B which receives a Q terminal output signal (referred to as a count-up signal) 233 indicating the counting result of the counter 202 and counts the output dots from the bitmap memory 105 corresponding to one horizontal scanning.

When the horizontal synchronization signal (HSYNC) 136 is input from the printing mechanism, the signal 204 holds (latches) and outputs a signal of level "H" to the counter A202, the counter B203 and the fourth flip-flop 207 in synchronization with the rising edge of the pulse It is a flip-flop (F / F).

Reference numeral 205 is a second flip-flop that synchronizes with the count-up signal 233 of the counter A202 and generates a signal that permits the signal output of the parallel-serial converter 109.

A third flip-flop 206 generates a DMA request signal (DREQ) 134, which will be described later, to the direct memory access controller 106 in synchronization with the count-up signal 233 of the counter A202.

Reference numeral 208 is an inverter for inverting the level of the count-up signal of the counter 2B, and the output of the inverter 208 is supplied to the third flip-flop 206 and the NAND gate 211.

An AND gate 209 outputs a signal obtained by ANDing (AND) the image data end signal 131 from the fourth flip-flop 207 and the signal 236 from the second flip-flop as an output permission signal 209 to the parallel-serial converter 109. .

210 is a NAND of the output enable signal 209 from the AND gate 209 and the output signal of the parallel-serial converter main body 109-1.
Then, the output signal of the parallel-serial converter main body 109-1, that is, the serial dot pattern 138 to be printed is output to the printing mechanism at the instruction timing of the output permission signal 209.

FIG. 3 shows the signal waveform of each signal shown in FIG.

The operation of this embodiment will be described with reference to the timing chart of FIG. The text data 121 including a character code and a form code sent from an external device such as a host computer is temporarily stored in the page memory 102 by the input control unit 101. Next, the text data 121 stored in the page memory 102 is sequentially read by the main control unit 103 from the top data.

The main control unit 103 converts the character code or form code read from the page memory 102 into dot pattern information by referring to the conversion table provided in the pattern generation unit 104, and stores it in the bitmap memory 105. The operation up to this point is similar to that of the conventional example. However, the bus request signal 13 is sent from the timing control unit 107 via the DMA control unit.
Since the dot pattern information is being read from the bitmap memory 105 while 2 is being supplied to the main control unit 103, the main control unit does not perform the write operation to the bitmap memory 105.

Next, the main control unit 103 sets to the DMA control unit 106 the address where the dot pattern information of the first scanning line in the bitmap memory 105 is stored, and the timing control unit 107 outputs the sequence enable signal 139. Output. Also, a print permission signal (not shown) is output to the printing mechanism.

The printing mechanism receives the print permission signal and starts the printing operation.

Next, the dot pattern information stored in the bitmap memory is sent to the printing mechanism by the following procedure (second
(See Figures and Figure 3).

(B) The horizontal synchronization signal (HSYN
C) When 136 is input at the timing T1, the first flip-flop 204 is set, and the counter A202 is counted by the output signal (HENB) 232 of the first flip-flop 204 by the image output clock 231 generated by the oscillator 201. To start.

(B) Timing T2 when counter A202 counts "8"
Then, the output signal 233 from the Q terminal of the counter A202 becomes "H" level, and as a result, the third flip-flop 206 is set. Therefore, the third flip-flop 206 outputs the request signal (DREQ) 134 indicated by the waveform A of level “L” to the DMA control unit 106.

(C) The DMA control unit 106 outputs the bus request signal 132 to the main control unit 103 when the DMA request signal (DREQ) 134 is input.

(D) When the bus request signal 132 is input to the main control unit 103,
The bus is released and at the same time, a bus release signal 133 indicating that the bus is released is transmitted to the DMA control unit 166.

(E) Next, the DMA control unit 106 outputs to the bitmap memory 105 the address 142 in which the dot pattern information to be output is stored, and the dot pattern information 140 that is addressed is output from the bitmap memory 105. Output. At the same time, DMA at timing T3 (see FIG. 3)
The control unit 106 outputs a latch signal (DACK) 135 to the latch circuit 108.

(F) Dot pattern information (DATA) 140 for 16 dots output from the bitmap memory 105 is a latch signal (DAC
K) is temporarily stored in the latch circuit 108 according to the latch instruction of 135. Further, the third flip-flop 206 is cleared in response to the latch signal 135. As a result, the output level of the Q terminal of the flip-flop 206 becomes "H" as shown by the waveform A.

(G) Next, the counter A202 displays the image output clock (VDC
K) RC0 of the counter A202 from the time T5 (see Fig. 2) when "231" is counted to the time T6 when "16" is counted.
(Ripple carry) The output becomes level “H”. At this timing T6, the Q terminal output 233 of the counter A202 changes from the "H" level to the "L" level, the counter B203 is counted by the falling of this signal, and the second flip-flop 205 is set. As a result, the image data output permission signal 237 is output from the second flip-flop 205 to the parallel-serial converter 109 via the AND gate 209.

(H) The 16-dot dot pattern information (VDATA) 141 temporarily stored in the latch circuit 108 is the synchronization signal (VDCK) 231.
Is read by the parallel-serial converter 109 in synchronism with the rising edge of the 16th pulse, that is, the timing T6. Next, the dot pattern information (VD0) converted in series is sequentially output via the AND gate 210 in synchronization with the synchronization signal (VDCK) 231.

(B) Until the counter B203 finishes counting the number of dots for one scanning line, the above sequence (b) to (h) is repeated every time the counter A202 counts “16”, and the dots for one scanning line are counted. The pattern information is output to the printing mechanism.

(E) At time T10 when the counter B203 finishes counting the number of dots for one scanning line, the output 235 of the counter B203 becomes "H" level.

(E) Time T11 when the counter A202 counts "16" pulses after the count-up output 235 goes to "H" level
The first F / F flip-flop 207 is synchronized with the falling edge of the Q output 233 of the counter A202 from "H" to "L".
Is set, and the output end signal (HEND) 131 of the image data for one scanning line is output (“L” level).

(W) The main control unit 103 uses the image data output signal (HEND) signal 1
When 31 is input, the sequence enable signal (SQEN
B) The circuit of the timing control unit 107 is reset by setting 139 to "L" level once, and the next horizontal synchronization signal (HSYNC)
Prepare for 136 inputs. At this time, if necessary, the DMA control unit 10
For 6, the address of the bitmap memory in which the dot pattern information for the next scanning line is stored is set.

In this way, the dot pattern information for one page is output to the printing mechanism and printed.

In the above embodiment, the timing of writing dot-converted dot information to the storage means is not the main, but the timing of reading is synchronized with the dot printing timing with a long time interval of the printer mechanism, and the dot information is provided in the gap of the dot printing timing. I wrote it, so
The dot information can be written in synchronization with the dot conversion speed of the conversion means.

As described above, according to the present invention, it is not necessary to provide an intermediate buffer between the storage unit (bitmap memory) and the printing mechanism, so that the manufacturing cost can be reduced and the access to the intermediate buffer can be achieved. Since the time can also be omitted, it is possible to contribute to an increase in printing speed.

[Brief description of drawings]

1 is a block diagram showing a system configuration of an embodiment of the present invention, FIG. 2 is a circuit diagram showing a detailed configuration of the timing control unit 109, a latch circuit, and a parallel-serial converter 109 shown in FIG. 1, FIG. Is a timing chart showing the signal waveform of each circuit shown in FIG. 2, and FIG. 4 is a block diagram showing the system configuration of a conventional example. 101 …… input / output control section, 102 …… page memory, 103 …… main control section, 104 …… pattern generation section, 105 …… bit map memory, 106 …… direct memory access section, 107 …… timing control section, 108 …… Latch circuit, 109 …… Parallel-to-serial converter.

Claims (1)

[Claims] 1. A generation unit for generating bitmap data from input data input from the outside, a storage unit for storing the bitmap data generated by the generation unit, and a predetermined amount read from the storage unit. Latching means for latching the bit map data, converting means for converting the predetermined amount of bit map data latched by the latch means into serial data, and outputting to the printer engine; and the predetermined amount of bitmap in the converting means. By the time the output of the data ends, the following predetermined amount of bitmap data is read from the storage means and latched by the latch means, and then the bitmap data is transferred to the conversion means. Printer control device.