JPS61117972A - Printer - Google Patents

Abstract

PURPOSE:To compose data of plural pages at an aribitrary position so as to print it by composing data of plural pages and providing a small capacity memory having at least data corresponding one line at the time of printing data on the same page. CONSTITUTION: A control part 3 stores character code data and control command such as the number of printed pages and the top address on each page among inputted data in a code page memory 4 and a work memory 5, respectively, sets set prescribed values in each start address latch circuit, dot number latch circuit, etc., according to the control commands, converts the character code which has to be printed and has been stored in the code page memory 4 into a dot image, and stores it in a line dot image memory. When the data to be stored in the line dot image memory is set, a read circuit is activated, and transmits sequentially printed data to a printing part 50 in synchronizing with a horizontal synchronizing signal 24 transmitted from the printing part 50 so as to print it. Normally, since data of plural pages are composed, at least dot image memories corresponding to pages included during one scan period are necessary.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a printing device that combines and prints information on a plurality of pages on the same page.

[Prior art] Conventionally, in this type of printing device, when compositing pages *a, it has multiple dot image memories each having a capacity for one page, and each dot image is printed according to the first start address of each composite page. From the address in memory,
Dot patterns of letters, symbols, etc. were developed and printed.

Therefore, the dot image memory capacity is equivalent to one page each, and as the paper size increases,
This has the disadvantage of requiring increasingly large capacity memory, resulting in high costs. Furthermore, if the memory capacity was insufficient, printing on large paper sizes could not be performed.

[Objective] The present invention aims to eliminate the drawbacks of the above-mentioned prior art, and provides a printing device that can combine and print out page data of any paper size using a small memory capacity. With the goal.

[Example] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

1 to 5 (A) and (B) show an embodiment according to the present invention, and FIG. 1 is a schematic block diagram, in which 1 is an interface signal line, 2 is an interface circuit, and 3 is an interface circuit. 4 is a code page memory, 5 is a work memory, 6 is an address conversion circuit, 7 is a character generator, 8 is a row dot image memory A, 9 is a row dot image memory B, and 10 is a row of the row dot image memory A8. The start address latch circuits AX and 11 that hold the start address in the direction (scanning direction) are transferred to the row dot image memory 8.
The start address latch circuit AY, 12, which holds the start address in the digit direction, is a row dot image memory B9.
The start address latch circuit BX, 13 that holds the start address in the row direction of the row dot image memory B9
The start address latch circuit BY, 14, which holds the start address in the digit direction, is a row dot image memory A8.
A dot number latch circuit 15 holds the number of dots in the row direction (scanning direction) of the row dot image memory B9.A dot number latch circuit 8 holds the number of dots in the row direction of the row dot image memory B9. Y counter A holds the number of dots in the digit direction of the stored dot image; 17 is a Y counter B that holds the number of dots in the digit direction of the stored dot image in the row dot image memory B9; 18 is data stored in the row dot image memory A. The reading circuit A reads out the data stored in the row dot image memory B and outputs it to the printing section 50. The reading circuit B 19 reads out the data stored in the row dot image memory B and outputs it to the printing section 50.

20 is an external controller that outputs print data etc., 50
A printing section prints out the print data from the readout circuits A18 and B19 onto recording paper, and in this embodiment, the printout is performed by electrophotography using semiconductor laser exposure.

The details of this readout circuit are shown in FIG. 2, in which the same components as in FIG. 1 are given the same numbers.

In FIG. 2, 21 is a synchronization clock generation circuit, 22 is an image clock counter, 23 is an AX comparison circuit, 24 is a horizontal synchronization signal, 25 is a scanning line counter, 26 is an AY comparison circuit, 2
7.29 is an AND circuit, 28 is a flip-flip circuit (
30 is a row counter, 31 is a digit counter, 33 is an end detection section, 34 is a parallel-serial (hereinafter referred to as F/F),
35 is serial output data, 51 is an OR circuit, 52 is a laser driver, 53 is a semiconductor laser, and 54 is a photoreceptor.

In the above configuration, there are two sets of row dot image memories, but it is of course possible to provide multiple sets of row dot image memories by adding similar configurations in parallel.

Next, the operation of the present embodiment having the above configuration will be described using as an example the case where a plurality of page data shown in FIG. 3 are combined and printed.

Figure 3 shows the combination of the first page data indicated by 101, the second page data indicated by 102, and the third page data indicated by 103, which have different print areas and printed character sizes. This is a printed example.

External controller 2 via interface signal line 1
Print data is input to the interface circuit 2 from 0,
The output signal enters the control section 3.

Of the input data, the control section 3 stores code data representing a one-character code in the code page memory 4, and stores control commands such as the number of print sheets and the start address of each page to be combined in the work memory 5.

The control unit 3 then sets predetermined values in each start address latch circuit, dot number latch circuit, etc. according to the control command stored in the work memory 5 according to the flowchart in FIG. The desired character code is converted into a dot image and stored in the row dot image memory.

First, in step S1, the control section 3 refers to the work memory 5 and checks whether there is output data to the row dot image memory A8. Here, if some print data is stored in the code page memory 4, the page data to start printing first on the print page is allocated to the line dot image memory 8, and the print area for one line is If there is any other page data to be printed, this page data is allocated to the next row dot image memory B9.

Therefore, in the example of FIG. 3, the data of page lot is allocated to row dot image memory A8, and the data of page 102 is allocated to row dot image memory B9.

If there is output data to the row dot image memory A8 in step S1, the process advances to step S2 to check whether the row dot image memory A8 is free. This is because if some print data is stored in the current row dot image memory A and all of this print data has not been printed by the printing section 50, the process waits until printing is finished.

When 8 is vacant in the row dot image memory, the process advances to step S3, and in the example of FIG. ABCD" start address in the digit direction x11. Calculate the start address Yl in the row direction, and set xl to the start address latch circuit AX.
IO and Yl are set in the start address latch circuit AYII, respectively.

Next, in step S4, the first row of code data is read from the code page memory 4 and sequentially output to the addressless conversion circuit 6. The address conversion circuit 6 converts the input code data into an address for accessing the character generator 7, and outputs the address to the character generator 7. The output of the character generator 7 is input to the row dot image memory A8, while the addresses of the row dot image memory 8 are sequentially output from the control section 3. Therefore, the character generator 7 converts the code data into a dot pattern corresponding to the code data, and stores it in the row dot memory A.
It is stored in 8. In this way, "ABCD" for one line
” is stored in the row dot image memory 8.

Then, the process returns to step S1. In step Sl, since the storage in the row dot image memory B9 has been completed, the process advances to step S5, and it is checked whether or not there is output data to the row dot image memory B9. If there is, the process advances to step S6, and the row dot image memory The free space in the image memory B9 is checked, and if there is free space, the process proceeds to step S7, where the data on page 102 in FIG. 3 is similarly developed.

That is, since the start address of the page 102 is stored in the work memory 5, the controller 3 calculates the column direction and row direction start address (x, y) of the first row based on it in step S7, It is output to the start address latch circuit BXI and the start address latch circuit BY13.

Next, in step S8, the code data of "abc" in the lt row of page 102 is sequentially outputted from the code memory 4 to the address conversion circuit 6. Then, the character generator 7
is converted into an address to access. The output of the character generator 7 is input to the row dot memory B9,
On the other hand, the addresses of the row dot memory B9 are sequentially input from the control section 3 to the row dot memory B9, and the dot patterns of the character generator 7 are stored therein.

In this way, one line of dot pattern "abc" is developed in the line dot memory 9.

On the other hand, prior to this, the control unit 3
The number of dots in the row direction of t, that is, in the scanning direction is M, and the number of parallel bits of the row dot image memory A8, that is, the number of bits read out by accessing the l address, is N (usually 8
(or 16 bits) and set M/N in the dot number latch circuit A14.

Similar calculations are made for page 102 in FIG. 3, and the calculations are set in the dot number latch circuit BL5. Also, the number of dots in one line in the row direction (Y direction) of page 101 in FIG. 3 is calculated, and the Y counter A16 is set to the L-adic counter. Similarly, the number L' of dots in one row of the page 102 in the row direction (Y direction) is calculated, and the Y counter B17 is used as the L' counter.

In the printing example shown in FIG. 3, pages 101 and 102 exist on the same line (same scanning period), but page 103 is independent. Therefore, the row dot image memory used as page 101 or page 102,
Since it can be used for page 103, it is sufficient to store two lines of one-line dot image memory, that is, two sets.

When the data to be printed is set in the row dot image memory, the readout circuit is activated, and the print data is sequentially sent to the printing section 50 in synchronization with the horizontal synchronization signal 4 sent from the printing section 50 for printing. When the printing progresses and all the data set in the row dot image memory is printed, the control section 3 sets the next data to be printed in the row dot image memory again in the above-described procedure.

Hereinafter, the readout control of the dot patterns from 8 to the row dot image memory by the readout circuit A18 of FIG. 2 will be explained.

The horizontal synchronization signal 24 is generated at the beginning of each scanning line in the main scanning direction (row direction) of the printing apparatus (not shown), and is input to the synchronization clock generation circuit z1. This circuit generates an image clock synchronized with the horizontal synchronization signal 24.
It is sent to the image clock counter 22. The AX comparison circuit 23 receives the output signal of the image clock counter 22 and the start address (Xi, Yl) of the page 101 in FIG.
t is latched.

The output signal of the start address latch circuit AXIO is input, and when both signals match, the AND circuit 27
Output to. On the other hand, the horizontal synchronization signal 24 is input to the scanning line counter 25, which starts counting the number of scanning lines from the top of the page. The output is input to the AY comparison circuit 26. The start address (X
J.

Of Yl), the output signal of the start address latch circuit AYII which latches Yl is also input to the AY comparison circuit 26, and its match signal is input to the AND circuit 27. The output timing of the AND circuit 27 ultimately means the timing at which the start address of the page 101 shown in FIG. 3 is detected, and the F/F 28 is set with this signal.

The output of the F/F 28 is input to an AND circuit 29, and the other input signal of the AND circuit 29 is ANDed with the image clock from the synchronous clock generation circuit 21. This output is input to the row counter 3o and counted down to l/N. This value of N means that the row dot image memory A8 outputs N bits in parallel.1 The clock counted down to l/N by the row counter 30, which is usually 8 bits or 16 bits, is output to the digit counter 31. The output of the 0-digit counter 31, which advances the address of the row dot image memory A8, is also input to the end detection section 33. As explained above, the value M/N obtained by dividing the number of dots in the scanning direction by N is set in the dot number latch circuit A14, and this value is input to the end detection section 33, where the value of the digit counter 31 is compared to the value. When a match is found, that is, when all the stored dot pattern data for one row of 8 is read out to the row dot image memory, the digit counter 31 is reset and the F/F 28 is reset. Further, the Y counter A16 is incremented by one. Y counter AlB is
This is a counter in the Y direction (direction in which scanning lines are counted) of the row dot image memory A8, and as mentioned above, if the number of dots in the Y direction on page 101 shown in FIG. When the set 0-row dot image memory A8 is sequentially read out, as explained in the flowchart of FIG.
The output signal of the 0-row dot image memory A8, in which the next row of data is sequentially written and all the data on the page 101 shown in FIG. input, and then AND circuit 2
The image clock from 9 is converted into a serial signal.

The output is inputted to the laser driver 52 via the OR circuit 51 of the printing section 50, which turns the semiconductor laser 53 on and off, and the light is incident on the photoreceptor 54, where printing is performed by a known electrophotographic method. .

On the other hand, to explain the case of page 102 shown in FIG. 3, the start address of the data on page 102 is latched by address latch circuit BXI and address latch circuit BY13, and the number of dots in the scanning direction is also latched by the dot number latch circuit. 15, so by accelerating the row dot image memory B9 with the same circuit configuration as above,
The page 102 can also be printed by reading the data and inputting it to the OR circuit 51.

The same applies to page 103.

The details of the row dot image memories A, B (8, 9) are shown in the fifth column.
As shown in the figure.

In FIG. 5, the row dot image memory is arranged in the row direction (X
direction) is Mo dots (for example, the maximum number of dots in the length of the paper width in the scanning direction), and the digit direction (Y direction) is Lo
Dots (for example, the maximum number of dots in the Y direction per line of the dot pattern).For example, as shown in FIG.
The dots maintain the relationship of M≦Mo and L≦L0.

The control unit 3 calculates the address of the starting point of this row dot image memory from the starting address of the first row of the page 101 shown in FIG. 3, and sets it in the address latch circuit AX8 and the address latch circuit Y9.

Generally, since data from a plurality of pages are combined, at least as many row dot image memories as the number of pages included in one scanning period are required.

On the other hand, the starting point shown in Fig. 6 is (0, 0), the ending point (Xe,
In the case where superscript 3 is added to the characters “X” and “Y”, ``x''IIY'' is written from the position (0, Y l) of the dot image memory. 3 means to write from the position (O1Y2). Therefore, when reading this data, write from the address (0, O
) It is necessary to read from the position (0, Y2), and the end point in the Y direction is not (0, Ye) but (0°Y3).
Therefore, for Y counter A16 or Y counter B17 shown in FIG.
It is configured to start counting from 2 and to be a Y ternary counter.

In the above explanation, an example has been described in which only the dot pattern from the character generator 7 is stored in the one-line dot image memory. When a character is needed, the controller 3 directly stores it in the row dot image memory, thereby generating the character generator 7 based on one character need data.
It is possible to print by mixing the original dot pattern with the directly sent pattern image data.

〔effect〕

As explained above, according to the present invention, when the #1 defeating page data is combined and printed on the same page, a small-capacity memory having a capacity of at least one line equal to the number of pages included in one line is provided. Inexpensive stamp IiI that can combine and print multiple pages of data at any position just by having the means
Equipment can be provided.

Furthermore, even when page data is to be combined over a long page, it can be performed using storage means with exactly the same storage capacity.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of an embodiment of the present invention. FIG. 2 is a detailed circuit diagram of the reading circuit shown in FIG. 1, and FIG. 3 is a diagram showing an example of composite data on the same page. FIG. 4 is a flowchart for controlling dot pattern storage in the row dot image memory of this embodiment. FIGS. 5 and 6 are diagrams showing examples of row dot image memory maps of this embodiment. In the figure, 3...control unit, 4...code page memory. 5... Work memory, 8, 9... Row dot image memory, 10-13... Start address tick circuit, 14.15... Dot number latch circuit, 16°17.
... Y counter, 18.19 ... Readout circuit, 21
. . . Synchronous clock generation unit, 22 . . . Image clock counter, 23. 26 . . . Comparison circuit, 24 . ... Digit counter, 33... End detection section,
34...P-5 conversion circuit. Figure 3 4wi

Claims (3)

[Claims] (1) In a printing device that combines and outputs a plurality of page information on the same page, there is provided a pattern storage means capable of storing dot patterns for at least one line of at least two printed pages, and a pattern storage means capable of storing dot patterns for at least one line of at least two printed pages; Holding means for holding the print output start position of the stored dot pattern in the pattern storage means, instruction means for instructing the current print position on the print page, an instruction value of the instruction means and a value held by each of the holding means. and an output means for reading and printing out a dot pattern from the corresponding pattern storage means for which a match has been detected by the detection means, according to the instruction value of the instruction means. printing device. (2) The instruction means is characterized by comprising a first counting means for counting the dot pattern output timing in the line direction of the printed page, and a second counting means for counting the number of print output dots in the digit direction of the printed page. A printing apparatus according to claim 1. (3) The printing apparatus according to claim 1 or 2, further comprising a pattern storage means for at least the number of page information to be combined per line of a printed page.