JPH0793682B2 - Image signal processor - Google Patents

Image signal processor

Info

Publication number
JPH0793682B2
JPH0793682B2 JP62045577A JP4557787A JPH0793682B2 JP H0793682 B2 JPH0793682 B2 JP H0793682B2 JP 62045577 A JP62045577 A JP 62045577A JP 4557787 A JP4557787 A JP 4557787A JP H0793682 B2 JPH0793682 B2 JP H0793682B2
Authority
JP
Japan
Prior art keywords
error
pixel
binarization
distribution
interest
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP62045577A
Other languages
Japanese (ja)
Other versions
JPS63212274A (en
Inventor
祐二 丸山
博義 土屋
克雄 中里
潔 高橋
俊晴 黒沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62045577A priority Critical patent/JPH0793682B2/en
Priority to EP87311205A priority patent/EP0272147B2/en
Priority to DE3751916T priority patent/DE3751916D1/en
Priority to EP92110386A priority patent/EP0507356B1/en
Priority to DE3751957T priority patent/DE3751957T2/en
Priority to DE3752022T priority patent/DE3752022T2/en
Priority to DE3785558T priority patent/DE3785558T3/en
Priority to EP92110032A priority patent/EP0507354B1/en
Priority to EP92110355A priority patent/EP0512578B1/en
Priority to US07/136,486 priority patent/US4891710A/en
Publication of JPS63212274A publication Critical patent/JPS63212274A/en
Publication of JPH0793682B2 publication Critical patent/JPH0793682B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Image Processing (AREA)
  • Facsimile Image Signal Circuits (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、階調画像を含む画像情報を2値再生する機能
を備えた画像信号処理装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal processing device having a function of binary-reproducing image information including a gradation image.

従来の技術 近年事務処理の機械化や画像通信の急速な普及に伴っ
て、従来の白黒2値原稿の他に、階調画像や印刷画像の
高品質での画像再現に対する要望が高まっている。
2. Description of the Related Art In recent years, along with the mechanization of office processing and the rapid spread of image communication, there has been an increasing demand for high-quality image reproduction of gradation images and printed images in addition to conventional black and white binary documents.

特に、階調画像の2値画像による擬似階調再現は、表示
装置や記録装置との適合性が良く多くの提案がなされて
いる。
In particular, many proposals have been made for the pseudo gradation reproduction by the binary image of the gradation image because of the good compatibility with the display device and the recording device.

これらの擬似階調再現の1つの手段として、ディザ法が
最もよく知られている。この方法は、予め定められた一
定面積において、その面積内に再現するドットの数によ
って階調を再現しようとするもので、ディザマトリック
スに用意した閾値と入力画情報を1画素毎に比較しなが
ら2値化処理を行っている。この方法は階調特性と分解
能がディザマトリックスの大きさに直接依存し、互いに
両立できない関係にある。また印刷画像などに用いた再
現画像におけるモアレ模様の発生は避けがたい。
The dither method is best known as one means for reproducing these pseudo gradations. This method attempts to reproduce gradation in a predetermined fixed area by the number of dots reproduced in that area. While comparing the threshold value prepared in the dither matrix with the input image information for each pixel. Binarization processing is performed. In this method, gradation characteristics and resolution are directly dependent on the size of the dither matrix, and are incompatible with each other. In addition, it is difficult to avoid the occurrence of moire patterns in reproduced images used for printed images.

上記階調特性と高分解能が両立し、かつモアレ模様の発
生抑制効果の大きい方法として、誤差拡散法〔アール.
フロイド アンド エル.スティンバーグ,“アン ア
ダプティブ アルゴリズムフォー スペイシャスル グ
レー スケール”エスアイディ75 ダイジェスト36〜37
ページ(文献:R.FLOYD&L.STEINBERG,“An Adaptive Al
gorithm for Spatial Gray Scale",SID 75 DIGEST,pp36
−37)〕が提案されている。
As a method that achieves both the gradation characteristics and high resolution and has a large effect of suppressing the generation of moire patterns, the error diffusion method [R.
Floyd and L. Stinberg, "Unadaptive Algorithm Force Spacious Gray Scale" SID 75 Digest 36-37
Page (Reference: R.FLOYD & L.STEINBERG, “An Adaptive Al
gorithm for Spatial Gray Scale ", SID 75 DIGEST, pp36
−37)] has been proposed.

第3図は上記誤差拡張法を実現するための装置の要部ブ
ロック図である。
FIG. 3 is a block diagram of a main part of an apparatus for realizing the error extension method.

原画像における注目画素の座標を(x,y)とするとき、3
01は誤差記憶手段、302は誤差配分係数マトリックスの
示す注目画素の周辺の未処理画素領域、303は座標(x,
y)における集積誤差Sxyの記憶位置、304は座標(x,y)
における入力レベルIxyの入力端子、305はI′xy(=Ix
y+Sxy)の入力補正手段、306は出力レベル0またはR
の2値信号Pxyの出力端子、307は一定閾値R/2を印加す
る信号端子、308は入力信号I′xyと一定閾値R/2を比較
してI′xy>R/2の時Pxy=Rを、その他の場合はPxy=
0を出力する2値化手段、309はExy(=I′xy−Pxy)
の注目画素に対する2値化誤差を求める差分演算手段で
ある。
When the coordinates of the pixel of interest in the original image are (x, y), 3
01 is the error storage means, 302 is the unprocessed pixel area around the pixel of interest indicated by the error distribution coefficient matrix, and 303 is the coordinate (x,
storage position of accumulated error Sxy in y), and 304 is coordinate (x, y)
Input terminal of input level Ixy at 305, I'xy (= Ix
y + Sxy) input correction means, 306 is output level 0 or R
Output terminal of the binary signal Pxy, 307 is a signal terminal for applying a constant threshold value R / 2, 308 is a comparison between the input signal I′xy and the constant threshold value R / 2, and when I′xy> R / 2, Pxy = R, otherwise Pxy =
Binarizing means for outputting 0, 309 is Exy (= I'xy-Pxy)
It is a difference calculation means for obtaining a binarization error for the pixel of interest.

さて、注目画素に対する集積誤差Sxyは第(1),
(2)式で表される。
Now, the integration error Sxy for the pixel of interest is (1),
It is expressed by equation (2).

Sxy=ΣKij・Ex−j+2 ……(1) (但し、i,jは誤差配分係数マトリックス内の座標を示
す) この誤差配分係数Kijは誤差Exyの注目画素の周辺画素へ
の配分の重み付けをするもので前記文献では ……(2) (但し、*は注目画素の位置) を例示している。
Sxy = ΣKij · Ex−j + 2 (1) (where i and j represent coordinates in the error distribution coefficient matrix) The error distribution coefficient Kij weights the distribution of the error Exy to the peripheral pixels of the target pixel. In the above literature ... (2) (where * is the position of the pixel of interest).

第3図の構成では、上記の演算は注目画素に対する2値
化誤差Exyに、未処理の周辺画素領域302内の各画素A〜
Dに対応する配分係数を乗算し、誤差記憶手段301内の
値に加算し再び該当位置へ記憶させる誤差配分演算手段
310によって実現している。ただし、誤差記憶手段301の
画素位置Bの集積誤差は予め0にクリアされている。
In the configuration shown in FIG. 3, the above calculation results in the binarization error Exy for the pixel of interest and each pixel A to A in the unprocessed peripheral pixel region 302.
Error distribution calculation means for multiplying D by a distribution coefficient corresponding to D, adding to the value in the error storage means 301, and storing again in the corresponding position
It is realized by 310. However, the integration error at the pixel position B of the error storage means 301 is cleared to 0 in advance.

発明が解決しようとする問題点 さて上記の誤差拡散法は、ディザ法に比して階調特性や
分解能の点で優れた性能を持ち、印刷画像を再現時にお
いてもモアレ模様の出現は極めて少く、原理的には入力
レベルIxyのすべてのレベルに応じた黒画素(または白
画素)密度の階調を再現できる方式である。
Problems to be Solved by the Invention The error diffusion method described above has excellent performance in terms of gradation characteristics and resolution compared to the dither method, and the appearance of moire patterns is extremely small even when reproducing a printed image. , In principle, it is a method that can reproduce the gradation of black pixel (or white pixel) density according to all the levels of the input level Ixy.

しかし、上記の処理方式を実用的な整数演算型の処理回
路で実現しようとすると、2値化誤差Exyと周辺画素へ
の誤差配分値の総和ΣKij・Exyが必ずしも一致しない。
このことは、2値化誤差Exyのすべての値を周辺画素に
配分していないことを意味し、入力レベルIxyの全レベ
ルに対応した階調を再現できず、特に入力レベルIxyが
低濃度および高濃度レベルのとき、この現象が顕著で、
階調再現領域が狭められた再生画素となる。
However, if it is attempted to implement the above processing method by a practical integer arithmetic processing circuit, the binarization error Exy and the sum ΣKij · Exy of the error distribution values to the peripheral pixels do not necessarily match.
This means that all the values of the binarization error Exy are not distributed to the peripheral pixels, and the gradation corresponding to all the levels of the input level Ixy cannot be reproduced. At high concentration levels this phenomenon is noticeable,
The reproduction pixel has a narrow gradation reproduction area.

本発明は、上記の誤差拡散法の実施に当って階調再現特
性を改良し、モアレ模様の極めて少い画像信号処理装置
を提供するものである。
The present invention provides an image signal processing apparatus which has improved tone reproduction characteristics when the above-mentioned error diffusion method is implemented and has an extremely small number of moire patterns.

問題点を解決するための手段 本発明は、画素単位でサンプリングした多階調の濃度レ
ベルを2値化する際に、注目画素の2値化誤差をその周
辺の画素位置に対応させて記憶する誤差記憶手段と、前
記注目画素の入力レベルと前記誤差記憶手段内の注目画
素位置に対応した集積誤差を加算し補正レベルを出力す
る入力補正手段と、前記補正レベルを予め定められた閾
値と比較し注目画素の2値化レベルを決定する2値化手
段と、前記補正レベルと2値化レベルの差分である2値
化誤差Exyを求める差分演算手段と、前記2値化誤差Exy
より下位nビットを抽出し剰余誤差Exylとして出力しさ
らに前記2値化誤差Exyの下位nビットを“0"で補填し
新たな2値化誤差Exyuとして出力する2値化誤差配分手
段と、前記2値化誤差を前記注目画素の周辺の未処理画
素に配分する配分係数を発生させる配分係数発生手段
と、前記2値化誤差配分手段から新たな2値化誤差Exyu
と前記配分係数発生手段からの配分係数とから注目画素
周辺の未処理画素に対応する誤差配分値を演算する誤差
配分値演算手段と、前記誤差配分値の内の1つと前記2
値化誤差配分手段からの剰余誤差Exylとを加算し、残り
の誤差配分値とともに前記誤差記憶手段内の対応する画
素位置の集積誤差とを加算し再び記憶させる誤差更新手
段とを設けたものである。
Means for Solving the Problems According to the present invention, when binarizing multi-tone density levels sampled on a pixel-by-pixel basis, the binarization error of the pixel of interest is stored in association with the pixel positions in the surroundings. Error storage means, input correction means for adding the input level of the pixel of interest and integrated error corresponding to the position of the pixel of interest in the error storage means and outputting a correction level, and comparing the correction level with a predetermined threshold value. Then, a binarizing unit that determines the binarizing level of the pixel of interest, a difference calculating unit that obtains a binarizing error Exy that is a difference between the correction level and the binarizing level, and the binarizing error Exy.
A binarization error distribution means for extracting the lower n bits and outputting as a remainder error Exyl, and further complementing the lower n bits of the binarization error Exy with “0” and outputting as a new binarization error Exyu; A distribution coefficient generating unit that generates a distribution coefficient that distributes the binarization error to unprocessed pixels around the target pixel, and a new binarization error Exyu from the binarization error distribution unit.
Error distribution value calculating means for calculating an error distribution value corresponding to an unprocessed pixel around the pixel of interest from the distribution coefficient from the distribution coefficient generating means, one of the error distribution values, and
An error updating means for adding the residual error Exyl from the binarizing error distributing means, adding the remaining error distribution value and the integrated error of the corresponding pixel position in the error storing means and storing again is provided. is there.

作用 本発明は上記構成により、2値化誤差Exyの下位nビッ
トを剰余誤差Exylとして注目画素の周辺画素の1つに配
分し、2値化誤差Exyの下位nビットに“0"を補填した
新たな2値化誤差Exyuを配分係数に従って周辺画素に配
分することにより、2値化誤差と周辺画素の誤差配分値
の総和を一致させ入力レベルの低濃度および高濃度領域
の階調再現特性を改良し、モアレ模様が発生しないよう
にしたものである。
According to the present invention, the lower n bits of the binarization error Exy are distributed to one of the peripheral pixels of the pixel of interest as the residual error Exyl by the above configuration, and "0" is filled in the lower n bits of the binarization error Exy. By distributing the new binarization error Exyu to the peripheral pixels according to the distribution coefficient, the sum of the binarization error and the error distribution value of the peripheral pixels is made to coincide, and the gradation reproduction characteristics of the low-density and high-density areas of the input level are It has been improved so that moire patterns do not occur.

実施例 第1図は本発明の一実施例における画像信号処理装置の
要部ブロック構成図である。
Embodiment FIG. 1 is a block diagram of the essential parts of an image signal processing apparatus in an embodiment of the present invention.

同図において、101〜109の各ブロックの構成と作用は第
3図の従来の誤差拡散法の301〜309の各部と同様であ
る。第1図において、第3図の構成と異なる点は、誤差
配分値演算手段110、配分係数発生手段111、誤差更新手
段112、2値化誤差配分手段113を設けた点であり、以下
これらについて詳細に述べる。
In the figure, the configuration and operation of each block of 101 to 109 is the same as that of each section of 301 to 309 of the conventional error diffusion method of FIG. 1 is different from the configuration of FIG. 3 in that an error distribution value calculating means 110, a distribution coefficient generating means 111, an error updating means 112, and a binarization error distributing means 113 are provided. Describe in detail.

2値化誤差配分手段113は、2値化誤差Exyより下位nビ
ットを抽出し剰余誤差Exylとして誤差更新手段112に出
力し、2値化誤差Exyの下位nビットに“0"を補填し新
たな2値化誤差Exyuとして誤差配分値演算手段110に出
力する。
The binarization error distribution unit 113 extracts the lower n bits from the binarization error Exy and outputs it as a residual error Exyl to the error updating unit 112, and supplements the lower n bits of the binarization error Exy with “0” to newly add it. The binary distribution error Exyu is output to the error distribution value calculation means 110.

配分係数発生手段111は、注目画素周辺の未処理画素に
対する配分係数セットを予め用意し、周辺画素領域102
内の画素位置A〜Dに対する前記新たな2値化誤差Exyu
の配分係数KA〜KDを誤差配分値演算手段110へ出力す
る。
The distribution coefficient generation means 111 prepares a distribution coefficient set for unprocessed pixels around the target pixel in advance,
The new binarization error Exyu for pixel positions A to D in
The distribution coefficients KA to KD are output to the error distribution value calculation means 110.

さて誤差配分値演算手段110では、画素処理周期に同期
した同期信号に同期しながら、前記配分係数KA〜KDと差
分演算手段109からの注目画素に対する新たな2値化誤
差Exyuとで誤差記憶手段101の周辺画素領域102内の画素
位置A,B,C,Dに対応する誤差配分値GA〜GDを下記第
(3)式により求める。
Now, in the error distribution value calculation means 110, the error storage means with the distribution coefficients KA to KD and the new binarization error Exyu for the target pixel from the difference calculation means 109 is synchronized with the synchronization signal synchronized with the pixel processing cycle. The error distribution values GA to GD corresponding to the pixel positions A, B, C and D in the peripheral pixel area 102 of 101 are obtained by the following formula (3).

GA=KA×Exyu GB=KB×Exyu GC=KC×Exyu ……(3) GD=KD×Exyu さらに誤差更新手段112に誤差配分値GA〜GDを出力す
る。
GA = KA × Exyu GB = KB × Exyu GC = KC × Exyu (3) GD = KD × Exyu Further, the error distribution values GA to GD are output to the error updating means 112.

誤差更新手段112は、前記同期信号に同期しながら、誤
差配分値演算手段110からの誤差配分値GA〜GDと2値化
誤差配分手段113からの剰余誤差Exylと誤差記憶手段101
の周辺画素領域102内の画素位置A,B,C,Dに対応する記憶
装置に記憶されているそれ以前の画素処理過程における
集積誤差SA′・SC′・SD′を読み出し、新たな集積誤差
SA〜SDを下記第(4)式により求める。
The error updating means 112 synchronizes with the synchronization signal, and the error distribution values GA to GD from the error distribution value computing means 110, the residual error Exyl from the binarization error distribution means 113, and the error storage means 101.
The integrated errors SA ′, SC ′, SD ′ in the previous pixel processing process stored in the storage device corresponding to the pixel positions A, B, C, D in the peripheral pixel region 102 of
SA to SD are calculated by the following formula (4).

SA=SA′+GA SB=Exyl+GB SC=SC′+GC ……(4) SD=SD′+GD さらに、誤差更新手段112は新たな集積誤差SA〜SDを誤
差記憶手段101の画素位置A〜Dに対応する記憶装置に
書込む更新処理をする。
SA = SA '+ GA SB = Exyl + GB SC = SC' + GC (4) SD = SD '+ GD Further, the error updating means 112 corresponds the new integrated errors SA to SD to the pixel positions A to D of the error storing means 101. Update processing for writing in the storage device.

ただし、第(4)式では剰余誤差Exylを周辺画素領域10
2内の画素位置Bに加算したが、画素位置A,B,C,Dの内い
ずれかの位置に加算してもよく、以後画素位置Bに加算
するものとして説明する。
However, in the formula (4), the residual error Exyl is set to the peripheral pixel area 10
Although the pixel position B in 2 is added, the pixel position B may be added to any of the pixel positions A, B, C, and D, and the pixel position B will be described later.

これら誤差配分値演算手段110と配分係数発生手段111と
誤差更新手段112および2値化誤差配分手段113の具体的
構成を第2図に示す。同図において剰余誤差Exylは周辺
画素位置Bに反映させるものとして、以下に説明する。
FIG. 2 shows a specific configuration of the error distribution value calculating means 110, the distribution coefficient generating means 111, the error updating means 112, and the binarization error distributing means 113. In the figure, the residual error Exyl will be described below as being reflected on the peripheral pixel position B.

配分係数発生手段205は配分係数KA〜KDを予め格納する
ために記憶手段206を設け画素処理の開始に先だって収
納する。また、記憶手段206は配分係数KA〜KDを予め書
込んだROM(リード・オンリ・メモリ)を用いてもよ
い。
The distribution coefficient generation means 205 is provided with a storage means 206 for storing the distribution coefficients KA to KD in advance, and stores them before starting the pixel processing. Further, the storage unit 206 may use a ROM (Read Only Memory) in which the distribution coefficients KA to KD are written in advance.

2値化誤差配分手段203は、前記2値化誤差Exyの下位n
ビットに“0"を補填するビット配分手段208の出力を新
たな2値化誤差Exyuとして誤差配分値演算手段207に出
力し、前記2値化誤差Exyの下位nビットを抽出し配分
するビット配分手段209の出力を剰余誤差Exylとして誤
差更新手段210に出力する。
The binarization error distribution means 203 is a lower order n of the binarization error Exy.
The output of the bit allocating means 208 for compensating the bits with “0” is output to the error allocating value calculating means 207 as a new binarizing error Exyu, and the lower n bits of the binarizing error Exy are extracted and distributed. The output of the means 209 is output to the error updating means 210 as the residual error Exyl.

前記誤差配分値演算手段207は、前記新たな2値化誤差E
xyuと前記配分係数KA〜KDとから誤差配分値GA〜GDを乗
算し求め、前記誤差更新手段210に出力する。
The error distribution value calculation means 207 uses the new binarization error E.
The error distribution values GA to GD are multiplied by xyu and the distribution coefficients KA to KD, and output to the error updating means 210.

前記誤差更新手段210は、同期信号入力端子204から入力
した画素処理に同期した同期信号214に同期しながら、
誤差配分値GAと誤差記憶手段201より読込んだ画素位置
Aに対応する集積誤差S′Aを加算し次の画素処理にお
ける集積誤差Sxyとして使用するため内部レジスタ211
(RA)に一時記憶する。画素位置Bに対する集積誤差は
誤差配分値GBと2値化誤差配分手段203からの剰余誤差E
xylと加算し画素位置Bに対応する集積誤差(SB)とし
て内部レジスタ212(RB)に一時記憶する。誤差配分値G
Cと前記画素処理において一時記憶している内部レジス
タ212(RB)のデータを加算し画素位置Cの集積誤差(S
C)として内部レジスタ213(RC)に一時記憶する。誤差
配分値GDと前記画素処理において一時記憶している内部
レジスタ213(RC)のデータとを加算し画素位置Dの集
積誤差(SD)として誤差記憶手段201の画素位置Dに対
応する記憶装置に記憶させる。
The error updating means 210, while synchronizing with the synchronizing signal 214 synchronized with the pixel processing input from the synchronizing signal input terminal 204,
The internal register 211 for adding the error distribution value GA and the integrated error S′A corresponding to the pixel position A read from the error storage means 201 and using it as the integrated error Sxy in the next pixel processing
Temporarily store in (RA). The integration error for the pixel position B is the error distribution value GB and the residual error E from the binarization error distribution means 203.
It is added to xyl and temporarily stored in the internal register 212 (RB) as an integrated error (SB) corresponding to the pixel position B. Error allocation value G
C and the data of the internal register 212 (RB) temporarily stored in the pixel processing are added to obtain the integration error (S
It is temporarily stored in the internal register 213 (RC) as C). The error distribution value GD and the data of the internal register 213 (RC) temporarily stored in the pixel processing are added to obtain a storage error corresponding to the pixel position D of the error storage means 201 as an integrated error (SD) of the pixel position D. Remember.

このような誤差更新手段210により、誤差記憶手段201内
の記憶装置へのアクセスは、画素位置Aに対応する読込
みアクセスと画素位置Dに対応する書込みアクセスのみ
となり、容易に実現可能な構成となる。
By such an error updating means 210, the storage device in the error storage means 201 can be accessed only by the read access corresponding to the pixel position A and the write access corresponding to the pixel position D, which is a readily feasible configuration. .

発明の効果 以上のように本発明では、2値化誤差Exyより下位nビ
ットを抽出し剰余誤差Exylとして注目画素の周辺の1つ
に配分し、さらに2値化誤差Exyの下位nビットに“0"
を補填した新たな2値化誤差Exyuを配分係数に従って周
辺画素に配分することにより、配分係数との演算時に発
生した切捨誤差を抑え2値化誤差Exyと注目画素の周辺
画素に配分された誤差配分値の総和とを一致させ、誤差
拡散法を実用的な整数演算型の処理回路で構成したとき
に問題となった入力レベルの低濃度および高濃度領域の
階調再現特性が大幅に改善され、実用的な処理が可能と
なった。
As described above, according to the present invention, the lower n bits of the binarization error Exy are extracted and distributed to one of the peripherals of the pixel of interest as the remainder error Exyl, and the lower n bits of the binarization error Exy are set to “n”. 0 "
By distributing the new binarization error Exyu, which has been compensated for, to the peripheral pixels according to the distribution coefficient, the truncation error generated during the calculation with the distribution coefficient is suppressed and the binarization error Exy and the peripheral pixels of the target pixel are distributed. The tone reproduction characteristics in the low and high density areas of the input level, which was a problem when the error diffusion method was configured with a practical integer arithmetic processing circuit by matching the sum of error distribution values, was greatly improved. The practical processing became possible.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の一実施例における画像信号処理装置の
要部ブロック構成図、第2図は同装置における誤差配分
値演算手段と配分係数発生手段と誤差更新手段および2
値化誤差配分手段のブロック構成図、第3図は従来の誤
差拡散法を実施する画像信号処理装置の要部ブロック構
成図である。 101,102…誤差記憶手段、110…誤差配分値演算手段、11
1…配分係数発生手段、112…誤差更新手段、113,203…
2値化誤差配分手段、206…記憶手段、211〜213…内部
レジスタ。
FIG. 1 is a block diagram of a main part of an image signal processing apparatus according to an embodiment of the present invention, and FIG. 2 is an error distribution value calculating means, a distribution coefficient generating means, an error updating means and 2 in the apparatus.
FIG. 3 is a block configuration diagram of the binarization error distribution means, and FIG. 3 is a block configuration diagram of a main part of an image signal processing device for implementing the conventional error diffusion method. 101, 102 ... Error storage means, 110 ... Error distribution value calculation means, 11
1 ... Allocation coefficient generating means, 112 ... Error updating means, 113, 203 ...
Binary error distribution means, 206 ... Storage means, 211-213 ... Internal registers.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 高橋 潔 神奈川県川崎市多摩区東三田3丁目10番1 号 松下技研株式会社内 (72)発明者 黒沢 俊晴 神奈川県川崎市多摩区東三田3丁目10番1 号 松下技研株式会社内 (56)参考文献 特開 昭57−125579(JP,A) 特開 昭61−48275(JP,A) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kiyoshi Takahashi Kiyoshi Takahashi 3-10-1 Higashisanda, Tama-ku, Kawasaki, Kanagawa Matsushita Giken Co., Ltd. (72) Toshiharu Kurosawa 3-chome, Higashisanda, Tama-ku, Kawasaki-shi, Kanagawa No. 10 No. 1 in Matsushita Giken Co., Ltd. (56) Reference JP-A-57-125579 (JP, A) JP-A-61-48275 (JP, A)

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】画素単位でサンプリングした多階調の濃度
レベルを2値化する際に、注目画素の2値化誤差をその
周辺の画素位置に対応させて記憶する誤差記憶手段と、
前記注目画素の入力レベルと前記誤差記憶手段内の注目
画素位置に対応した集積誤差を加算し補正レベルを出力
する入力補正手段と、前記補正レベルを予め定められた
閾値と比較し注目画素の2値化レベルを決定する2値化
手段と、前記補正レベルと前記2値化レベルの差分であ
る2値化誤差Exyを求める差分演算手段と、前記2値化
誤差Exyより下位nビットを抽出し剰余誤差Exylとして
出力しさらに前記2値化誤差Exyの下位nビットを“0"
で補填し新たな2値化誤差Exyuとして出力する2値化誤
差配分手段と、前記新たな2値化誤差Exyuを前記注目画
素の周辺の未処理画素に配分する配分係数を発生させる
配分係数発生手段と、前記2値化誤差配分手段からの新
たな2値化誤差Exyuと前記配分係数発生手段からの配分
係数とから注目画素周辺の未処理画素に対応する誤差配
分値を演算する誤差配分値演算手段と、前記誤差配分値
の内の1つと前記2値化誤差配分手段からの剰余誤差Ex
ylとを加算し、残りの誤差配分値とともに前記誤差記憶
手段内の対応する画素位置の集積誤差とを加算し再び記
憶させる誤差更新手段とを具備する画像信号処理装置。
1. An error storage means for storing a binarization error of a pixel of interest in association with a pixel position in the vicinity thereof when binarizing a multi-tone density level sampled in pixel units.
The input correction means for adding the input level of the pixel of interest and the integrated error corresponding to the position of the pixel of interest in the error storage means and outputting the correction level, and the correction level is compared with a predetermined threshold value to obtain 2 pixels of the pixel of interest. Binarization means for determining a binarization level, difference calculation means for obtaining a binarization error Exy which is a difference between the correction level and the binarization level, and extracting lower n bits from the binarization error Exy. Output as a remainder error Exyl, and further output the lower n bits of the binarization error Exy to "0".
And a binarization error distribution means for generating a new binarization error Exyu to be distributed to unprocessed pixels around the pixel of interest. Means, and an error distribution value for calculating an error distribution value corresponding to an unprocessed pixel around the target pixel from the new binarization error Exyu from the binarization error distribution means and the distribution coefficient from the distribution coefficient generation means. Arithmetic means, one of the error distribution values, and the residual error Ex from the binarization error distribution means
and an error updating unit for adding the accumulated error of the corresponding pixel position in the error storage unit and storing the result again.
JP62045577A 1986-12-19 1987-02-27 Image signal processor Expired - Fee Related JPH0793682B2 (en)

Priority Applications (10)

Application Number Priority Date Filing Date Title
JP62045577A JPH0793682B2 (en) 1987-02-27 1987-02-27 Image signal processor
EP87311205A EP0272147B2 (en) 1986-12-19 1987-12-18 Bi-level image display signal processing apparatus
DE3751916T DE3751916D1 (en) 1986-12-19 1987-12-18 Device for processing signals for displaying images with two levels
EP92110386A EP0507356B1 (en) 1986-12-19 1987-12-18 Bi-level image display signal processing apparatus
DE3751957T DE3751957T2 (en) 1986-12-19 1987-12-18 Device for processing signals for displaying images with two levels
DE3752022T DE3752022T2 (en) 1986-12-19 1987-12-18 Device for processing signals for displaying images with two levels
DE3785558T DE3785558T3 (en) 1986-12-19 1987-12-18 Device for processing signals for displaying images with two levels.
EP92110032A EP0507354B1 (en) 1986-12-19 1987-12-18 Bi-level image display signal processing apparatus
EP92110355A EP0512578B1 (en) 1986-12-19 1987-12-18 Bi-level image display signal processing apparatus
US07/136,486 US4891710A (en) 1986-12-19 1987-12-21 Bi-level image display signal processing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62045577A JPH0793682B2 (en) 1987-02-27 1987-02-27 Image signal processor

Publications (2)

Publication Number Publication Date
JPS63212274A JPS63212274A (en) 1988-09-05
JPH0793682B2 true JPH0793682B2 (en) 1995-10-09

Family

ID=12723202

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62045577A Expired - Fee Related JPH0793682B2 (en) 1986-12-19 1987-02-27 Image signal processor

Country Status (1)

Country Link
JP (1) JPH0793682B2 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6148275A (en) * 1984-08-16 1986-03-08 Matsushita Electric Ind Co Ltd Picture signal processor

Also Published As

Publication number Publication date
JPS63212274A (en) 1988-09-05

Similar Documents

Publication Publication Date Title
JP3322522B2 (en) Color image processing equipment
JPS63209370A (en) Image signal processor
JPH0793682B2 (en) Image signal processor
JPH0666873B2 (en) Image signal processor
JPH0722333B2 (en) Image signal processor
JPH0666875B2 (en) Image signal processor
JPH0722334B2 (en) Image signal processor
JPH06105953B2 (en) Image signal processor
JPH01238373A (en) Picture signal processor
JPH0681257B2 (en) Image signal processor
JPH0666876B2 (en) Image signal processor
JPH079672B2 (en) Image signal processor
JPH0824339B2 (en) Image signal processor
JPH0666874B2 (en) Image signal processor
JPH0824338B2 (en) Image signal processor
JPH0155795B2 (en)
JPH06103922B2 (en) Image signal processor
JPS63155956A (en) Picture signal processor
JP3089857B2 (en) Image processing method used for halftone image reproduction
JP2839095B2 (en) Image processing device
JP3094810B2 (en) Color image processing equipment
JPH02107062A (en) Picture signal processor
JPS6148275A (en) Picture signal processor
JPH08214156A (en) Image processing unit
JP3305835B2 (en) Halftone image dot processing device

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees