JPH0666876B2 - Image signal processor - Google Patents

Image signal processor

Info

Publication number
JPH0666876B2
JPH0666876B2 JP61304249A JP30424986A JPH0666876B2 JP H0666876 B2 JPH0666876 B2 JP H0666876B2 JP 61304249 A JP61304249 A JP 61304249A JP 30424986 A JP30424986 A JP 30424986A JP H0666876 B2 JPH0666876 B2 JP H0666876B2
Authority
JP
Japan
Prior art keywords
error
pixel
binarization
level
distribution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP61304249A
Other languages
Japanese (ja)
Other versions
JPS63155954A (en
Inventor
祐二 丸山
克雄 中里
博義 土屋
俊晴 黒沢
潔 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP61304249A priority Critical patent/JPH0666876B2/en
Priority to DE3785558T priority patent/DE3785558T3/en
Priority to EP92110355A priority patent/EP0512578B1/en
Priority to EP92110032A priority patent/EP0507354B1/en
Priority to DE3751916T priority patent/DE3751916D1/en
Priority to DE3751957T priority patent/DE3751957T2/en
Priority to EP92110386A priority patent/EP0507356B1/en
Priority to EP87311205A priority patent/EP0272147B2/en
Priority to DE3752022T priority patent/DE3752022T2/en
Priority to US07/136,486 priority patent/US4891710A/en
Publication of JPS63155954A publication Critical patent/JPS63155954A/en
Publication of JPH0666876B2 publication Critical patent/JPH0666876B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、階調画像を含む画像情報を2値再生する機能
を備えた画像信号処理装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal processing device having a function of binary-reproducing image information including a gradation image.

従来の技術 近年事務処理の機械化や画像通信の急速な普及に伴っ
て、従来の白黒2値原稿の他に、階調画像や印刷画像の
高品質で画像再現に対する要望が高まっている。
2. Description of the Related Art In recent years, along with the mechanization of office processing and the rapid spread of image communication, there is an increasing demand for high-quality image reproduction of gradation images and printed images in addition to conventional black and white binary documents.

特に、階調画像の2値画像による擬似階調再現は、表示
装置や記録装置との適合性が良く多くの提案がなされて
いる。
In particular, many proposals have been made for the pseudo gradation reproduction by the binary image of the gradation image because of the good compatibility with the display device and the recording device.

これらの擬似階調再現の1つの手段として、ディザ法が
最もよく知られている。この方法は、予め定められた一
定面積において、その面積内に再現するドットの数によ
って階調を再現しようとするもので、ディザマトリック
スに用意した閾値と入力画情報を1画素毎に比較しなが
ら2値化処理を行っている。この方法は階調特性と分解
能がディザマトリクスの大きさに直接依存し、互いに両
立できない関係にある。また印刷画像などに用いた再現
画像におけるモアレ模様の発生は避けがたい。
The dither method is best known as one means for reproducing these pseudo gradations. This method attempts to reproduce gradation in a predetermined fixed area by the number of dots reproduced in that area. While comparing the threshold value prepared in the dither matrix with the input image information for each pixel. Binarization processing is performed. In this method, the gradation characteristics and the resolution directly depend on the size of the dither matrix, and are incompatible with each other. In addition, it is difficult to avoid the occurrence of moire patterns in reproduced images used for printed images.

上記階調特性と高分解能が両立し、かつモアレ模様の発
生抑制効果が大きい方法として、誤差拡差拡散法(文
献:アール(R).フロード アンド(FLOYD &).
エル(L).ステインバーグ(STEINBERG)、“アン
アダプテイブ アルゴリズム フオー スペイシヤル
グレー スケール(An Adaptive Algorithm for Sp
atial Grey Scale)”、エスデイアイ(SDI) 75
ダイジエスト(DIGEST)、pp36−37)が提案されてい
る。
As a method in which the gradation characteristics and high resolution are compatible with each other and the moire pattern generation suppressing effect is large, the error difference diffusion method (reference: R. FROOD & FLOYD &.
L (L). STEINBERG, “Ann
Adaptive Algorithm Forspeech
Gray Scale (An Adaptive Algorithm for Sp
atial Gray Scale) ”, esd eye (SDI) 75
DIGEST, pp36-37) has been proposed.

第3図は上記誤差拡散法を実現するための装置の要部ブ
ロック図である。
FIG. 3 is a block diagram of an essential part of an apparatus for realizing the above error diffusion method.

原画像における注目画素の座標を、(x,y)とするとき
は、1は誤差記憶手段、2は誤差配分係数マトリクスの
示す注目画素の周辺の未処理画素領域、3は座標(x,
y)における集積誤差Sxyの記憶位置、4は座標(x,y)
における入力レベルIxyの入力端子、5はI′xy(=Ixy
+Sxy)の入力補正手段、6は出力レベル0またはRの
出力画信号Pxyの出力端子、7は一定閾値R/2を印加
する信号端子、8は入力信号I′xyと一定閾値R/2を
比較してI′xy>R/2の時Pxy=Rを、その他の場合
はPxy=0を出力する2値化手段、9はExy(=I′xy−
Pxy)の注目画素に対する2値化誤差を求める差分演算
手段である。
When the coordinates of the pixel of interest in the original image are (x, y), 1 is the error storage means, 2 is the unprocessed pixel area around the pixel of interest indicated by the error distribution coefficient matrix, and 3 is the coordinate (x, y).
Storage position of accumulated error Sxy in y), 4 is coordinate (x, y)
Input terminal of input level Ixy at 5 is I'xy (= Ixy
+ Sxy) input correction means, 6 is an output terminal of an output image signal Pxy of output level 0 or R, 7 is a signal terminal for applying a constant threshold value R / 2, and 8 is an input signal I′xy and a constant threshold value R / 2. In comparison, a binarizing means for outputting Pxy = R when I'xy> R / 2 and Pxy = 0 otherwise, 9 is Exy (= I'xy-
Pxy) is a difference calculation means for obtaining a binarization error for the pixel of interest.

さて、注目画素に対する集積誤差Sxyは第(1)、
(2)式で表される。
Now, the integration error Sxy for the pixel of interest is (1),
It is expressed by equation (2).

Sxy=ΣKij・Ex−j,y−i+1 …(1) (但し、i,jは誤差配分係数マトリクス内の座標を示
す)この誤差配分係数Kijは誤差Exyの注目画素の周辺画
素への配分の重み付けをするもので前記文献では (但し、*は注目画素の位置) を例示している。
Sxy = ΣKij · Ex −j, y−i + 1 (1) (where i and j indicate coordinates in the error distribution coefficient matrix) This error distribution coefficient Kij is the distribution of the error Exy to the peripheral pixels of the target pixel. In the above literature, (However, * indicates the position of the pixel of interest).

第3図の構成では、上記の演算は注目画素に対する2値
化誤差Exyに、未処理の周辺画素領域2内の各画素A〜
Dに対応する配分係数を乗算し、誤差記憶手段1内の値
に加算し再び該当位置へ記憶させる誤差配分演算手段10
によって実現している。ただし、誤差記憶手段1の画素
位置Bの集積誤差は予め0にクリアされている。
In the configuration shown in FIG. 3, the above calculation results in the binarization error Exy for the pixel of interest and each pixel A to A in the unprocessed peripheral pixel region 2.
Error distribution calculation means 10 for multiplying the distribution coefficient corresponding to D, adding to the value in the error storage means 1 and storing again in the corresponding position
Is realized by. However, the integration error at the pixel position B of the error storage means 1 is cleared to 0 in advance.

発明が解決しようとする問題点 さて上記の誤差拡散法は、ディザ法に比して階調特性や
分解能の点で優れた性能を持ち、印刷画像の再現時にお
いてもモアレ模様の出現は極めて少い。しかし、濃度変
化の少い画像や計算機で生成された均一な濃度の画像な
どでは方式特有の模様(テクスチャ)が発生するため、
ほとんど普及していない。このテクスチャの発生の主た
る原因は、注目画素の周辺画素に対する2値化誤差の配
分の割合が注目画素と常に一定の相対的位置関係に保持
されているためである。
Problems to be Solved by the Invention The error diffusion method described above has excellent performance in terms of gradation characteristics and resolution compared to the dither method, and the appearance of moire patterns is extremely small even when reproducing a printed image. Yes. However, the pattern (texture) peculiar to the method occurs in an image with little change in density or an image with uniform density generated by a computer.
It is hardly popular. The main cause of the occurrence of this texture is that the ratio of the binarization error distribution to the peripheral pixels of the target pixel is always held in a constant relative positional relationship with the target pixel.

また、上記誤差拡散法の構成では、1画素処理が多段の
演算となるために高速な画像処理装置を得ることは困難
である。
Further, with the above-described configuration of the error diffusion method, it is difficult to obtain a high-speed image processing device because one pixel processing is a multi-stage calculation.

本発明は上記誤差拡散法におけるテクスチャの発生を抑
制し、階調特性・分解能に優れ、かつ印刷画像の再生時
にもモアレ模様の極めて少く、高速処理が可能な画像信
号処理装置を提供するものである。
The present invention provides an image signal processing apparatus that suppresses the occurrence of texture in the error diffusion method, is excellent in gradation characteristics and resolution, has very few moire patterns even when a printed image is reproduced, and is capable of high-speed processing. is there.

問題点を解決するための手段 本発明は、画素単位でサンプリングした多階調の濃度レ
ベルを2値化する際に、注目画素の2値化誤差をその周
辺の画素位置に対応させて記憶する誤差記憶手段と、注
目画素の入力レベルと前記誤差記憶手段内の注目画素位
置に対応した集積誤差を加算レジスタに一時記憶し補正
レベルを出力する入力補正手段と、前記補正レベルを2
値化レベルの2状態で予らかじめ並列に差分を求めてそ
れぞれのレジスタに一時記憶し差分レベルAと差分レベ
ルBを出力する差分演算手段と、前記差分レベルAと差
分レベルBと前画素処理時に一時記憶しておいた2値化
誤差とをそれぞれに加算し誤差Aと誤差Bを求め、誤差
Aを予め定められた閾値と比較し注目画素の2値化レベ
ルを決定し、この2値化レベルにより誤差Aあるいは誤
差Bを選択し新な2値化誤差を得レジスタに一時記憶し
て次の画素処理の際に2値化誤差とする2値化手段と、
前記2値化誤差を注目画素の周辺の未処理画素に配分す
る配分係数を、予め定められた変更周期で、複数組の配
分係数セットの中から任意副走査ライン毎に任意に初期
設定された乱数発生に従って発生させる配分係数発生手
段と、前記差分演算手段からの差分と前記配分係数発生
手段からの複数の配分係数から注目画素周辺の未処理画
素に対応する誤差配分値を算出し、前記誤差配分値を前
記誤差記憶手段内の対応する画素位置の集積誤差とを加
算し新な集積画素とし再び記憶させる誤差配分・更新手
段から成る画像信号処理装置を構成し、上記目的を達成
しようとするものである。
Means for Solving the Problems According to the present invention, when binarizing multi-tone density levels sampled on a pixel-by-pixel basis, the binarization error of the pixel of interest is stored in association with the pixel positions in the surroundings. The error storage means, the input level of the target pixel, the input correction means for temporarily storing the integrated error corresponding to the position of the target pixel in the error storage means in the addition register, and outputting the correction level;
Difference calculation means for obtaining differences in parallel in advance in two states of the binarization level, temporarily storing in each register and outputting difference level A and difference level B, the difference level A, difference level B, and previous pixel The binarization error temporarily stored during the processing is added to each to obtain the error A and the error B, the error A is compared with a predetermined threshold value, and the binarization level of the pixel of interest is determined. Binarization means for selecting the error A or the error B according to the binarization level, temporarily storing the new binarization error in the register, and setting it as the binarization error in the next pixel processing,
A distribution coefficient for distributing the binarization error to unprocessed pixels around the pixel of interest is arbitrarily initialized for each arbitrary sub-scanning line from a plurality of distribution coefficient sets at a predetermined change cycle. An error distribution value corresponding to an unprocessed pixel around the pixel of interest is calculated from the distribution coefficient generating means generated according to random number generation, the difference from the difference calculating means, and the plurality of distribution coefficients from the distribution coefficient generating means, and the error is calculated. An image signal processing device comprising error distribution / update means for adding the distribution value to the integration error of the corresponding pixel position in the error storage means and storing again as a new integrated pixel is attempted to achieve the above object. It is a thing.

作 用 本発明は上記構成により、2値化誤差を得る際予じめ2
値化レベルの2状態でそれぞれに誤差演算を行い、2値
化レベルの決定に応じ選択するとともに、注目画素の周
辺画素に対する2値化誤差の配分割合を、複数組の配分
係数セットの中から任意副走査ライン毎に任意値または
前ライン+nした値で初期設定された乱数発生に従って
1組を選択する配分係数発生手段の機能によって、2値
化誤差の配分量が注目画素と一定の相対的位置関係にあ
る画素に偏らないようにし、処理された出力画像にテク
スチャ模様の発生を抑制し、しかも高速な画素処理が出
来るようにしたものである。また、マキシマムレングス
・カウンタ回路などの乱数発生器は周期性を持ってお
り、主走査方向すなわちX方向の画素数がその周期性の
N倍の場合にも、出力画像にテクスチャが発生しないよ
うにしたものである。
Operation The present invention has the above-mentioned configuration so as to make a prediction when a binarization error is obtained.
The error calculation is performed in each of the two states of the binarization level, and the binarization error is selected according to the decision of the binarization level, and the distribution ratio of the binarization error to the peripheral pixels of the pixel of interest is selected from a plurality of distribution coefficient sets. By the function of the distribution coefficient generating means that selects one set according to the random number generation initialized by an arbitrary value or a value obtained by adding + n to the previous line for each arbitrary sub-scanning line, the distribution amount of the binarization error is constant relative to the pixel of interest. This is to prevent the pixels having a positional relationship from being biased, suppress the occurrence of a texture pattern in the processed output image, and enable high-speed pixel processing. Further, the random number generator such as the maximum length counter circuit has a periodicity, so that the texture is not generated in the output image even when the number of pixels in the main scanning direction, that is, the X direction is N times the periodicity. It was done.

実施例 第1図は本発明の一実施例における画像信号処理装置の
要部ブロック構成図である。
Embodiment FIG. 1 is a block diagram of the essential parts of an image signal processing apparatus in an embodiment of the present invention.

第1図において、原画像における注目画素の座標を(x,
y)とするとき、1は誤差記憶手段、2は誤差配分係数
マトリクスの示す注目画素の周辺の未処理画素領域、3
は座標(x+2,y)における集積誤差の読み出し位置で
ある。15は入力補正手段、18は差分演算手段、23は2値
化手段、11は誤差配分・更新手段、12は配分係数発生手
段であり、これらの構成はさらに以下で詳細に説明す
る。
In FIG. 1, the coordinates of the pixel of interest in the original image are (x,
y), 1 is the error storage means, 2 is the unprocessed pixel area around the pixel of interest indicated by the error distribution coefficient matrix, 3
Is the read position of the integration error at the coordinate (x + 2, y). Reference numeral 15 is an input correction means, 18 is a difference calculation means, 23 is a binarization means, 11 is an error distribution / update means, and 12 is a distribution coefficient generation means. These configurations will be described in further detail below.

入力補正手段15は、注目画素の座標を(x,y)としたと
き入力端子4から入力レベルIx+2,yと誤差記憶手段
1から集積誤差Sx+2,yとを加算し画素処理周囲に同
期した同期信号14でレジスタ17に一時記憶する。
The input correction means 15 adds the input level I x + 2, y from the input terminal 4 and the integrated error S x + 2, y from the error storage means 1 when the coordinates of the pixel of interest are (x, y), and synchronizes with the surroundings of pixel processing. The sync signal 14 is temporarily stored in the register 17.

差分演算手段18は、入力補正手段15から出力されたI′
x+1,yと出力レベルである0およびRの2値化レベル
との差分をそれぞれにとりレジスタ21とレジスタ22に一
時記憶し差分レベルAと差分レベルBを出力する。
The difference calculating means 18 outputs the I ′ output from the input correcting means 15.
Differences between x + 1 and y and the binarization levels of 0 and R which are output levels are respectively stored in the registers 21 and 22 and temporarily output to the difference levels A and B.

2値化手段23は、前記差分レベルAと差分レベルBとを
それぞれに誤差配分・更新手段11からの誤差配分値47と
加算し誤差Aと誤差Bを求める。誤差Aを予じめ定めら
れた閾値と比較し、2値化レベルPxyを得るとともに2
値化レベルに応じセレクタ27により誤差Aまたは誤差B
を選択し新たな2値化誤差としてレジスタ28に一時記憶
し2値化誤差Exyを出力する。
The binarizing means 23 adds the difference level A and the difference level B to the error distribution value 47 from the error distribution / update means 11 to obtain the error A and the error B. The error A is compared with a predetermined threshold value to obtain the binarization level Pxy and 2
The error A or the error B is selected by the selector 27 according to the digitization level
Is temporarily stored in the register 28 as a new binarization error and the binarization error Exy is output.

配分係数発生手段12は、注目画素周辺の未処理画素に対
する複数組の配分係数セットを予め用意し、同期信号入
力端子13よりX方向の画素処理周期に同期した同期信号
14を得て周辺画素領域2内の画素位置A〜Dに対する2
値化誤差Exyの配分係数KA〜KDを前記複数組の配分係数
セットより選択し、誤差配分・更新手段11へ出力する。
誤差配分・更新手段11は同期信号14に同期しながら、前
記配分係数KA〜KDとともに差分演算手段9からの注目画
素に対する2値化誤差Exyおよび誤差記憶手段1の周辺
画素領域2内の画素位置A、C、Dに対応する記憶装置
に記憶されている。それ以前の画素処理課程における集
積誤差S′、S′、S′を読み出し、新たな集積
誤差SA〜SBを第(3)式により求める。
The distribution coefficient generating means 12 prepares a plurality of distribution coefficient sets for unprocessed pixels around the target pixel in advance, and a sync signal synchronized with the pixel processing cycle in the X direction from the sync signal input terminal 13.
2 for pixel positions A to D in the peripheral pixel area 2 by obtaining 14
The distribution coefficients K A to K D of the binarization error Exy are selected from the plurality of distribution coefficient sets and output to the error distribution / updating means 11.
The error distribution / updating means 11 synchronizes with the synchronization signal 14 and, along with the distribution coefficients K A to K D , the binarization error Exy for the pixel of interest from the difference calculating means 9 and the peripheral pixel area 2 of the error storing means 1 It is stored in the storage device corresponding to the pixel positions A, C, and D. Integrated error S 'A, S' in the previous pixel processing program C, reads the S 'D, obtaining a new integrated error S A to S B by the equation (3).

さらに誤差配分・更新手段11は新たな集積誤差SA〜SD
誤差記憶手段1内の画素位置A〜Dに対応する記憶装置
に書込む更新処理を行う。
Further, the error distribution / updating means 11 carries out an updating process of writing new integrated errors S A to S D in the storage devices corresponding to the pixel positions A to D in the error storage means 1.

これら誤差配分・更新手段11と配分係数発生手段12のよ
り具体的回路を第2図に示す。同図において、配分係数
セットは2組とした場合について説明する。
A more specific circuit of the error distribution / update means 11 and the distribution coefficient generation means 12 is shown in FIG. In the same figure, the case where the number of distribution coefficient sets is two will be described.

配分係数発生手段12は複数組の配分係数セットK1A〜K1D
とK2A〜K2Dを予め格納するために記憶装置40と記憶装置
41を設け前記係数セツトを画素処理の開始に先だって収
納する。
The distribution coefficient generating means 12 is composed of a plurality of distribution coefficient sets K 1A to K 1D.
And a storage device 40 for storing K 2A to K 2D in advance.
41 is provided to store the coefficient set prior to the start of pixel processing.

初期値テーブル37は副走査ライン毎に乱数発生の開始点
を決める初期値を画素処理の開始に先だって格納し、ラ
イン同期信号入力端子35から与えられる副走査方向すな
わちY方向の同期信号であるライン同期信号36によって
初期値38が出力される。また初期値テーブルは、副走査
ライン毎に+nした初期値が格納されたRAMまたはROMの
ような記憶装置でも構成できるが、任意副走査ライン毎
に前ライン+nの初期値を設定する場合には計数カウン
タ等でも容易に構成できる。
The initial value table 37 stores an initial value for determining a starting point of random number generation for each sub-scanning line prior to the start of pixel processing, and a line which is a synchronizing signal in the sub-scanning direction, that is, the Y direction, given from the line synchronizing signal input terminal 35. An initial value 38 is output by the synchronization signal 36. The initial value table can also be configured by a storage device such as a RAM or a ROM that stores an initial value + n for each sub-scanning line, but when setting the initial value of the previous line + n for each arbitrary sub-scanning line, A counting counter or the like can be easily configured.

またランダム信号発生器39は初期値テーブル37より出力
された初期値38はライン同期信号36によって乱数発生の
開始点が設定され、同期信号入力端子13から与えられる
X方向の画素処理周期に対応した同期信号14の入力によ
りセレクト信号42を出力する。
The random signal generator 39 sets the starting point of random number generation for the initial value 38 output from the initial value table 37 by the line synchronization signal 36, and corresponds to the pixel processing cycle in the X direction given from the synchronization signal input terminal 13. When the synchronizing signal 14 is input, the select signal 42 is output.

ランダム信号発生器39はマクシムレングス・カウンタ回
路等を用いてセレクト信号42を発生し、2組の配分係数
セットを選択する。
The random signal generator 39 uses a Maxim length counter circuit or the like to generate a select signal 42 and selects two distribution coefficient sets.

誤差配分・更新手段11は同期信号14に同期しながら、配
分係数発生手段12から入力された配分係数KA〜KDと2値
化手段23から入力された2値化誤差Exyを乗算し誤差配
分値47〜50を得る。誤差配分値47は新たな2値化誤差を
求めるために2値化手段23へ出力される。画素位置Bに
対する集積誤差は注目画素3の処理において生ずるた
め、誤差配分値48を画素位置Bに対応する集積誤差
(SB)として内部レジスタ51(RB)に一時記憶する。誤
差配分値49と前画素処理において一時記憶している内部
レジスタ51(RB)のデータを加算し画素位置Cの集積誤
差(SC)として内部レジスタ52(RC)のデータとし一時
記憶する。誤差配分値50と前画素の処理において一時記
憶している内部レジスタ52(RC)のデータと加算し、誤
差記憶手段1の画素位置Dに対応する記憶装置に記憶さ
せる。このような誤差配分・更新手段11により、誤差記
憶手段1内の記憶装置へのアクセスは、画素位置(x+
2,y)に対応する読込みアクセスと画素位置Dに対応す
る書込みアクセスのみとなり容易に実現可能な構成とな
る。
The error distribution / updating means 11 multiplies the distribution coefficients K A to K D input from the distribution coefficient generating means 12 and the binarization error Exy input from the binarization means 23 while synchronizing with the synchronization signal 14, and the error Get a share of 47-50. The error distribution value 47 is output to the binarizing means 23 to obtain a new binarizing error. Since the integration error for the pixel position B occurs in the processing of the pixel of interest 3, the error distribution value 48 is temporarily stored in the internal register 51 (R B ) as the integration error (S B ) corresponding to the pixel position B. The error distribution value 49 and the data of the internal register 51 (R B ) temporarily stored in the previous pixel processing are added, and the data is temporarily stored as the data of the internal register 52 (RC) as the integration error (SC) of the pixel position C. The error distribution value 50 and the data of the internal register 52 (RC) temporarily stored in the processing of the previous pixel are added and stored in the storage device corresponding to the pixel position D of the error storage means 1. With such an error distribution / update means 11, access to the storage device in the error storage means 1 is performed at the pixel position (x +
2, y), and only the read access corresponding to the pixel position D and the write access corresponding to the pixel position D can be realized easily.

発明の効果 以上のように本発明では、2値化誤差を求める際予じめ
2通りの仮の2値化誤差を演算し2値化レベルが確定し
たときに2通りの仮の2値化誤差から選択することで多
段の演算回路構成が一段の演算回路構成となり高速処理
が可能となった。
As described above, according to the present invention, when the binarization error is obtained, two types of provisional binarization errors are calculated in advance, and when the binarization level is determined, two types of provisional binarization are performed. By selecting from the error, the multi-stage arithmetic circuit configuration becomes a single-stage arithmetic circuit configuration and high-speed processing becomes possible.

注目画素の周辺画素に対する2値化誤差の配分比率を一
定とせず、画素処理とともに複数組の配分係数セットの
中から選択して用いることにより、従来の誤差拡散法に
見られた偽画像(テクスチャ)を大幅に抑制することが
可能で、また、乱数発生の開始点を任意副走査ライン毎
に設定することにより、X方向の画素数に影響されるこ
となく偽画像(テクスチャ)を大幅に抑制することが可
能となった。
The distribution ratio of the binarization error to the peripheral pixels of the pixel of interest is not fixed, but is selected from a plurality of distribution coefficient sets together with the pixel processing to be used. ) Can be significantly suppressed, and by setting the starting point of random number generation for each arbitrary sub-scanning line, the false image (texture) can be significantly suppressed without being affected by the number of pixels in the X direction. It became possible to do.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の一実施例における画像信号処理装置の
要部ブロック構成図、第2図は第1図の要部である誤差
配分・更新手段と配分係数発生手段の詳細回路図、第3
図は従来の誤差拡散法を実現する要部ブロック構成図で
ある。 1……誤差記憶手段、11……誤差配分・更新手段、40〜
41……記憶装置、39……ランダム信号発生器、43〜46…
…セレクタ、51〜52……内部レジスタ、37……初期値テ
ーブル。
FIG. 1 is a block diagram of a main part of an image signal processing apparatus according to an embodiment of the present invention. FIG. 2 is a detailed circuit diagram of an error distribution / update means and a distribution coefficient generation means, which are the main parts of FIG. Three
The figure is a block diagram of a main part for realizing the conventional error diffusion method. 1 ... Error storage means, 11 ... Error distribution / update means, 40-
41 ... Memory device, 39 ... Random signal generator, 43-46 ...
… Selector, 51 to 52 …… Internal register, 37 …… Initial value table.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 黒沢 俊晴 神奈川県川崎市多摩区東三田3丁目10番1 号 松下技研株式会社内 (72)発明者 高橋 潔 神奈川県川崎市多摩区東三田3丁目10番1 号 松下技研株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiharu Kurosawa 3-10-10 Higashisanda, Tama-ku, Kawasaki City, Kanagawa Matsushita Giken Co., Ltd. (72) Kiyoshi Takahashi 3-chome, Higashisanda, Tama-ku, Kawasaki City, Kanagawa Prefecture No. 10 No. 1 Matsushita Giken Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】画素単位でサンプリングした多階調の濃度
レベルを2値化する際に、注目画素の2値化誤差をその
周辺の画素位置に対応させて記憶する誤差記憶手段と、
注目画素の入力レベルと前記誤差記憶手段内の注目画素
位置に対応した集積誤差を加算レジスタに一時記憶し、
補正レベルを出力する入力補正手段と、前記補正レベル
を2値化レベルの2状態で予らかじめそれぞれに差分を
求めそれぞれのレジスタに一時記憶し差分レベルAと差
分レベルBを出力する差分演算手段と、前記差分レベル
Aと差分レベルBと前面画素処理時に一時記憶しておい
た2値化誤差とをそれぞれに加算し誤差Aと誤差Bを求
め、誤差Aを予め定められた閾値と比較し注目画素の2
値化レベルを決定し、この2値化レベルにより誤差Aあ
るいは誤差Bを選択し新な2値化誤差を得るレジスタに
一時記憶して次の画素処理の際に2値化誤差とする2値
化手段と、前記2値化誤差を注目画素の周辺の未処理画
素に配分する配分係数を、予め定められた変更周期で、
複数組の配分係数セットの中から乱数発生に従って発生
させる配分係数発生手段と、前記配分係数発生手段から
の複数の配分係数から注目画素周辺の未処理画素に対応
する誤差配分値を算出し、前記誤差配分値を前記誤差記
憶手段内の対応する画素位置の集積誤差とを加算して再
び記憶させる誤差配分・更新手段とを具備する画像信号
処理装置。
1. An error storage means for storing a binarization error of a pixel of interest in association with a pixel position in the vicinity thereof when binarizing a multi-tone density level sampled in pixel units.
The input level of the pixel of interest and the integrated error corresponding to the position of the pixel of interest in the error storage means are temporarily stored in an addition register,
An input correction means for outputting a correction level and a difference operation for predicting the difference between the correction levels in two states of the binarization level and temporarily storing the difference in each register and outputting the difference level A and the difference level B. Means, the difference level A, the difference level B, and the binarization error temporarily stored at the time of the front pixel processing are added to obtain the error A and the error B, and the error A is compared with a predetermined threshold value. 2 of the attention pixel
A binary value that determines the binarization level, selects the error A or the error B according to this binarization level, temporarily stores it in a register that obtains a new binarization error, and uses it as the binarization error in the next pixel processing. And a distribution coefficient that distributes the binarization error to unprocessed pixels around the pixel of interest at a predetermined change cycle.
A distribution coefficient generating means for generating a random number from a plurality of distribution coefficient sets, and an error distribution value corresponding to an unprocessed pixel around the pixel of interest are calculated from the plurality of distribution coefficients from the distribution coefficient generating means, An image signal processing apparatus comprising: an error distribution / update means for adding an error distribution value to an integrated error of a corresponding pixel position in the error storage means and storing again.
JP61304249A 1986-12-19 1986-12-19 Image signal processor Expired - Fee Related JPH0666876B2 (en)

Priority Applications (10)

Application Number Priority Date Filing Date Title
JP61304249A JPH0666876B2 (en) 1986-12-19 1986-12-19 Image signal processor
DE3785558T DE3785558T3 (en) 1986-12-19 1987-12-18 Device for processing signals for displaying images with two levels.
EP92110355A EP0512578B1 (en) 1986-12-19 1987-12-18 Bi-level image display signal processing apparatus
EP92110032A EP0507354B1 (en) 1986-12-19 1987-12-18 Bi-level image display signal processing apparatus
DE3751916T DE3751916D1 (en) 1986-12-19 1987-12-18 Device for processing signals for displaying images with two levels
DE3751957T DE3751957T2 (en) 1986-12-19 1987-12-18 Device for processing signals for displaying images with two levels
EP92110386A EP0507356B1 (en) 1986-12-19 1987-12-18 Bi-level image display signal processing apparatus
EP87311205A EP0272147B2 (en) 1986-12-19 1987-12-18 Bi-level image display signal processing apparatus
DE3752022T DE3752022T2 (en) 1986-12-19 1987-12-18 Device for processing signals for displaying images with two levels
US07/136,486 US4891710A (en) 1986-12-19 1987-12-21 Bi-level image display signal processing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61304249A JPH0666876B2 (en) 1986-12-19 1986-12-19 Image signal processor

Publications (2)

Publication Number Publication Date
JPS63155954A JPS63155954A (en) 1988-06-29
JPH0666876B2 true JPH0666876B2 (en) 1994-08-24

Family

ID=17930782

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61304249A Expired - Fee Related JPH0666876B2 (en) 1986-12-19 1986-12-19 Image signal processor

Country Status (1)

Country Link
JP (1) JPH0666876B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2553799B2 (en) * 1992-02-14 1996-11-13 松下電送株式会社 Image processing device
JP3459890B2 (en) 1999-09-22 2003-10-27 Nec液晶テクノロジー株式会社 Initialization method of pseudo intermediate processing circuit

Also Published As

Publication number Publication date
JPS63155954A (en) 1988-06-29

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