JPH0793357B2 - Semiconductor integrated circuit - Google Patents

Description

The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit including a plurality of functional blocks.

[Conventional technology]

Recently, the systemization and scale-up of semiconductor integrated circuits are remarkable in the field of analog integrated circuits.
The mainstream method is to design the entire system in units of multiple functional blocks for standardization. Further, the occupied area of basic elements such as transistors and resistors is rapidly decreasing with the progress of process technology, and restrictions on the redundancy of circuits and layouts have been alleviated.
Therefore, in ASIC, it is more important to develop an LSI satisfying the circuit characteristics in a shorter delivery time than to reduce the chip area by optimizing the circuit and layout design.

[Problems to be solved by the invention]

In conventional analog LSIs, block standardization has been delayed, and L
The mainstream is to design and commercialize functional blocks according to the development of SI. Therefore, the verified functional blocks used in the digital LSI development system are not used, and therefore the circuit characteristics may not be satisfied at the time of product evaluation. Of course, in order to eliminate such problems, we are making bullet boards (BB) using transistors made in the same process as the product and confirming the characteristics, but recent transistors have become lower in current as speed increases. Since the load resistance is measured, a resistance whose load resistance is one digit higher is used. In such a breadboard (BB), because of the influence of the wiring capacity in it, the characteristics of the BB are significantly different from the actual chip operation. In addition, circuit simulation also verifies the analog operation using SPICE, but due to various restrictions, it is not possible to simulate all functional blocks.
Therefore, in the product evaluation, the offset of the functional block is large, the frequency characteristic of gain is different from the design value,
For a variety of reasons, it was necessary to repeat the redesign and reprototype, which had the drawback of increasing TAT.

It is an object of the present invention to provide a semiconductor integrated circuit that can adjust not only a defect in analog characteristics but also a deviation from a design value.

[Means for solving problems]

A semiconductor integrated circuit according to the present invention comprises a plurality of functional blocks formed on a semiconductor substrate and basic elements such as various transistors, resistors, capacitors, and the like. An analog master block connected to the functional block and formed on a part of the semiconductor substrate, a plurality of wirings and through holes for connecting the functional block and the analog master block diagram, and all the wirings including the plurality of wirings Of the wiring, a pad to which a wiring that requires external connection is connected is provided, and a circuit change is performed using the basic element of the analog master block and the wiring with respect to the functional block that is defective in evaluation. Is configured as follows.

That is, the present invention includes various analog circuit blocks (power supply, OPAMP, various AMP, comparator, VCO, A / D, D / A, special block such as killer circuit), various NPN transistors, PNP transistors, and P ⁺ diffusion resistors. , A P ^- diffusion resistor, a polysilicon resistor, an analog master block consisting of basic elements such as a MOS capacitor, multiple layers of aluminum wiring for connecting these blocks, a through hole and a pad, and the entire chip. The circuit block that became defective in the later evaluation is to change the circuit of the basic element of the analog master block by using Al wiring.

In short, the present invention integrates the master slice resistors and the like, which are conventionally incorporated in the functional block, into the analog master block.

〔Example〕

 Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view showing the outline of the entire chip for explaining the first embodiment of the present invention.

As shown in FIG. 1, the chip 1 has functional blocks 2a (A1 to A4), functional blocks 2b (B1 to B4), functional blocks 2c (C1 to C3), and functional blocks 2d (D1 to D3) on the same substrate. ， Function block 2e (E1 to E3), Function block 2f (F1 to F3)
It is composed of an analog master block (AMB) 3 for adjusting the characteristics of these functional blocks and a bonding pad 4 arranged on the inner peripheral portion of the chip 1. In this embodiment, the wiring is designed by using the Al two-layer process, and the wiring between the blocks is a horizontal wiring in the first Al wiring 5 (represented by a solid line) and a vertical wiring in the second Al wiring 6 (dotted line). Represented by
Are using. The first Al wiring 5 and the second Al wiring 6
Are electrically connected to each other through the through hole portion 7. Each of the functional blocks 2a to 2f is the first in the inter-block wiring area.
It is connected using the Al wiring 5 and the second Al wiring 6,
Signal processing is sequentially performed for each block. In addition, the analog master block 3 placed in the center is for various NPN and PNP
Transistor, resistance group in units of 1KΩ and 10KΩ, MOS
A capacitor, Schottky diode, etc. are built in for adjustment.

On the other hand, various evaluations are performed on the prototyped LSI after the design is completed, but during this evaluation, problems specific to analog circuits such as channel balance, crosstalk, S / N, offset, frequency characteristics, and electrostatic breakdown may occur. There is. As a conventional measure, a defective circuit block is first found, and then the circuit configuration of this circuit block is changed or the constants of transistors and resistors are changed. Normal,
The layout design of each block is designed at the minimum interval in accordance with the design standard, and the layout design must be restarted from the beginning when changes are made. Therefore,
Modification is a change from the embedded diffusion process and is required for trial manufacture
TAT costs as much as the first design sample. Also, since the layout is redone for all the processes, unexpected parasitic effects occur or design errors occur.

In this example, the elements necessary for circuit change and constant change are prepared in AMB, and the blocks that become defective in the design / sample evaluation are selected from the corresponding defective block to AMB.
The wiring is drawn out to improve the block only by the Al wiring process. In this embodiment, since the correction is made only on the Al wiring, not only the TAT can be greatly shortened as compared with the conventional one but also a design error can be prevented as in the gate array. As for the inter-block wiring to the AMB, in principle, the first Al wiring layer 5, the second Al wiring layer 6 and the through hole are provided between the block where the defect is found after the electrical characteristics of the chip are evaluated and the AMB. 7 is used for designing, but it is also possible to wire between each functional block AMB and the functional block AMB in the first designing stage without connecting to the element in the AMB. In this case, since the wiring for the correction is prepared in anticipation that the functional block having the malfunction and the AMB will be corrected immediately, the correction TAT can be performed earlier.

When the element size of the entire chip increases, the AWB placed in the center of the chip from all the defective functional blocks
It becomes difficult to connect the blocks to the block 3. In this case, if the three-layer Al wiring process is adopted and the three-layer wiring is used as the inter-block wiring from each block to the AMB3, the target wiring can be easily performed.

Furthermore, in any case, such as when the constant has deviated from the optimum value due to the variation in the characteristics depending on the user or due to the dispersion of the process in mass production, the element built in the AMB in this embodiment is It is easy to correct the optimum design again by using.

FIG. 2 is a schematic plan view of the entire chip for explaining the second embodiment of the present invention.

As shown in FIG. 2, this embodiment has functional blocks 2a to 2e and analog master blocks 3a to 3d in a chip 1, and the analog master blocks 3a to 3d (AMB1 to AMB7) are functional blocks in principle. It is arranged next to. On the other hand, when a functional block that is stable in mass production such as the functional block 2e (E1 block, E2 block) is used, the AMB does not need to be laterally arranged because no correction is necessary. As described above, in this embodiment, as a general rule, the analog master block is arranged immediately next to each functional block, and therefore the defective functional block is connected to the necessary element in the AMB without using the inter-block arrangement. This makes it easy to make corrections. Further, in this case, since the wiring length can be shortened, it is possible to improve without impairing the frequency characteristic. Further, as shown in AMB7, it is also possible to enter the common AMB from the left and right functional blocks 2d (D1, D2) to recreate the circuit and constants. Mentioned above
The size of the AMB is determined from the number of elements in the functional block and the stability of the characteristics. The smaller the number of elements in the functional block and the higher the stability, the smaller the number of elements in the AMB. The other numbers in FIG. 2 are the same as the numbers shown in FIG.
The functional description is omitted.

〔The invention's effect〕

As described above, in the development of an analog LSI or a mixed analog / digital LSI, the semiconductor integrated circuit of the present invention has an analog master block (AMB) prepared as a group of single devices at the initial top design stage and sufficiently verified. In the case where the functional block that has not been formed has a defective electrical characteristic or deviates from the design center, it is possible to change the functional block very easily by changing the Al wiring process. Therefore, there is an effect that the TAT of the improved LSI, that is, the TAT until mass production can be significantly improved.

Also, by providing redundancy in a part of the chip, the size of the chip naturally increases, but recent device miniaturization is rapidly progressing, and the redundancy of AMB is costly in terms of area as a whole chip. Can also be fully absorbed. In other words, the chip area is reduced because the AMBs are arranged in the center of the entire chip or corresponding to a plurality of function blocks without preparing a large number of elements for condition adjustment in the function blocks. It is possible. Therefore, in the semiconductor integrated circuit of the present invention, the defective functional block can be corrected and the constant can be changed to the optimum value in the Al wiring step, so that the correction is easy and the design error is small.

[Brief description of drawings]

FIG. 1 is a plan view showing the outline of the entire chip for explaining the first embodiment of the present invention, and FIG. 2 is a plan view showing the outline of the entire chip for explaining the second embodiment of the present invention. It is a figure. 1 ... Chip, 2a-2f ... Function block, 3,3a-3d ...
Analog master block (AMB), 4 ... Pad, 5
...... First aluminum wiring (solid line), 6 ... Second aluminum wiring (dotted line), 7 ... through hole.

Claims (2)

[Claims] 1. A plurality of functional blocks formed on a semiconductor substrate and basic elements such as various transistors, resistors, capacitors, etc., and between the functional blocks or the functional blocks in order to adjust mutual characteristics of the functional blocks. An analog master block formed on a part of the semiconductor substrate by being connected to a plurality of wirings and through holes for connecting the functional block and the analog master block, and all wirings including the plurality of wirings. It has a pad to which a wiring that requires external connection is connected, and for the functional block that becomes defective in evaluation, the circuit is changed using the basic element and the wiring of the analog master block. Semiconductor integrated circuit. 2. The analog master block according to claim 1, further comprising a first analog master block adjacent to the functional block and a second analog master block arranged between the functional blocks. Semiconductor integrated circuit.