JPH0793319B2 - Method for manufacturing field effect transistor - Google Patents
Method for manufacturing field effect transistorInfo
- Publication number
- JPH0793319B2 JPH0793319B2 JP59215135A JP21513584A JPH0793319B2 JP H0793319 B2 JPH0793319 B2 JP H0793319B2 JP 59215135 A JP59215135 A JP 59215135A JP 21513584 A JP21513584 A JP 21513584A JP H0793319 B2 JPH0793319 B2 JP H0793319B2
- Authority
- JP
- Japan
- Prior art keywords
- organic material
- film
- resist
- field effect
- effect transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 230000005669 field effect Effects 0.000 title claims description 5
- 238000000034 method Methods 0.000 title description 5
- 239000011368 organic material Substances 0.000 claims description 18
- 229910010272 inorganic material Inorganic materials 0.000 claims description 11
- 239000011147 inorganic material Substances 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229920003986 novolac Polymers 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明はマイクロ波帯等で用いられる電界効果トランジ
スタ（FET）の製造方法に関するものである。The present invention relates to a method for manufacturing a field effect transistor (FET) used in a microwave band or the like.
（従来例の構成とその問題点） GaAsFETの高周波、高速性能の向上にはソース抵抗の低
減がきわめて重要であり、このためにこれまでゲートを
セルフアラインで形成する様々な方法が提案されてき
た。(Structure of conventional example and its problems) It is very important to reduce the source resistance in order to improve the high frequency and high speed performance of GaAs FET. For this reason, various methods of forming the gate by self-alignment have been proposed so far. ..
以下、図面を参照しながら従来のゲートをセルフアライ
ンで形成する製造方法の一例について説明する。Hereinafter, an example of a conventional manufacturing method for forming a gate by self-alignment will be described with reference to the drawings.
第２図は従来のゲートをセルフアラインで形成するため
の製造工程の一例を示すものである。半導体基板１上の
ｎ層２の表面のゲート電極を形成すべき場所にSiO2など
の無機物の膜、いわゆるダミーゲート３を形成した後、
ダミーゲート３をマスクとしてイオン注入してn+層を形
成する。その上に有機物の膜としてレジスト５を塗布す
る（第２図（ａ））。このときダミーゲート３の上部の
レジスト５は若干薄くなる。FIG. 2 shows an example of a manufacturing process for forming a conventional gate by self-alignment. After forming a film of an inorganic material such as SiO 2 or so-called dummy gate 3 on the surface of the n-layer 2 on the semiconductor substrate 1 at the place where the gate electrode is to be formed,
Ions are implanted using the dummy gate 3 as a mask to form an n + layer. A resist 5 is applied as an organic material film thereon (FIG. 2 (a)). At this time, the resist 5 on the dummy gate 3 is slightly thinned.
次にダミーゲート３の上部が露出するようにO2を用いた
プラズマエッチによりレジスト５をエッチングする（第
２図（ｂ））。Next, the resist 5 is etched by plasma etching using O 2 so that the upper part of the dummy gate 3 is exposed (FIG. 2 (b)).
次いで、SiO2で形成したダミーゲート３をウェットエッ
チし、Alなどの金属６を蒸着する（第２図（ｃ））。そ
してレジスト５を除去するとレジスト５の上の金属６が
リフトオフされ、ゲート電極７が得られる（第２図
（ｄ））。Next, the dummy gate 3 made of SiO 2 is wet-etched, and a metal 6 such as Al is deposited (FIG. 2 (c)). Then, when the resist 5 is removed, the metal 6 on the resist 5 is lifted off and the gate electrode 7 is obtained (FIG. 2 (d)).
しかしながら、上記のような方法ではダミーゲート３の
上部のレジスト５の厚さと半導体上のレジストの厚さと
の差が小さいため、ダミーゲート３の上部を露出するよ
うにエッチングするとリフトオフ用レジストスペーサー
が薄くなり金属６を厚く蒸着することができず、ゲート
抵抗が増大するという欠点を有していた。However, in the above method, since the difference between the thickness of the resist 5 on the dummy gate 3 and the thickness of the resist on the semiconductor is small, if the upper part of the dummy gate 3 is etched to expose the lift-off resist spacer. However, the metal 6 cannot be vapor-deposited thickly, and the gate resistance increases.
（発明の目的） 本発明は上記欠点をなくすためになされたものであり、
ゲート電極を厚く形成することのできるFETの製造方法
を提供するものである。(Object of the Invention) The present invention has been made to eliminate the above-mentioned drawbacks,
An FET manufacturing method capable of forming a thick gate electrode.
（発明の構成） この目的を達成するために本発明のFETの製造方法は、
ゲート電極を形成すべき場所に無機物の膜が形成された
半導体基板上に、第１の有機物を塗布したのち200℃以
上の熱処理を行ない、次いで第１の有機物を薄くして前
記無機物の膜の上部を露出せしめる工程と、第２の有機
物を塗布したのち第２の有機物を薄くして無機物の膜の
上部を露出せしめる工程と、前記無機物の膜をエッチン
グ除去し、ゲート金属を蒸着したのち、前記第２の有機
物の上のゲート電極を第２の有機物とともに除去する工
程とを備えて構成されている。(Structure of the Invention) In order to achieve this object, the method of manufacturing the FET of the present invention is
After coating the first organic material on the semiconductor substrate on which the inorganic material film is formed at the place where the gate electrode is to be formed, heat treatment is performed at 200 ° C. or higher, and then the first organic material is thinned to remove the inorganic material film. Exposing the top, exposing the top of the inorganic film by thinning the second organic after applying the second organic, and etching away the inorganic film and depositing the gate metal, And a step of removing the gate electrode on the second organic material together with the second organic material.
（実施例の説明） 以下本発明の一実施例について図面を参照しながら説明
する。(Description of Embodiments) One embodiment of the present invention will be described below with reference to the drawings.
第１図は本発明の電界効果トランジスタの製造方法によ
る製造工程を示すものである。FIG. 1 shows a manufacturing process according to the method for manufacturing a field effect transistor of the present invention.
半導体基板11上のｎ層12の表面のゲート電極を形成すべ
き場所にSiO2などの無機物の膜、いわゆるダミーゲート
13を形成した後、ダミーゲート13をマスクとしてイオン
注入してn+層14を形成する。その上に有機物の膜として
第１のレジスト15を塗布する（第１図（ａ））。次に20
0℃以上で熱処理して第１のレジスト15を平坦化し、ダ
ミーゲート13の上部が露出するようにO2を用いたプラズ
マエッチにより第１のレジスト15をエッチングする（第
１図（ｂ））。A film of an inorganic material such as SiO 2 , a so-called dummy gate, is formed on the surface of the n layer 12 on the semiconductor substrate 11 at the place where the gate electrode is to be formed.
After forming 13, the ion implantation is performed using the dummy gate 13 as a mask to form the n + layer 14. A first resist 15 is applied thereon as an organic film (FIG. 1 (a)). Then 20
The first resist 15 is planarized by heat treatment at 0 ° C. or higher, and the first resist 15 is etched by plasma etching using O 2 so that the upper part of the dummy gate 13 is exposed (FIG. 1 (b)). .
このとき熱処理温度が高い程平坦化が充分に行なわれ、
例えばノボラック系の樹脂を用いたレジストでは300℃
が最適である。At this time, the higher the heat treatment temperature is, the more the flattening is performed,
For example, the resist using novolac resin is 300 ℃
Is the best.
次いでその上に第２の有機物の膜として第２のレジスト
16を形成し、ダミーゲート13の上部が露出するようにO2
を用いたプラズマエッチにより第２のレジスト16をエッ
チングする（第１図（ｃ））。Then, a second resist is formed thereon as a second organic film.
16 is formed and O 2 is exposed so that the upper part of the dummy gate 13 is exposed.
The second resist 16 is etched by plasma etching using (FIG. 1 (c)).
その後、SiO2で形成したダミーゲート13をウェットエッ
チし、Alなどの金属17を蒸着する（第１図（ｄ））。こ
の時、金属17は第１の有機物の層があるため厚く蒸着す
ることができる。そしてレジスト15,16を除去すると第
１のレジスト15の上の金属17がリフトオフされ、ゲート
電極18が得られる（第１図（ｅ））。After that, the dummy gate 13 made of SiO 2 is wet-etched, and a metal 17 such as Al is deposited (FIG. 1 (d)). At this time, the metal 17 can be deposited thick because of the first organic material layer. Then, when the resists 15 and 16 are removed, the metal 17 on the first resist 15 is lifted off and the gate electrode 18 is obtained (FIG. 1 (e)).
（発明の効果） 以上のように本発明は半導体基板上に第１の有機物を塗
布したのち200℃以上の熱処理を行い、次いで第１の有
機物を薄くして無機物の膜の上部を露出せしめる工程
と、第２の有機物を塗布したのち第２の有機物を薄くし
て無機物の膜の上部を露出せしめる工程と、無機物の膜
をエッチング除去することによりゲート電極を厚く形成
でき、その実用的効果は大なるものがある。(Effect of the invention) As described above, according to the present invention, a step of applying a first organic material on a semiconductor substrate and then performing a heat treatment at 200 ° C. or higher, and then thinning the first organic material to expose the upper part of the inorganic material film And a step of applying the second organic material and then thinning the second organic material to expose the upper portion of the inorganic material film, and the gate electrode can be formed thick by etching away the inorganic material film. There is a great one.
第１図（ａ）〜（ｅ）は本発明の製造工程図、第２図
（ａ）〜（ｄ）は従来の製造工程図である。 1,11……半導体基板、2,21……ｎ層、3,13……ダミーゲ
ート、4,14……n+層、５……レジスト、6,17……蒸着金
属、7,18……ゲート電極、15……第１のレジスト、16…
…第２のレジスト。1 (a) to 1 (e) are manufacturing process diagrams of the present invention, and FIGS. 2 (a) to 2 (d) are conventional manufacturing process diagrams. 1,11 …… Semiconductor substrate, 2,21 …… n layer, 3,13 …… Dummy gate, 4,14 …… n + layer, 5 …… Resist, 6,17 …… Evaporated metal, 7,18… ... Gate electrode, 15 ... First resist, 16 ...
… Second resist.
Claims (2)
が形成された半導体基板上に、第１の有機物を塗布する
工程と、 前記第１の有機物を薄くして前記無機物の膜の上部を露
出せしめる工程と、 前記第１の有機物及び前記無機物の膜上に第２の有機物
を塗布する工程と、 前記第２の有機物を薄くして前記無機物の膜の上部を露
出せしめる工程と、 前記無機物の膜を除去する工程と、 前記ゲート電極となる金属膜を全面に蒸着する工程と、 前記第２の有機物上の前記金属膜を前記第２の有機物と
ともに除去する工程と を備えたことを特徴とする電界効果トランジスタの製造
方法。1. A step of applying a first organic material on a semiconductor substrate on which an inorganic material film is formed at a location where a gate electrode is to be formed; and a step of thinning the first organic material to form an upper portion of the inorganic material film. Exposing the first organic material and the inorganic material film with a second organic material, and thinning the second organic material to expose the upper part of the inorganic material film, A step of removing the inorganic film, a step of depositing a metal film to be the gate electrode on the entire surface, and a step of removing the metal film on the second organic material together with the second organic material. A method of manufacturing a characteristic field effect transistor.
熱処理を行うことを特徴とする特許請求の範囲第１項記
載の電界効果トランジスタの製造方法。2. The method for producing a field effect transistor according to claim 1, wherein a heat treatment at 200 ° C. or higher is performed after the first organic material is applied.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59215135A JPH0793319B2 (en) | 1984-10-16 | 1984-10-16 | Method for manufacturing field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59215135A JPH0793319B2 (en) | 1984-10-16 | 1984-10-16 | Method for manufacturing field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6194374A JPS6194374A (en) | 1986-05-13 |
| JPH0793319B2 true JPH0793319B2 (en) | 1995-10-09 |
Family
ID=16667281
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59215135A Expired - Lifetime JPH0793319B2 (en) | 1984-10-16 | 1984-10-16 | Method for manufacturing field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0793319B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59229876A (en) * | 1983-06-13 | 1984-12-24 | Toshiba Corp | Manufacture of schottky gate type field effect transistor |
-
1984
- 1984-10-16 JP JP59215135A patent/JPH0793319B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6194374A (en) | 1986-05-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS5950567A (en) | Manufacture of field effect transistor | |
| US4377899A (en) | Method of manufacturing Schottky field-effect transistors utilizing shadow masking | |
| JPS59229876A (en) | Manufacture of schottky gate type field effect transistor | |
| JPS6032364A (en) | Manufacture of semiconductor device | |
| US3679492A (en) | Process for making mosfet's | |
| JPS6151923A (en) | Method of superposing two positive photorewist layer | |
| JPS6351550B2 (en) | ||
| JPH0793319B2 (en) | Method for manufacturing field effect transistor | |
| JPH022175A (en) | Manufacture of thin film transistor | |
| JP2714026B2 (en) | Method for forming electrode for semiconductor device | |
| JPS62211957A (en) | Manufacture of field-effect transistor | |
| JPS61240684A (en) | Schottky-type field effect transistor and manufacture thereof | |
| JPH0793318B2 (en) | Method for manufacturing semiconductor device | |
| JPH0684950A (en) | Manufacture of field effect transistor | |
| JPH03289142A (en) | Manufacture of compound semiconductor device | |
| JPS6390171A (en) | Manufacture of field effect transistor | |
| JPS61280673A (en) | Manufacture of compound semiconductor device | |
| JPH04233240A (en) | Method for manufacture of metallized part on semiconductor material | |
| JPH0629322A (en) | Formation of gate electrode of field-effect transistor | |
| JPH02165639A (en) | Manufacture of semiconductor element | |
| JPS63308958A (en) | Manufacture of semiconductor device | |
| JPH07120673B2 (en) | Method of manufacturing Schottky gate field effect transistor | |
| JPH03133144A (en) | Electrode formation of semiconductor device | |
| JPH04346442A (en) | Manufacture of field-effect transistor | |
| JPH0410629A (en) | Manufacture of semiconductor device |