JPH0786540A - Laminated soi and its manufacture - Google Patents

Laminated soi and its manufacture

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Publication number
JPH0786540A
JPH0786540A JP25015593A JP25015593A JPH0786540A JP H0786540 A JPH0786540 A JP H0786540A JP 25015593 A JP25015593 A JP 25015593A JP 25015593 A JP25015593 A JP 25015593A JP H0786540 A JPH0786540 A JP H0786540A
Authority
JP
Japan
Prior art keywords
wafer
epitaxial layer
laser
density
heat treatment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP25015593A
Other languages
Japanese (ja)
Other versions
JP3260516B2 (en
Inventor
Hiroaki Yamamoto
博昭 山本
Kuniyuki Uemura
訓之 植村
Mitsuo Kono
光雄 河野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumco Techxiv Corp
Original Assignee
Komatsu Electronic Metals Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Komatsu Electronic Metals Co Ltd filed Critical Komatsu Electronic Metals Co Ltd
Priority to JP25015593A priority Critical patent/JP3260516B2/en
Publication of JPH0786540A publication Critical patent/JPH0786540A/en
Application granted granted Critical
Publication of JP3260516B2 publication Critical patent/JP3260516B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)

Abstract

PURPOSE:To provide a laminated SOI wafer in which an oxide film has a sufficiently high withstand voltage when devices are incorporated in it and which facilitates the improvement of the yield of the devices and its manufacturing method. CONSTITUTION:An epitaxial layer 7 whose laser scattering element density is not larger than 5X10<5>/cm<3> is made to grow on a first wafer 6 and an insulating layer 8 is formed at least on one of the first wafer 6 and a second wafer 9. Then the first wafer 6 and the second wafer 9 are bonded to each other with the epitaxial layer 7 and the insulating layer 8 therebetween. After that, whole of the first wafer 6 and a part of the epitaxial layer 7 are removed to form a semiconductor wafer 5.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は貼合せSOI(Silico
n On Insulator)とその製造方法に関し、特に貼合せS
OIの酸化膜耐圧の改良に関する。
This invention relates to a bonded SOI (Silico
n On Insulator) and its manufacturing method, especially bonding S
The present invention relates to improvement of breakdown voltage of oxide film of OI.

【0002】[0002]

【従来の技術】貼合せSOIは従来より図9に示すよう
に、例えば第1のウェハ(活性ウェハ)16に1μm程
度の酸化膜(SiO2)18を形成し、この酸化膜18
を形成した第1のウェハ(活性ウェハ)16を第2のウ
ェハ(基板ウェハ)19上に重ね合わせ、約1100℃
の熱処理を施して両ウェハ16,19を接着し、第1の
ウェハ(活性ウェハ)16の接着側と反対側の面を所望
の厚さまで研磨などによって除去して、貼合せSOI1
5に形成していた。除去して残る第1のウェハ(活性ウ
ェハ)16の厚さ、すなわち活性層16aの厚さは、バ
イポーラ素子に適用するときには1〜2μm程度であ
る。
2. Description of the Related Art Conventionally, as shown in FIG. 9, a bonded SOI has an oxide film (SiO 2 ) 18 of about 1 μm formed on a first wafer (active wafer) 16 and the oxide film 18 is formed.
The first wafer (active wafer) 16 on which is formed is superposed on the second wafer (substrate wafer) 19, and the temperature is about 1100 ° C.
Heat treatment is performed to bond the two wafers 16 and 19 together, and the surface of the first wafer (active wafer) 16 opposite to the adhesion side is removed by polishing or the like to a desired thickness, and the bonded SOI1
5 was formed. The thickness of the first wafer (active wafer) 16 remaining after removal, that is, the thickness of the active layer 16a is about 1 to 2 μm when applied to a bipolar device.

【0003】[0003]

【発明が解決しようとする課題】上記貼合せSOI15
の表層には各種のデバイスが組み込まれるが、各デバイ
スが電気的に良好に作動するためには、貼合せSOIの
酸化膜耐圧の値が基準値を越えている必要がある。しか
るに従来よりデバイスの酸化膜耐圧に影響を及ぼす因子
については必ずしも十分に解明されておらず、この結果
組み込んだデバイスの酸化膜耐圧が基準値に達していな
いために不良品とされる貼合せSOIが少なからず存在
し、デバイスの歩留りを悪化させていた。本発明はデバ
イスを組み込んだときの酸化膜耐圧が十分に高く、した
がってデバイスの歩留りを向上することができる貼合せ
SOIとその製造方法を提供することを目的とする。
[Problems to be Solved by the Invention] The above bonded SOI15
Various devices are incorporated in the surface layer of 1., but in order for each device to operate favorably electrically, the value of the oxide film breakdown voltage of the bonded SOI must exceed the reference value. However, the factors affecting the oxide film breakdown voltage of the device have not been sufficiently clarified so far, and as a result, the bonded SOI that is regarded as a defective product because the oxide film breakdown voltage of the incorporated device has not reached the reference value. Existed, and the device yield was deteriorated. It is an object of the present invention to provide a bonded SOI and a method for manufacturing the same, which has a sufficiently high breakdown voltage of an oxide film when the device is incorporated therein and can improve the yield of the device.

【0004】[0004]

【課題を解決するための手段】本発明者は上記目的を達
成するために研究を重ね、半導体ウェハにレーザーを照
射したときの散乱光に着目し、この散乱光を生じさせる
レーザー散乱体が半導体ウェハの表層部に多く存在する
と、酸化膜耐圧が劣化することを見出した。また半導体
ウェハの基板上にエピタキシャル層を成長させたエピタ
キシャルウェハについて上記レーザー散乱体の密度を測
定したところ、レーザー散乱体の密度はエピタキシャル
層の表面側では0となっているものの、基板との界面側
では基板のレーザー散乱体密度を引き継いで成長するこ
とを見出し、こうして本発明を完成するに至った。
Means for Solving the Problems The present inventor has conducted extensive research in order to achieve the above object, paying attention to scattered light when a semiconductor wafer is irradiated with a laser, and a laser scatterer which causes this scattered light is a semiconductor. It has been found that the oxide film withstand voltage deteriorates if it is present in a large amount in the surface layer of the wafer. Further, when the density of the laser scatterer was measured for an epitaxial wafer in which an epitaxial layer was grown on a substrate of a semiconductor wafer, the density of the laser scatterer was 0 on the surface side of the epitaxial layer, but the interface with the substrate. On the other hand, they have found that they grow by inheriting the laser scatterer density of the substrate, and thus completed the present invention.

【0005】すなわち本発明は、基板上に、絶縁層を介
して、レーザー散乱体密度が5×105個/cm3以下で
あるエピタキシャル層が貼り合わせられた貼合せSOI
である。本発明はまた、第1のウェハ上にエピタキシャ
ル層を成長させ、この第1のウェハと第2のウェハとの
少なくともいずれか一方に絶縁層を形成し、エピタキシ
ャル層側を接着面として第1のウェハを第2のウェハ上
に重ね合わせて両ウェハを接着し、第1のウェハの全部
とエピタキシャル層の一部を除去して半導体ウェハに形
成する貼合せSOIの製造方法である。本発明はまた、
第1のウェハを浮遊帯域溶融法によって形成し、この第
1のウェハ上にエピタキシャル層を成長させ、この第1
のウェハと第2のウェハとの少なくともいずれか一方に
絶縁層を形成し、エピタキシャル層側を接着面として第
1のウェハを第2のウェハ上に重ね合わせて両ウェハを
接着し、少なくとも第1のウェハの全部を除去して半導
体ウェハに形成する貼合せSOIの製造方法である。そ
の際、前記浮遊帯域溶融法に代えて、第1のウェハを、
引上げ速度が0.6mm/min以下のチョクラルスキ
ー法によって形成することができ、また、第1のウェハ
を、チョクラルスキー法によって製造した後に、133
0〜1400℃、0.5Hr以上の熱処理を施して形成
することもできる。熱処理については、H2雰囲気にお
いて1180℃以上、30min以上の熱処理を施すこ
ともできる。
That is, the present invention is a bonded SOI in which an epitaxial layer having a laser scatterer density of 5 × 10 5 pieces / cm 3 or less is bonded on a substrate through an insulating layer.
Is. According to the present invention, an epitaxial layer is grown on a first wafer, an insulating layer is formed on at least one of the first wafer and the second wafer, and the first epitaxial layer side is used as a bonding surface. This is a method of manufacturing a bonded SOI in which a wafer is overlaid on a second wafer, the two wafers are bonded to each other, and the entire first wafer and part of the epitaxial layer are removed to form a semiconductor wafer. The present invention also provides
A first wafer is formed by the floating zone melting method, and an epitaxial layer is grown on the first wafer.
An insulating layer is formed on at least one of the second wafer and the second wafer, and the first wafer is superposed on the second wafer with the epitaxial layer side as a bonding surface to bond the two wafers together. Is a method for manufacturing a bonded SOI in which the entire wafer is removed to form a semiconductor wafer. At that time, instead of the floating zone melting method, the first wafer was
It can be formed by the Czochralski method with a pulling speed of 0.6 mm / min or less, and after the first wafer is manufactured by the Czochralski method, 133
It can also be formed by performing heat treatment at 0 to 1400 ° C. for 0.5 hour or more. Regarding the heat treatment, it is also possible to perform heat treatment at 1180 ° C. or higher for 30 min or longer in an H 2 atmosphere.

【0006】[0006]

【実施例】以下に本発明の実施例を説明する。引上げ法
すなわちチョクラルスキー法によって単結晶シリコンイ
ンゴットを製造し、これにスライス・ラップ・面取り・
化学研磨の各工程を施してシリコンウェハの試料とし
た。試料の諸元は、直径6インチ、結晶軸<100>、
P型、ボロンドープ、抵抗率10〜20Ωcm、酸素濃
度12〜15×1017atoms/cm3(1979年
版アニュアル ブックオブ エーエスティエム スタン
ダーズ[以下の計測値は、この標準に従う]表示)であ
る。この試料についてレーザー散乱体の密度を測定し、
また実際にMOSキャパシターを作成して酸化膜耐圧を
測定した。図1は、上記試料のレーザー散乱体密度を測
定するための装置を示している。シリコンウェハ1の表
面に向けてレーザー発射装置2より波長1.3μmのレ
ーザー光が垂直に照射され、シリコンウェハの表面又は
内部にこのビームをフォーカスして、ウェハの表面又は
内部の任意に定めた複数のポイントを、ウェハがスライ
ドすることで走査する。ビームが欠陥に当たるとわずか
な位相のずれを生じるが、このずれを検出することで欠
陥を検出する。
EXAMPLES Examples of the present invention will be described below. A single crystal silicon ingot is manufactured by the pulling method, that is, the Czochralski method, and slice, lap, chamfer,
Each step of chemical polishing was performed to obtain a silicon wafer sample. The specifications of the sample are as follows: diameter 6 inches, crystal axis <100>,
P-type, boron-doped, resistivity 10 to 20 Ωcm, oxygen concentration 12 to 15 × 10 17 atoms / cm 3 (1979 edition Annual Book of ASTM Standards [the following measured values comply with this standard] display). Measure the density of the laser scatterer for this sample,
In addition, a MOS capacitor was actually created and the oxide film breakdown voltage was measured. FIG. 1 shows an apparatus for measuring the laser scatterer density of the above sample. A laser beam having a wavelength of 1.3 μm is vertically emitted from the laser emitting device 2 toward the surface of the silicon wafer 1, and the beam is focused on the surface or inside of the silicon wafer to arbitrarily determine the surface or inside of the wafer. A plurality of points are scanned by sliding the wafer. When the beam hits the defect, a slight phase shift occurs, and the defect is detected by detecting this shift.

【0007】図2は、シリコンウェハ1の表面近傍(0
〜3μm)でのレーザー散乱体の密度と、酸化膜耐圧が
3MV/cm以上、8MV/cm以下のBモード不良品
率との関係を示す。同図より明らかなように、レーザー
散乱体密度とBモード不良品率との間には著しい相関関
係があり、すなわちレーザー散乱体密度が増加するとB
モード不良品率が増加することが良く理解される。また
図3はレーザー散乱体の密度と酸化膜耐圧が8MV/c
m以上のCモード良品率との関係を示し、同図より明ら
かなように、レーザー散乱体密度が増加するとCモード
良品率が減少することが理解される。具体的な数値とし
ては、一般的に酸化膜耐圧のCモード良品率としては9
5%以上が要求されるから、図3よりレーザー散乱体密
度としては約5×105個/cm3以下である必要がある
ことが解る。これは貼合せSOIについても当てはまる
から、結局酸化膜耐圧が十分に高い貼合せSOIとして
は、その活性層のレーザー散乱体密度が5×105個/
cm3以下である必要があることが解る。発明者が調べ
た範囲では、活性層のレーザー散乱体密度が5×105
個/cm3以下である貼合せSOIは、従来存在しなか
った。
FIG. 2 shows the vicinity of the surface (0
Shows the relationship between the density of the laser scatterer at ˜3 μm) and the B-mode defective product rate when the oxide film withstand voltage is 3 MV / cm or more and 8 MV / cm or less. As is clear from the figure, there is a significant correlation between the laser scatterer density and the B-mode defective product rate, that is, when the laser scatterer density increases, B
It is well understood that the mode defective rate increases. Further, FIG. 3 shows that the density of the laser scatterer and the breakdown voltage of the oxide film are 8 MV / c.
The relationship with the C-mode non-defective rate of m or more is shown, and as is clear from the figure, it is understood that the C-mode non-defective rate decreases as the laser scatterer density increases. As a concrete numerical value, in general, the C-mode non-defective rate of the oxide film withstand voltage is 9
Since 5% or more is required, it is understood from FIG. 3 that the laser scatterer density needs to be about 5 × 10 5 pieces / cm 3 or less. Since this also applies to the bonded SOI, as a bonded SOI having a sufficiently high oxide film withstand voltage, the laser scatterer density of the active layer is 5 × 10 5 pieces /
It turns out that it needs to be less than or equal to cm 3 . In the range examined by the inventors, the laser scatterer density of the active layer is 5 × 10 5
The pasted SOI having the number of pieces / cm 3 or less did not exist conventionally.

【0008】次に図4は、チョクラルスキー法(CZ
法)によって製造したシリコンウェハの基板上に厚さ1
0μm、20μm、30μm、及び60μmのエピタキ
シャル層(Epi)を積層したエピタキシャルウェハ
と、浮遊帯域溶融法(FZ法)によって製造したシリコ
ンウェハの基板上に厚さ10μmのエピタキシャル層を
積層したエピタキシャルウェハについて、深さ方向のレ
ーザー散乱体密度を測定した結果を示す。先ずチョクラ
ルスキー法によって製造したシリコンウェハの基板上に
エピタキシャル層を積層したエピタキシャルウェハで
は、エピタキシャル層の表面側ではレーザー散乱体密度
は0となっているものの、基板との界面側では、レーザ
ー散乱体密度は基板のレーザー散乱体密度を引き継いで
成長している。すなわちこの実施例では、基板のレーザ
ー散乱体密度はほぼ1×106個/cm3であり、エピタ
キシャル層の基板側の遷移域において、レーザー散乱体
密度は1×106個/cm3から5×105個/cm3に漸
減し、更に0にまで漸減している。図5はこの結果を別
の視点から表わしたものであり、レーザー散乱体密度が
0の範囲、及び5×105個/cm3以下の範囲を示す。
すなわちエピタキシャル層の全域においてレーザー散乱
体密度が0あるいは5×105個/cm3以下となってい
る訳ではないことが解る。以上のレーザー散乱体に関連
する結果は、図1に示した透過散乱法によるものであ
る。これに対して図6は、結晶表面に垂直に波長1.0
6μmのレーザー光を照射し、照射方向と直交する方向
より散乱光を観測した垂直散乱法と、上記垂直散乱法に
よる結果とを比較したものであり、同図より明らかなよ
うに、垂直散乱法によっても、レーザー散乱体に関連す
る結果は透過散乱法のときと同傾向を示している。ただ
し垂直散乱法では表面散乱光の影響を受けるために、表
面近傍(0〜10μm)の測定が困難となる。そこでウ
ェハ全領域測定可能な透過散乱法による結果を述べたも
のである。
Next, FIG. 4 shows the Czochralski method (CZ
Thickness of silicon wafer manufactured by
Regarding an epitaxial wafer in which 0 μm, 20 μm, 30 μm, and 60 μm epitaxial layers (Epi) are laminated, and an epitaxial wafer in which a 10 μm thick epitaxial layer is laminated on a substrate of a silicon wafer manufactured by a floating zone melting method (FZ method) Shows the results of measuring the laser scatterer density in the depth direction. First, in an epitaxial wafer in which an epitaxial layer is stacked on a silicon wafer substrate manufactured by the Czochralski method, the laser scatterer density is 0 on the surface side of the epitaxial layer, but the laser scatterer is on the interface side with the substrate. The body density is grown by taking over the laser scatterer density of the substrate. That is, in this example, the laser scatterer density of the substrate was approximately 1 × 10 6 pieces / cm 3 , and the laser scatterer density was 1 × 10 6 pieces / cm 3 to 5 in the transition region on the substrate side of the epitaxial layer. The number gradually decreased to × 10 5 pieces / cm 3 , and further decreased to 0. FIG. 5 shows this result from another viewpoint, showing the range where the laser scatterer density is 0 and the range where it is 5 × 10 5 pieces / cm 3 or less.
That is, it is understood that the density of the laser scatterers is not 0 or 5 × 10 5 pieces / cm 3 or less in the entire area of the epitaxial layer. The above results relating to the laser scatterer are based on the transmission scattering method shown in FIG. On the other hand, in FIG. 6, the wavelength 1.0 is perpendicular to the crystal surface.
This is a comparison of the results obtained by the vertical scattering method in which the scattered light was observed from the direction orthogonal to the irradiation direction by irradiating the laser light of 6 μm, and the results by the above-mentioned vertical scattering method. Also, the results related to the laser scatterer show the same tendency as in the case of the transmission scattering method. However, in the vertical scattering method, it is difficult to measure the vicinity of the surface (0 to 10 μm) because it is affected by the surface scattered light. Therefore, the results of the transmission scattering method capable of measuring the entire area of the wafer are described.

【0009】次に貼合せSOIの活性層のレーザー散乱
体密度を5×105個/cm3以下にする手段について説
明する。図7は本発明方法の第1実施例を示し、先ず第
1のウェハ6上にエピタキシャル層7を成長させ、この
エピタキシャル層7の上に酸化膜8を形成する。次いで
エピタキシャル層7側を接着面として第1のウェハ6を
第2のウェハ9上に重ね合わせ、1100℃程度の熱処
理を施して両ウェハ6,9を接着する。次いで第1のウ
ェハ6の接着面の反対側を平面研削と研磨によって薄膜
化し、更に仕上げ研磨を施して第1のウェハ6の全部と
エピタキシャル層7の一部を除去し、こうして貼合せS
OI5に形成する。但し酸化膜8は第2のウェハ9側に
形成することもできるし、エピタキシャル層7を成長さ
せた第1のウェハ6と第2のウェハ9との両方に形成す
ることもできる。また第2のウェハ9としては、チョク
ラルスキー法によって形成したシリコンウェハ、浮遊帯
域溶融法によって形成したシリコンウェハ、石英、セラ
ミックスなどを用いることができる。更に研磨に代えて
エッチングなどを用いることもできる。この貼合せSO
I5のエピタキシャル層7のレーザー散乱体密度は、酸
化膜8側界面では0となっているものの、第1のウェハ
6側界面に向って漸増し、第1のウェハ6側界面では第
1のウェハ6のレーザー散乱体密度を引き継いでいる。
したがって図5よりレーザー散乱体密度が5×105
/cm3以下の領域の厚さを求め、その厚さ以下となる
ようにエピタキシャル層7を研磨することにより、エピ
タキシャル層7の全域でレーザー散乱体密度が5×10
5個/cm3以下となり、したがって酸化膜耐圧が十分に
高い貼合せSOI5を得ることができる。
Next, the means for adjusting the density of the laser scatterers in the active layer of the bonded SOI to 5 × 10 5 pieces / cm 3 or less will be described. FIG. 7 shows a first embodiment of the method of the present invention. First, an epitaxial layer 7 is grown on a first wafer 6 and an oxide film 8 is formed on the epitaxial layer 7. Next, the first wafer 6 is superposed on the second wafer 9 with the epitaxial layer 7 side as the bonding surface, and heat treatment at about 1100 ° C. is performed to bond the two wafers 6 and 9. Next, the opposite side of the bonding surface of the first wafer 6 is thinned by surface grinding and polishing, and further subjected to finish polishing to remove all of the first wafer 6 and a part of the epitaxial layer 7, and thus the bonding S
Form to OI5. However, the oxide film 8 can be formed on the second wafer 9 side, or can be formed on both the first wafer 6 and the second wafer 9 on which the epitaxial layer 7 has been grown. As the second wafer 9, a silicon wafer formed by the Czochralski method, a silicon wafer formed by the floating zone melting method, quartz, ceramics, or the like can be used. Further, etching or the like may be used instead of polishing. This bonded SO
Although the laser scatterer density of the epitaxial layer 7 of I5 is 0 at the interface on the oxide film 8 side, it gradually increases toward the interface on the first wafer 6 side and reaches the first wafer at the interface on the first wafer 6 side. The laser scatterer density of 6 is succeeded.
Therefore, the thickness of the region in which the laser scatterer density is 5 × 10 5 pieces / cm 3 or less is obtained from FIG. Scatterer density is 5 × 10
The number is 5 pieces / cm 3 or less, and thus a bonded SOI 5 having a sufficiently high oxide film withstand voltage can be obtained.

【0010】次に本発明方法の第2実施例について説明
する。既述のごとくエピタキシャル層のレーザー散乱体
密度は、成長基板のレーザー散乱体密度を引き継いで成
長する。したがって成長基板のレーザー散乱体密度を低
減しておくことにより、エピタキシャル層のレーザー散
乱体密度を低減することができる。図4に示されている
ごとく、浮遊帯域溶融法(FZ法)によって製造したシ
リコンウェハの基板上にエピタキシャル層を積層したエ
ピタキシャルウェハについて見ると、この場合には成長
基板のレーザー散乱体密度が0のために、エピタキシャ
ル層のレーザー散乱体密度も0となっている。したがっ
て図7において、第1のウェハ6を浮遊帯域溶融法によ
って形成することにより、ピタキシャル層7はその全域
でレーザー散乱体密度が5×105個/cm3以下となる
から、酸化膜耐圧が十分に高い貼合せSOI5を得るこ
とができる。なおこの場合、第1のウェハ6のレーザー
散乱体密度も0であるから、第1のウェハ6の一部だけ
を研磨などによって除去することもできるが、エピタキ
シャル層7を形成した観点から、少なくとも第1のウェ
ハ6の全部を除去することが好ましい。
Next, a second embodiment of the method of the present invention will be described. As described above, the density of the laser scatterers in the epitaxial layer is succeeded by the density of the laser scatterers in the growth substrate. Therefore, by reducing the laser scatterer density of the growth substrate, the laser scatterer density of the epitaxial layer can be reduced. As shown in FIG. 4, regarding an epitaxial wafer in which an epitaxial layer is laminated on a substrate of a silicon wafer manufactured by the floating zone melting method (FZ method), in this case, the laser scatterer density of the growth substrate is 0. Therefore, the laser scatterer density of the epitaxial layer is also zero. Therefore, in FIG. 7, by forming the first wafer 6 by the floating zone melting method, the density of the laser scatterers in the entire axial layer 7 becomes 5 × 10 5 pieces / cm 3 or less, so that the oxide film withstand voltage is reduced. A sufficiently high bonded SOI5 can be obtained. In this case, since the laser scatterer density of the first wafer 6 is also 0, it is possible to remove only a part of the first wafer 6 by polishing or the like, but at least from the viewpoint of forming the epitaxial layer 7, It is preferable to remove all of the first wafer 6.

【0011】次にエピタキシャル層7を成長させる第1
のウェハ6のレーザー散乱体密度を5×105個/cm3
以下とするための第2の手段について説明する。チョク
ラルスキー法において引上げ速度を0.6mm/min
以下で引き上げた直径6インチ、結晶軸<100>、P
型、ボロンドープ、抵抗率0.01〜0.02Ωcm、
酸素濃度12〜15×1017atoms/cm3の結晶
のレーザー散乱体密度は、5×105個/cm3以下であ
り、したがってこの結晶を成長基板としてエピタキシャ
ル成長を行ったエピタキシャル層中のレーザー散乱体密
度も、5×105個/cm3以下であった。したがって少
なくとも第1のウェハ6の全部を除去することにより、
酸化膜耐圧が十分に高い貼合せSOI5を得ることがで
きる。
Next, a first epitaxial layer 7 is grown.
The laser scatterer density of the wafer 6 is 5 × 10 5 pieces / cm 3
The second means for achieving the following will be described. Pulling speed is 0.6mm / min in Czochralski method
6 inch diameter pulled up below, crystal axis <100>, P
Mold, boron doped, resistivity 0.01 to 0.02 Ωcm,
The laser scatterer density of a crystal having an oxygen concentration of 12 to 15 × 10 17 atoms / cm 3 is 5 × 10 5 pieces / cm 3 or less. Therefore, laser scattering in an epitaxial layer in which epitaxial growth is performed using this crystal as a growth substrate is performed. The body density was also 5 × 10 5 pieces / cm 3 or less. Therefore, by removing at least the entire first wafer 6,
It is possible to obtain a bonded SOI 5 having a sufficiently high breakdown voltage of an oxide film.

【0012】次にエピタキシャル層7を成長させる第1
のウェハ6のレーザー散乱体密度を5×105個/cm3
以下とするための第3の手段、すなわちチョクラルスキ
ー法において通常の引上げ速度でシリコン単結晶を製造
した後に熱処理を施す方法について、次に説明する。図
8は熱処理条件を各種変更したときのシリコンウェハ1
の表面近傍(0〜3μm)でのレーザー散乱体の密度を
示す。同図に示されるごとく、熱処理を何ら施さないと
きには、この実施例では3×106個/cm3程度のレー
ザー散乱体が存在しており、このレーザー散乱体の密度
は1300℃程度までの熱処理を施そうとも、また熱処
理時間を長くしてもほとんど変わることがなく、すなわ
ちこのレーザー散乱体は非常に安定であることが解る。
しかしながら熱処理温度を1330℃程度以上とする
と、少なくとも0.5Hrの熱処理を施すことにより、
ほぼ完全にレーザー散乱体は消滅している。したがって
シリコンの融点を考慮して、1330〜1400℃、
0.5Hr以上の熱処理を施すことにより、レーザー散
乱体をほぼ完全に消し去ることができ、この第1のウェ
ハ6上にエピタキシャル層を積層することにより、酸化
膜耐圧が十分に高い貼合せSOI5を得ることができ
る。発明者が行った実施例として、チョクラルスキー法
において通常の引上げ速度で成長させた直径6インチ、
結晶軸<100>、N型、アンチモンドープ、抵抗率
0.01〜0.02Ωcm、酸素濃度13〜16×10
17atoms/cm3の結晶について、上記1330〜
1400℃、0.5Hr以上の熱処理を施し、エピタキ
シャル成長を行っても、エピタキシャル層中のレーザー
散乱体密度は、5×105個/cm3以下であった。
Next, the first epitaxial layer 7 is grown.
The laser scatterer density of the wafer 6 is 5 × 10 5 pieces / cm 3
A third means for achieving the following, that is, a method of performing heat treatment after manufacturing a silicon single crystal at a normal pulling rate in the Czochralski method will be described below. FIG. 8 shows a silicon wafer 1 when various heat treatment conditions are changed.
The density of the laser scatterer in the vicinity of the surface (0 to 3 μm) is shown. As shown in the figure, when no heat treatment is performed, in this embodiment, about 3 × 10 6 pieces / cm 3 of laser scatterers are present, and the density of the laser scatterers is up to about 1300 ° C. It can be seen that the laser scatterer is very stable even if it is subjected to the heat treatment or the heat treatment time is prolonged.
However, if the heat treatment temperature is set to about 1330 ° C. or higher, by performing heat treatment of at least 0.5 Hr,
The laser scatterers have disappeared almost completely. Therefore, considering the melting point of silicon, 1330 to 1400 ° C,
The laser scatterer can be almost completely erased by applying a heat treatment of 0.5 Hr or more. By stacking an epitaxial layer on the first wafer 6, a bonded SOI 5 having a sufficiently high oxide film breakdown voltage. Can be obtained. As an example performed by the inventor, a diameter of 6 inches grown at a normal pulling rate in the Czochralski method,
Crystal axis <100>, N type, antimony doped, resistivity 0.01 to 0.02 Ωcm, oxygen concentration 13 to 16 × 10
For a crystal of 17 atoms / cm 3 , the above 1330-
Even when the epitaxial heat treatment was performed at 1400 ° C. for 0.5 hr or more, the laser scatterer density in the epitaxial layer was 5 × 10 5 pieces / cm 3 or less.

【0013】なおシリコンインゴットからシリコンウェ
ハへの加工と、1330〜1400℃、0.5Hr以上
の熱処理との間には特に関係はないから、本実施例のよ
うにシリコンウェハに加工した後に熱処理を行うことが
出来るほか、シリコンインゴットのままで熱処理を施
し、しかる後にシリコンウェハに加工することも出来
る。また熱処理を行う装置については、熱処理専用の装
置を用いることが出来るほか、引き上げ装置自体を熱処
理炉として用いることができ、この方法はシリコンイン
ゴットのままで熱処理を施すときに特に効果的である。
また上記実施例では熱処理を不活性ガス、具体的にはA
rガス雰囲気下で行ったものであるが、H2雰囲気下で
行うこともでき、このときには1180℃以上、30m
in以上の熱処理を施すことにより、例えば1200
℃、60minの熱処理を施すことにより、ほぼ完全に
レーザー散乱体を消滅させることができる。
Since there is no particular relation between the processing of a silicon ingot into a silicon wafer and the heat treatment at 1330 to 1400 ° C. and 0.5 Hr or more, the heat treatment is performed after processing the silicon wafer as in this embodiment. In addition to the heat treatment, the silicon ingot may be heat-treated as it is and then processed into a silicon wafer. As for the apparatus for heat treatment, a dedicated apparatus for heat treatment can be used, and the pulling apparatus itself can be used as a heat treatment furnace. This method is particularly effective when heat treatment is performed on a silicon ingot as it is.
In the above embodiment, the heat treatment is performed with an inert gas, specifically A
Although it was carried out in an r gas atmosphere, it can also be carried out in an H 2 atmosphere.
By applying a heat treatment of not less than in, for example, 1200
By performing heat treatment at 60 ° C. for 60 minutes, the laser scatterer can be almost completely extinguished.

【0014】[0014]

【発明の効果】本発明によれば、酸化膜耐圧が十分に高
く、したがってデバイスの歩留りが良好な貼合せSOI
と、その製造方法を得ることができる。
According to the present invention, a bonded SOI having a sufficiently high breakdown voltage of an oxide film and thus a good device yield.
And the manufacturing method can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】レーザー散乱体密度の測定手法を示す図FIG. 1 is a diagram showing a method for measuring a laser scatterer density.

【図2】レーザー散乱体密度とBモード不良品率との関
係を示す図
FIG. 2 is a diagram showing the relationship between the density of laser scatterers and the B-mode defective product rate.

【図3】同じくCモード良品率との関係を示す図FIG. 3 is a graph showing a relationship with the C-mode non-defective rate.

【図4】エピタキシャルウェハの深さ方向のレーザー散
乱体密度を示す図
FIG. 4 is a diagram showing a laser scatterer density in a depth direction of an epitaxial wafer.

【図5】エピタキシャル層の厚さに対する低欠陥領域と
遷移域を示す図
FIG. 5 is a diagram showing a low defect region and a transition region with respect to the thickness of an epitaxial layer.

【図6】垂直散乱法および透過散乱法によるエピタキシ
ャルウェハのレーザー散乱体深さ方向分布を示す図
FIG. 6 is a diagram showing depth distributions of laser scatterers on an epitaxial wafer by a vertical scattering method and a transmission scattering method.

【図7】本発明方法の一実施例を示す工程図FIG. 7 is a process chart showing an embodiment of the method of the present invention.

【図8】熱処理温度とレーザー散乱体密度との関係を示
す図
FIG. 8 is a graph showing the relationship between heat treatment temperature and laser scatterer density.

【図9】従来の貼合せSOIの製造方法を示す工程図FIG. 9 is a process diagram showing a conventional method for manufacturing a bonded SOI.

【符号の説明】[Explanation of symbols]

1…シリコンウェハ 2…レーザー発射装置 5
…貼合せSOI 6…第1のウェハ 7…エピタキシャル層 8
…酸化膜 9…第2のウェハ
1 ... Silicon wafer 2 ... Laser emitting device 5
... Bonded SOI 6 ... First wafer 7 ... Epitaxial layer 8
… Oxide film 9… Second wafer

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】基板上に、絶縁層を介して、レーザー散乱
体密度が5×105個/cm3以下であるエピタキシャル
層が貼り合わせられた貼合せSOI。
1. A bonded SOI, in which an epitaxial layer having a laser scatterer density of 5 × 10 5 particles / cm 3 or less is bonded onto a substrate via an insulating layer.
【請求項2】第1のウェハ上にエピタキシャル層を成長
させ、この第1のウェハと第2のウェハとの少なくとも
いずれか一方に絶縁層を形成し、前記エピタキシャル層
側を接着面として第1のウェハを第2のウェハ上に重ね
合わせて両ウェハを接着し、前記第1のウェハの全部と
エピタキシャル層の一部を除去して半導体ウェハに形成
する貼合せSOIの製造方法。
2. An epitaxial layer is grown on a first wafer, an insulating layer is formed on at least one of the first wafer and the second wafer, and the first epitaxial layer is used as a bonding surface. The method of manufacturing a bonded SOI, wherein the wafer is overlaid on a second wafer, the two wafers are adhered to each other, and the entire first wafer and a part of the epitaxial layer are removed to form a semiconductor wafer.
【請求項3】第1のウェハを浮遊帯域溶融法によって形
成し、この第1のウェハ上にエピタキシャル層を成長さ
せ、この第1のウェハと第2のウェハとの少なくともい
ずれか一方に絶縁層を形成し、前記エピタキシャル層側
を接着面として第1のウェハを第2のウェハ上に重ね合
わせて両ウェハを接着し、少なくとも前記第1のウェハ
の全部を除去して半導体ウェハに形成する貼合せSOI
の製造方法。
3. A first wafer is formed by a floating zone melting method, an epitaxial layer is grown on the first wafer, and an insulating layer is formed on at least one of the first wafer and the second wafer. Forming a semiconductor wafer by laminating the first wafer on the second wafer with the epitaxial layer side as the adhesive surface and adhering the two wafers together, and removing at least the entire first wafer to form a semiconductor wafer. Combined SOI
Manufacturing method.
【請求項4】前記浮遊帯域溶融法に代えて、前記第1の
ウェハを、引上げ速度が0.6mm/min以下のチョ
クラルスキー法によって形成する請求項3記載の貼合せ
SOIの製造方法。
4. The method for producing a bonded SOI according to claim 3, wherein the first wafer is formed by a Czochralski method with a pulling rate of 0.6 mm / min or less, instead of the floating zone melting method.
【請求項5】前記浮遊帯域溶融法に代えて、前記第1の
ウェハを、チョクラルスキー法によって製造した後に、
1330〜1400℃、0.5Hr以上の熱処理を施し
て形成する請求項3記載の貼合せSOIの製造方法。
5. In place of the floating zone melting method, after the first wafer is manufactured by the Czochralski method,
The method for manufacturing a bonded SOI according to claim 3, which is formed by performing a heat treatment at 1330 to 1400 ° C. at 0.5 Hr or higher.
【請求項6】前記熱処理に代えて、H2雰囲気において
1180℃以上、30min以上の熱処理を施す請求項
5記載の貼合せSOIの製造方法。
6. The method for producing a bonded SOI according to claim 5, wherein instead of the heat treatment, a heat treatment at 1180 ° C. or higher for 30 min or longer is performed in an H 2 atmosphere.
JP25015593A 1993-09-09 1993-09-09 Laminated SOI and manufacturing method thereof Expired - Lifetime JP3260516B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25015593A JP3260516B2 (en) 1993-09-09 1993-09-09 Laminated SOI and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH0786540A true JPH0786540A (en) 1995-03-31
JP3260516B2 JP3260516B2 (en) 2002-02-25

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ID=17203646

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Country Status (1)

Country Link
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5744380A (en) * 1993-08-23 1998-04-28 Komatsu Electronic Metals Co., Ltd. Method of fabricating an epitaxial wafer
EP0984483A2 (en) * 1998-09-04 2000-03-08 Canon Kabushiki Kaisha Semiconductor substrate and method for producing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5744380A (en) * 1993-08-23 1998-04-28 Komatsu Electronic Metals Co., Ltd. Method of fabricating an epitaxial wafer
EP0984483A2 (en) * 1998-09-04 2000-03-08 Canon Kabushiki Kaisha Semiconductor substrate and method for producing the same
EP0984483A3 (en) * 1998-09-04 2000-11-15 Canon Kabushiki Kaisha Semiconductor substrate and method for producing the same

Also Published As

Publication number Publication date
JP3260516B2 (en) 2002-02-25

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