JP5730688B2 - Silicon substrate manufacturing method - Google Patents

Description

  The present invention relates to a method of manufacturing a silicon substrate and a silicon substrate, and more particularly to a method of manufacturing a silicon substrate cut out from a silicon single crystal manufactured by the Czochralski method and a silicon substrate obtained thereby.

  Among silicon wafers (silicon substrates), there is a silicon wafer having a defect-free layer (hereinafter also simply referred to as a wafer). The defect-free layer referred to here is a so-called DZ (Dented Zone), which is a layer (or a layer with few defects) free from defects (BMD: Bulk Micro Defect) caused by silicon oxide precipitates.

  One of the conventional methods for manufacturing a silicon wafer having a defect-free layer is a technique using a bonding method. This technology uses a silicon wafer (referred to as an FZ wafer) cut out from a silicon single crystal grown by a floating zone (FZ) method as the device forming side wafer, and Czochralski (CZ) on the support wafer side. A silicon wafer (referred to as a CZ wafer) cut out from a silicon single crystal grown by the method is used (for example, Patent Document 1). This is referred to as an FZ-CZ bonded wafer. The FZ-CZ bonded wafer according to Patent Document 1 has a defect-free layer and can provide a high-resistance substrate.

  Further, as a silicon wafer obtained by another conventional bonding method, there is a silicon wafer using a CZ wafer on both the device forming side and the support side (for example, Patent Document 2). This is referred to as a CZ-CZ bonded wafer. The CZ-CZ bonded wafer according to Patent Document 2 can provide a high-resistance substrate after utilizing defects peculiar to CZ as a lifetime killer.

Japanese Patent No. 3573243 Japanese Patent No. 3947953 JP 2010-21394 A Paragraph 0011 of JP2010-208894A

Page 9 of Baifukan Advanced Electronics Series, edited by Kawamata, Bulk Crystal Growth Technology (First Edition, May 20, 1994)

  Each of the FZ-CZ bonded wafer and the CZ-CZ bonded wafer has advantages and disadvantages.

  The FZ-CZ bonded wafer has the advantages that it is difficult to perform BMD because the oxygen concentration of the FZ wafer itself is low, and it is easy to form a defect-free layer. However, in recent years, a large number of wafers with a diameter of 200 or 300 mm have been widely used as wafers for manufacturing semiconductor devices, and a large-diameter wafer having a diameter of 450 mm or more has also appeared (for example, Patent Document 3). However, the FZ method has a problem that it is difficult to sufficiently provide a large-diameter FZ wafer because stable production of such a large-diameter crystal is difficult.

  On the other hand, as for the CZ-CZ bonded wafer, the CZ wafer itself already corresponds to a large-diameter wafer, and it is the mainstream as a wafer for manufacturing semiconductor devices. Therefore, it is superior in cost compared with the FZ wafer and is suitable for mass production. However, in the CZ wafer, oxygen is contained in the single crystal during the manufacturing process, and BMD is generated based on this oxygen (for example, Patent Document 4). For this reason, there is a problem that it is difficult to form a defect-free layer.

  In addition, it is known that oxygen in the CZ wafer generates oxygen donors by heat treatment at around 450 ° C. and greatly changes the resistivity of the CZ wafer. Such oxygen donors are said to be extinguished by heat treatment at about 650 ° C. (Non-patent Document 1).

  However, according to the research of the present inventors, when low-temperature annealing at about 450 ° C. is performed again for a long time in the device manufacturing process, a part of oxygen in the CZ wafer may become an oxygen donor again. It has been found that this is a fatal drawback in power devices that require precise resistivity design. That is, in the CZ wafer as an active layer for power devices, it is necessary to further suppress the generation of BMD and the generation of oxygen donors.

  Therefore, an object of the present invention is to provide a silicon substrate manufacturing method for manufacturing a silicon substrate with a reduced oxygen concentration using a silicon substrate cut out from a silicon single crystal manufactured by the Czochralski method. That is.

  Another object is to provide a silicon substrate with a reduced oxygen concentration using a silicon substrate cut out from a silicon single crystal produced by the Czochralski method.

In order to achieve the above object, the silicon substrate manufacturing method according to the present invention is such that the initial oxygen concentration Oi (atomic number / cm ³ ) of the silicon substrate cut out from the silicon single crystal manufactured by the Czochralski method is 5. A step (a) of processing a thickness Tsi (μm) of at least a device formation scheduled region portion of the silicon substrate of 0 × 10 ^{17 to} 9.0 × 10 ¹⁷ atoms / cm ³ to 50 to 200 μm; When the silicon substrate processed to ˜200 μm is assumed to have an annealing temperature T (° C.), an annealing time t (seconds), and an initial oxygen concentration Oi (atomic number / cm ³ ) of the silicon substrate, the following formula (1)
t = f (Oi) ² (Tsi / 200) ² /{[0.52exp[-2.94×10 ⁴ / (273 + T)]} (1)
(In the formula, f (Oi) = 1.43 × 10 ⁻⁶⁹ Oi ⁴ −3.35 × 10 ⁻⁵¹ Oi ³ + 2.51 × 10 ⁻³³ Oi ² −3.99 × 10 ⁻¹⁶ Oi−83. And (b) a step of annealing at a temperature equal to or higher than a temperature T (° C.) given by (T. 43) for a time longer than t (seconds).

  According to the present invention, after processing a silicon substrate cut out from a silicon single crystal manufactured by the Czochralski method to a thickness of 50 to 200 μm, an annealing temperature and annealing time satisfying the formula (1) obtained in advance. By annealing, the oxygen inside the substrate can be reduced and the oxygen concentration can be lowered as a silicon substrate alone. As a result, the BMD can be reduced by reducing the oxygen concentration, and a silicon substrate having a defect-free layer can be provided.

It is a schematic diagram of the thinned wafer which made the circumference | surroundings of the wafer into the ring-shaped convex shape, FIG. 1 (a) is a top view, FIG.1 (b) is sectional drawing which follows the BB line in (a) figure. . It is a graph which shows the relationship between the initial oxygen concentration Oi of the silicon wafer in which the average oxygen concentration after annealing becomes 4.5 × 10 ¹⁷ atoms / cm ³ and the diffusion length of oxygen atoms when the thickness of the silicon wafer is 200 μm. It is sectional drawing which shows an example of a bonded wafer. It is a graph which shows the simulation result of the oxygen concentration in a wafer depth direction. It is a schematic diagram which shows the generation | occurrence | production situation of BMD copied from the image photograph of the cleavage plane in Example 3.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Each drawing is for explaining the embodiment, and its size and scale are exaggerated or omitted, so that it is different from the size and scale of actual members and devices.

  In the method of manufacturing a silicon wafer (silicon substrate) according to the present embodiment, first, a silicon wafer cut out from a silicon single crystal manufactured by a normal CZ method is prepared.

When the silicon wafer prepared here is a high-resistance wafer, the resistivity is about 30 to 200 Ωcm (generally about 1 to 15 Ωcm in a normal IC silicon wafer), and the oxygen concentration is 7 × 10 ¹⁷ to 8 × 10 ¹⁷ atoms / cm ³ . The wafer thickness varies depending on the wafer diameter. For example, a typical thickness is about 625 μm for a 150 mm diameter wafer, about 725 μm for 200 mm, about 775 μm for 300 mm, and about 925 μm for 450 mm. The wafer thickness is standardized (including the standardization study stage) corresponding to the diameter of a semiconductor device manufacturing wafer. Therefore, also in the present embodiment, the wafer prepared first may be a wafer having a thickness manufactured as standardized.

  Further, the wafer prepared here may be a wafer that is cut out from an ingot and is not subjected to mirror polishing (mirror polishing) only by rough finishing polishing (polishing before mirror polishing). This is because, as will be described later, after reducing the oxygen concentration, a device forming surface is determined, and the surface is mirror-polished to provide a device forming wafer. Of course, a mirror-polished wafer may be prepared. Similarly, there may or may not be a back surface gettering layer (an IG (Intrinsic Gettering) layer that mechanically damages the back surface of the wafer).

  Next, the wafer is thinned to a thickness of about 50 to 200 μm required from the device design. For this purpose, an existing polishing method such as mechanical polishing, sandblasting, or CMP (Chemical Mechanical Polishing) may be used, and detailed description thereof is omitted.

  When the thickness of the wafer is about 50 to 200 μm, since the thickness of the wafer is thin, the wafer is easily broken and easily warped. Also, handling is not good. Since wafer thinning is generally performed after device formation, there is also a meaning of protecting the device forming surface along with supporting the thinned wafer, and a protective sheet made of resin or glass is adhered (or bonded) to the device forming surface. Later, the back surface (the surface opposite to the surface on which the device is formed) is polished.

  However, in this embodiment, as will be described later, since a thinned wafer (referred to as a thinned wafer) is annealed at a high temperature, a resin sheet cannot be used. Further, even when glass is used, a resin adhesive cannot be used. Further, when glass is directly bonded, oxygen removal ability in an annealing process described later is lowered, so that it cannot be used. Therefore, in this embodiment, when the wafer is thinned, the periphery of the wafer is left thicker than the inside so as to have a ring-like convex shape. As a technique for processing a wafer so as to have such a ring-shaped convex shape, there are techniques such as Japanese Patent Application Laid-Open Nos. 2007-019461 and 2010-194680.

  The techniques of these publications are techniques after device formation, but can be adopted as this embodiment in order to obtain a wafer having a thin main part and a ring-like convex shape.

  1A and 1B are schematic views of a thinned wafer having a ring-like convex shape around the wafer. FIG. 1A is a plan view, and FIG. 1B is a BB line in FIG. It is sectional drawing which follows.

  As shown in the figure, a wafer 1 having a thin periphery with a ring-shaped convex shape has a ring-shaped convex portion 2 around the wafer. On the other hand, the inner side (C portion in FIG. 1A) of the ring-shaped convex portion 2 is a portion to be a device formation scheduled region, and the thickness (t in FIG. 1B) is reduced to 50 to 200 μm. It is.

  The width of the ring-shaped convex portion 2 (portion A in FIG. 1B) may be small if the diameter of the wafer is small, and large if the diameter is large.

  For example, when the diameter of the wafer is 300 to 450 mm, the width A is preferably 2 to 5 mm. If the width A is less than 2 mm, it becomes difficult to hold the shape of the wafer after polishing, and there is no point in forming the ring-shaped convex portion 2. On the other hand, if it is about 5 mm, even if it is a 300-450 mm wafer, a shape can fully be hold | maintained. If the width A is too large, the device formation scheduled area decreases, which is not preferable. Therefore, it is preferable to set this width as the upper limit.

  The thickness of the ring-shaped convex part 2 (h in FIG. 1B) is 300 to 1000 μm. However, this thickness h does not exceed the original thickness when the wafer was provided. The thickness h of the ring-shaped convex portion 2 may be the same thickness as when the wafer is provided, or may be thinned as necessary. If the thickness h of the ring-shaped convex portion 2 is less than 300 μm, there is a possibility that the entire shape retaining ability may be lost when the inner side is ground and thinned.

  For the specific manufacture of the wafer 1 having the ring-shaped convex portion 2, an existing method (for example, the above-mentioned JP-A-2007-019461) is used.

  First, as a wafer to be ground, a wafer before the device forming process is prepared as described above. Then, the wafer is placed on the chuck table of the grinding apparatus and held by suction. Then, while rotating the wafer together with the chuck table, the grinding wheel is pressed against the grinding surface of the wafer, and the grinding wheel is rotated to perform grinding. The grindstone is such that the diameter of the outermost circumference of the rotating track is larger than the radius of the portion where the wafer is thinned and smaller than the diameter of the portion where the wafer is thinned, and the diameter of the innermost circumference of the rotating track is the wafer Is formed to be smaller than the radius of the portion to be processed thinly. Thereby, the ring-shaped convex part 2 remains around the wafer, and the inside thereof is ground and thinned.

  Various conditions such as the rotation speed of the wafer, the rotation speed of the grinding wheel, and the pressing force may be adjusted so that the wafer does not crack or chip during grinding. Further, the grinding process itself may be performed in two or more stages.

  Since the techniques of the above publications process the wafer after the device is formed, the back side where no device is formed is ground. In this respect, in this embodiment, since the device is not formed, it may be ground from either surface. For this reason, as will be described later, grinding is performed depending on whether a thin wafer with a reduced oxygen concentration is provided alone or as a bonded wafer, a wafer with an oxide film, an SOI (Silicon On Insulator) wafer, or the like. You just have to decide the side. The same applies when the ring-shaped convex portion 2 is not formed on the side to be ground.

  Thus, the wafer 1 having the ring-shaped convex portion 2 can maintain the shape of the thinned wafer alone without using a protective sheet or protective glass, and can easily perform high-temperature annealing. Therefore, during annealing, it is possible to use a normal annealing furnace or the like to place a plurality of thinned wafers in a state where they are standing on the boat for annealing.

  Further, annealing of the thinned wafer can be performed without forming a ring-shaped convex portion on the thinned wafer by devising a support method in the annealing furnace. For example, it is made of SiC, quartz, etc., and has a striped chevron or a plate or bowl-shaped support having a plurality of scattered chevron projections on its surface. Annealed wafer may be annealed by placing it on a plane.

  In this case, since the whole wafer may be ground thinly, the thinning process becomes easier than manufacturing a wafer having a ring-shaped convex portion.

Next, the thinned wafer is annealed at a high temperature. The annealing temperature and processing time depend on the thickness of the thinned wafer and the initial average oxygen concentration. From the experimental results to be described later, when the average oxygen concentration after annealing was 4.5 × 10 ¹⁷ atoms / cm ³ or less, good results were obtained with respect to the BMD number and resistivity variation.

FIG. 2 shows the relationship between the initial oxygen concentration Oi of a silicon wafer in which the average oxygen concentration after annealing is 4.5 × 10 ¹⁷ atoms / cm ³ and the oxygen atom diffusion length when the thickness of the silicon wafer is 200 μm. It is a graph which shows. “Measured values” indicated by circles in the figure are when the initial oxygen concentration is 8.0 × 10 ¹⁷ atoms / cm ³ in a silicon wafer having a thickness of 200 μm, and the others (diamonds in the figure) were obtained by simulation. It is a result.

  Incidentally, the wafer sample from which the actual measurement value was obtained was prepared in the same manner as the sample of the example described later. The simulation was performed as follows.

A one-dimensional diffusion equation when the oxygen concentration C (atomic number / cm ³ ) in the silicon substrate is given as follows.

∂C (x, t) / ∂t = D (T) ∂ 2 C (x, t) / ∂ 2 x
Here, D (T (° C.)) is a diffusion constant of oxygen atoms depending on the annealing temperature T and is obtained by the following equation.

D (T) = 0.13exp [-2.94 × 10 ⁴ / (273 + T)]... Unit (cm ² / s)
The above equation can be simulated by the explicit method, and the following calculation formula is used.

C (x _j , t _{n + 1} ) = C (x _j , t _n ) + D (T) (Δt / Δx ² ) [C (x _{j + 1} , t _n ) −2C (x _j , t _n ) + C (x _{j− 1} , t _n )]
When the surface of the silicon substrate having the initial oxygen concentration Oi is x = 0 (cm) and the substrate center direction is a positive direction, the initial condition at this time is C (x, 0) = Oi at time t = 0 (s). , And x = 0 and C (0, t) = 0 (atomic number / cm ³ ). Δt and Δx can be arbitrarily set. In this simulation, Δt = 1200 (seconds) and Δx (cm) are values obtained by dividing the distance to the center of the silicon substrate by 10 as shown in the simulation results of FIG. . The average oxygen concentration is obtained by a value (average value) obtained by dividing the result obtained from the above-described simulation by doubling the total oxygen concentration from the silicon substrate surface to the thickness center and dividing the result by the thickness.

The derivation method of FIG. 2 will be described below. A silicon wafer having an initial oxygen concentration of 8 × 10 ¹⁷ atoms / cm ³ and thinned to a thickness of 200 μm is annealed at a temperature of 1100 ° C. for 60 hours, and then the same method as in the examples described later. Measurement was performed with an average oxygen concentration to obtain 4.5 × 10 ¹⁷ atoms / cm ³ . As for the oxygen concentration, good results have been obtained for the number of BMDs and resistivity fluctuations from the experimental results described later, and similarly good results if the oxygen concentration is equal to or lower than the oxygen concentration after annealing regardless of the initial oxygen concentration of the silicon wafer. It can be seen that When the initial oxygen concentration of the silicon wafer is different from 5 × 10 ¹⁷ atoms / cm ³ , 6 × 10 ¹⁷ atoms / cm ³ , 7 × 10 ¹⁷ atoms / cm ^3, and 9 × 10 ¹⁷ atoms / cm ³ Annealing in which the average oxygen concentration after annealing is 4.5 × 10 ¹⁷ atoms / cm ³ when the above-described simulation is performed and a 200 μm-thick silicon wafer having each initial oxygen concentration is annealed for 60 hours. The temperature T is obtained, and the diffusion length L (cm) of the oxygen atom after annealing at each initial oxygen concentration is calculated from the following equation:
L = 2√ (D (T) t)
FIG. 2 is obtained by plotting the diffusion length of oxygen atoms after annealing obtained from the actually measured values and the simulation results for each initial oxygen concentration.

  The broken line in FIG. 2 is an approximate curve based on the simulation result and is expressed by the following equation.

f (Oi) = 1.43 × 10 ⁻⁶⁹ Oi ⁴ −3.35 × 10 ⁻⁵¹ Oi ³ + 2.51 × 10 ⁻³³ Oi ² −3.99 × 10 ⁻¹⁶ Oi−83.43
This equation, adding effect when the thickness of the silicon wafer which is thinned below 200 [mu] m and Tsi ([mu] m), the initial oxygen concentration Oi (atoms pieces / ^cm 3), the annealing temperature T (° C.) and annealing Expression (1), which is a relational expression with time t (seconds), is obtained as follows.
t = f (Oi) ² (Tsi / 200) ² / [4D (T)] (2)
However, in the formula (1), D (T) is a diffusion constant (unit: cm ² / s) of oxygen atoms depending on the annealing temperature, and is given by the following formula (3).

D (T) = 0.13exp [-2.94 × 10 ⁴ / (273 + T)] (3)
From these formulas (2) and (3), the following formula (1) is obtained.

t = f (Oi) ² (Tsi / 200) ² /{[0.52exp[-2.94×10 ⁴ / (273 + T)]} (1)
From the above, if the initial oxygen concentration Oi (atomic number / cm ³ ) of the silicon wafer, the thickness Tsi (μm) of the thinned silicon wafer and the annealing temperature T (° C.) are arbitrarily selected, the equation (1) If annealing is performed for t (seconds) or more, a silicon wafer having an average oxygen concentration after annealing of 4.5 × 10 ¹⁷ atoms / cm ³ or less can be obtained.

  Also, the annealing temperature suitable for the conditions of the silicon wafer can be obtained by determining the annealing time in advance and calculating the equation (1) in reverse. For example, if the annealing time is increased beyond 60 hours, it is effective for lowering the oxygen concentration inside the silicon wafer and lowering the annealing temperature. It is not preferable. Therefore, the minimum annealing temperature when annealing is performed for up to 60 hours with respect to an arbitrary wafer thickness and initial oxygen concentration can be achieved.

  On the other hand, the upper limit temperature may be any temperature at which the thinned wafer is not damaged by the temperature. However, when the temperature exceeds 1250 ° C., the yield is likely to be affected by metal contamination from the furnace. The processing time at the upper limit temperature can be determined according to the condition of the silicon wafer from the equation (1).

The atmosphere in the annealing furnace during annealing needs to be a non-oxidizing atmosphere such as argon gas (Ar) or nitrogen (N ₂ ). This is to prevent the silicon of the thinned wafer being annealed from being oxidized into an oxide film.

A wafer having a low oxygen concentration can be provided as a single wafer by using the wafer cut from the single crystal formed by the CZ method by the above process, that is, the wafer thinning and the subsequent annealing process. . According to an example described later, when the thickness in the device formation planned region is 50 to 200 μm, the average oxygen concentration in the wafer can be 4.5 × 10 ¹⁷ atoms / cm ³ or less.

And it succeeded in reducing BMD which is a defect resulting from the silicon oxide in a wafer by reducing oxygen concentration in this way. As in Examples described later, the average BMD can be less than 8.5 × 10 ⁶ pieces / cm ³ .

  The thinned wafer after oxygen concentration reduction (referred to as oxygen concentration reduced wafer) thus completed can be provided as a device forming wafer as it is. When providing an oxygen concentration reduced wafer alone to a user, if the original wafer is not mirror-polished, it is mirror-polished later. If the original wafer is mirror-finished with mirror polish, the back side is ground.

  The oxygen concentration-reduced wafer has a very thin device formation region, and may be cracked or chipped during the device formation process. Therefore, it can be further processed and provided according to the application of the device to be formed.

  For example, it is a bonded wafer in which an ordinary silicon wafer is bonded to an oxygen concentration reduced wafer.

  FIG. 3 is a cross-sectional view showing an example of a bonded wafer.

When the bonded wafer is thinned by providing the ring-shaped convex portion 2 when the oxygen concentration reduced wafer 10 is manufactured as shown in FIG. 3A, as shown in FIG. The silicon wafer 13 is directly bonded to the surface 12 where the portion 2 is not present. The silicon wafer 13 to be bonded here may be a normal wafer for manufacturing a semiconductor device, for example, a thickness of 300 to 1000 μm, which may be a standard thickness along with the diameter of the wafer, or a wafer that is thinned as necessary. It may be. The oxygen concentration remains as a normal wafer for manufacturing semiconductor devices. That is, there are about 7 to 8 × 10 ¹⁷ atoms / cm ³ . In the case of a high-resistance wafer, the resistivity is 0.9 to 100 mΩcm for the bonded wafer.

  Bonding can be realized by direct bonding of generally known silicon wafers. For example, it can be performed as follows. First, RCA cleaning is performed to remove deposits on the wafer surface. However, in this cleaning with dilute hydrofluoric acid, ozone water is added to make the silicon wafer surface hydrophilic. After drying, both silicon wafers are bonded together without pressure, and immediately heat-treated at 900-1100 ° C. for about 1 hour in a nitrogen atmosphere.

  After bonding, as shown in FIG. 3C, the surface 11 on the side where the ring-shaped convex portion 2 is provided is polished and mirror-polished to remove the ring-shaped convex portion 2, and the surface 11 is mirror-finished. . The ring-shaped convex portion 2 may be removed by polishing and removing the entire surface 11 on the side where the ring-shaped convex portion 2 is present, but after bonding using a bevel processing technique in a normal wafer manufacturing process. The ring-shaped convex portion 2 may be removed from the periphery of the wafer (in this case, mirror polishing is performed after the bevel processing step).

As a result, the bonded wafer 20 having the defect-free (DZ) silicon layer 21 having an oxygen concentration of 4.5 × 10 ¹⁷ atoms / cm ³ or less and a thickness of 50 to 200 μm is obtained.

  When such a bonded wafer 20 is used, a wafer having a gettering layer with mechanical damage formed on the surface to be bonded is used as a base wafer for manufacturing the oxygen concentration reduced wafer 10. Thus, a bonded substrate having a gettering layer (IG) at the bonding interface can be obtained. In this case, a thinned wafer is obtained by grinding from the surface side where the gettering layer is not formed. Then, a support wafer is bonded to the gettering layer side during bonding.

  Even when the ring-shaped convex portion 2 is not formed when the oxygen concentration reduced wafer 10 is manufactured, a bonded wafer can be formed in the same manner. When the ring-shaped convex part is not formed, as the original silicon wafer, when a mirror-finished wafer is used, grinding for thinning is performed from the back side (side that is not mirror-finished), The ground surface is mirror-polished and both surfaces are mirror-finished. The bonding may be performed by bonding a support wafer to either one of the surfaces. In this way, mirror polishing after pasting becomes unnecessary.

  Sample silicon wafers with different thicknesses were prepared and annealed at 450 ° C. as a heat treatment corresponding to the device process. The oxygen concentration of each wafer was confirmed, and the number of BMDs and the resistivity of the 450 ° C. heat treatment were Changes were measured.

(Sample creation)
The original silicon wafer to be processed into a sample wafer has a diameter of 8 inches (200 mm), a thickness of 725 μm, a p-type conductivity, a resistivity of about 10 Ωcm, and an average oxygen concentration (see oxygen concentration measurement described later) 8.0 × 10 ¹⁷ atoms. Pieces / cm ³ , main surface mirror finish.

  This silicon wafer was ground from the back side (the surface opposite to the main surface). The grinding method was performed in two stages, rough cutting and finishing. In rough cutting, 80% of the total amount for grinding to a desired thickness was ground, and the rest was finished. # 400 was used for roughing and # 8000 was used for finishing, both of which had a concentration of 80 or more, and grinding was performed with a register bond type diamond wheel.

  In addition, the ring-shaped convex part was not formed, and the whole wafer was ground so as to have a uniform thickness with an error of about ± 2 μm.

  The thickness of each sample wafer is 100 μm in Example 1, 150 μm in Example 2, 200 μm in Example 3, and 300 μm in Comparative Example 1.

  The sample wafers of Examples 1 to 3 and Comparative Example 1 were annealed. In the annealing, the inside of the annealing furnace is purged with argon (always in an argon atmosphere during annealing), each sample wafer is charged at 700 ° C. in the annealing furnace, and ramped up at a rate of 700 ° C. to 5 ° C./min. The temperature was maintained at 1100 ° C. for 60 hours. Thereafter, the temperature was lowered at a rate of 3 ° C./min until 700 ° C., and the furnace temperature reached 700 ° C. Then, the sample wafer was taken out of the annealing furnace and left at room temperature.

  At the time of annealing, each sample wafer was annealed by placing it on a SiC dish whose surface (surface on which the wafer is placed) has a chevron shape.

(Oxygen concentration measurement)
The oxygen concentrations of the sample wafers of Examples 1 to 3 and Comparative Example 1 were measured.

  The measurement of the oxygen concentration was performed by Fourier transform infrared spectroscopy (FTIR: Fourier Transform Infrared Spectroscopy). Three points of the center, radius / 2, and outer peripheral position of each sample were measured, and the average was used as a representative value. This method measures only the average oxygen concentration inside each sample wafer, and doubles the sum of oxygen concentrations from the surface to the thickness center shown in FIG. 4 to divide by the thickness (average value). Equivalent to.

The measurement results of FTIR were 4.5 × 10 ¹⁷ atoms / cm ³ in Example ³ and 4.9 × 10 ¹⁷ atoms / cm ³ in Comparative Example 1 (actual value in FIG. 4). . In Examples 1 and 2, measurement was unstable due to the influence of thinning of the silicon substrate, and oxygen concentration could not be obtained. For this reason, the value by simulation was shown (predicted value in FIG. 4).

  FIG. 4 is a graph showing the simulation results of the oxygen concentration in the depth direction of the sample wafers of Examples 1 to 3 and Comparative Example 1.

  A simulation of the oxygen concentration in the depth (thickness) direction of the wafer will be described. Since the simulation of such oxygen concentration is a commonly performed method, the method performed in this embodiment will be briefly described here.

A one-dimensional diffusion equation when the oxygen concentration C (atomic number / cm ³ ) in the silicon substrate is given as follows.

∂C (x, t) / ∂t = D (T) ∂ 2 C (x, t) / ∂ 2 x
Here, D (T) is a diffusion constant of oxygen atoms depending on the annealing temperature T and is obtained by the following equation.

D (T) = 0.13exp [-2.94 × 10 ⁴ / (273 + T)]
The above equation can be simulated by the explicit method, and the following calculation formula is used.

C (x _j , t _{n + 1} ) = C (x _j , t _n ) + D (T) (Δt / Δx ² ) [C (x _{j + 1} , tn) −2C (x _j , t _n ) + C (x _j−1) , T _n )]
When the surface of the silicon substrate having the initial oxygen concentration Oi is x = 0 and the substrate center direction is the positive direction, the initial condition at this time is C (x, 0) = Oi at time t = 0 and x = 0. Let C (0, t) = 0. Δt and Δx can be arbitrarily set. In this simulation, Δt = 1200 (seconds), and Δx is a value obtained by dividing the distance to the center of the silicon substrate by 10 as shown in the simulation result of FIG.

  The FTIR result and the average oxygen concentration obtained from the simulation are almost the same, and the simulation result represents the oxygen concentration distribution in the actual depth direction of the sample wafers of Examples 1 to 3 and Comparative Example 1. Recognize.

  And as shown in FIG. 4, as for Example 1-3 and the comparative example 1 of thickness 100-300 micrometers which annealed, the direction where the depth is shallow has a low oxygen concentration. Therefore, it can be seen that the oxygen in the wafer can be reduced by annealing after reducing the thickness of the wafer.

(BMD measurement)
Using Example 3 (thickness: 200 μm, with annealing), the wafer surface was cleaved so that a cross-section passing through the approximate center was obtained, and the number of BMDs on the cleaved surface was measured. The measurement positions are approximately the center position of the wafer, a half radius (radius / 2) position, and an outer peripheral position (position 10 mm from the edge).

  The number of BMDs is automatically measured by imaging the cleavage plane with BMD analyzer MO-4 made by Mitsui Kinzoku Co., Ltd., and converting the total number of oxygen precipitates projected in the obtained visual field area per unit volume. The number of BMDs is calculated.

  FIG. 5 is a schematic diagram showing the occurrence of BMD copied from the image photograph of the BMD analyzer MO-4 on the cleaved surface of the sample wafer of Example 3.

BMD number is, 1.7 × 10 ⁷ cells at the center position / cm ^3, 4.2 × 10 ⁶ cells at the position of the radius of the half / cm ^3, be 4.2 × 10 ⁶ cells / cm ³ at the outer peripheral position The average value was 8.5 × 10 ⁶ pieces / cm ³ . In addition, as shown in FIG. 5, BMD could not be confirmed within about 50 μm from the wafer surface.

For reference, the oxygen concentration was also measured at each of these positions. The measurement method is the same as the measurement of the oxygen concentration described above. In the sample wafer of Example 3, the average oxygen concentration before the annealing treatment described above was 8.0 × 10 ¹⁷ atoms / cm ³ at the center position, and 8.2 × 10 ¹⁷ atoms / cm ³ at the half radius position. The outer peripheral position was 7.8 × 10 ¹⁷ atoms / cm ³ , and the average of three locations was 8.0 × 10 ¹⁷ atoms / cm ³ .

On the other hand, the average oxygen concentration of the sample wafer of Example 3 after the annealing treatment is 4.8 × 10 ¹⁷ atoms / cm ³ at the center position and 4.5 × 10 ¹⁷ atoms / cm ³ at the half radius position. The outer peripheral position was 4.1 × 10 ¹⁷ atoms / cm ³ , and the average of three locations was 4.5 × 10 ¹⁷ atoms / cm ³ . From this result, it can be seen that in Example 3, the oxygen concentration was uniformly reduced over the entire wafer surface.

  Thus, it was found that the defect-free layer (DZ) can be formed by reducing the number of BMDs by annealing the wafer having a thickness of 200 μm. In addition, since BMD is generated due to oxygen precipitation nuclei in the silicon wafer, if the measurement result of the oxygen concentration is combined, the oxygen concentration is reduced by annealing after processing to a thickness of less than 300 μm. Even in a reduced wafer, it is estimated that the occurrence of BMD is less than that in a wafer not subjected to such processing. Therefore, it can be seen that the oxygen concentration-reduced wafer annealed after being processed to a thickness of less than 300 μm can be provided as a defect-free layer wafer by itself.

(Resistivity measurement)
One sample wafer of each of Examples 1 to 3 and Comparative Example 1 (sample wafer after annealing) was subjected to a heating acceleration test at 450 ° C. for 48 hours, and the 0th hour (before heating) and 4th hour ( 4 hrs), 24 hours (24 hrs), and 48 hours (48 hrs) of resistivity were measured, and the heat treatment time dependency of the substrate resistivity was evaluated. The results are shown in Table 1. In Table 1, the value of resistivity is the resistivity before 450 ° C. heat treatment (elapsed 0 hours). The resistivity after the wafer was annealed at 450 ° C. for each time in Table 1 was measured. The ratio of change relative to the resistivity before heat treatment was calculated and expressed as a percentage.

  The measurement position of the resistivity was measured at the center position of each sample in the wafer surface, the half radius (radius / 2) position, and the outer peripheral position (position 10 mm from the edge).

  Before the first 450 ° C heat treatment, the thickness of each sample at the resistivity measurement position is measured with a contact-type thickness meter, and the measured thickness is used before and after each 450 ° C heat treatment. The resistivity was measured by the probe method.

  This evaluation is to evaluate the influence of the heat treatment corresponding to the heat treatment that may be added to the present Examples 2 and 3 and Comparative Example 1 in the device manufacturing process. Evaluation by low-temperature heat treatment similar to such device manufacturing process evaluates how much oxygen donors are generated and resistance changes due to low-temperature (around 450 ° C.) heat treatment that may be performed during the device manufacturing process. Is. Since the oxygen donor behaves as a donor impurity (= n-type impurity), when it occurs, the resistance of the wafer is changed. This control is particularly important for power devices and the like because the resistivity of the substrate directly affects the breakdown voltage characteristics of the device. For this reason, it is necessary to evaluate the generation of oxygen donors by measuring the resistivity of the wafer after long-time heat treatment at a low temperature.

Further, as Comparative Example 2, the wafer (diameter 8 inches (200 mm), thickness 725 μm, conductivity type p-type, resistivity 10 Ωcm, average oxygen concentration 8.0 × 10 ¹⁷ atoms / cm ³ as the basis of the example) The main surface mirror finished) was subjected to normal donor killer treatment (inert gas atmosphere, annealing at 650 ° C. for 20 minutes), followed by heat treatment at 450 ° C. in the same manner as above to measure the resistivity. The results are shown in Table 2.

As shown in Table 1, in Example 2 (thickness 150 μm), the resistivity hardly changed, and the resistivity change rate was 0% (less than 0.5%) even after the heat treatment for 48 hours. Even in the case of Example 3 (thickness 200 μm), the change in resistivity could be suppressed within 10%. This indicates that the oxygen donor increment can be suppressed to about 1.5 × 10 ¹⁴ atoms / cm ³ or less.

  On the other hand, in Comparative Example 1 (thickness 300 μm, with annealing), the resistivity has increased by about 16% after 4 hours. The reason for this is that oxygen does not escape at a thickness of 300 μm, so that part of the oxygen in the wafer becomes an oxygen donor during the 450 ° C. heat treatment, which works to cancel the acceptor of the P-type wafer and increase the wafer resistance. by. In this case, when the annealing is performed at 450 ° C. for 48 hours, the resistivity greatly changes with an increase of 365%. Therefore, this wafer cannot be used for device manufacturing involving such a long-time heat treatment.

  Moreover, it can be seen from the results of Table 2 that the resistivity value is greatly changed even in Comparative Example 2 (thickness: 725 μm). The resistivity of this wafer is adjusted with p-type boron. For this reason, when oxygen donors are generated, while the initial donors are small (while the concentration is lower than that of the initial p-type boron), the resistivity changes in the direction of increasing, and when the donor concentration further increases and reverses to n-type, this time oxygen Resistance decreases with the amount of donors generated. The results in Table 2 are a good representation of this.

  From the above results, the resistivity does not change even if high temperature annealing is performed after thin processing. Therefore, when a silicon single crystal body is formed by the Czochralski method as an original silicon wafer, if a silicon single crystal body with high resistance is formed, it can be used as it is and has high resistance and no defects. A silicon wafer can be provided. In particular, it can be provided as a silicon wafer suitable for power devices that require high resistance, such as power MOSFETs, IGBTs, and the like.

  From the results of the above examples, it can be seen that the wafer alone can be provided as a defect-free layer wafer by annealing after processing to a thickness of 200 μm or less.

  According to the embodiments and examples described above, a silicon wafer having a defect-free layer can be provided as a silicon wafer alone. In addition, it is possible to provide a wafer suitable for power device applications in which the resistance value hardly changes even by heat treatment during the device manufacturing process. In addition, since the original silicon wafer is cut from a silicon single crystal produced by the Chocrasky method, defect-free silicon wafers with various diameters from small to large diameters (compared with FZ method) And can be made at low cost.

  Although the embodiments and examples of the present invention have been described above, the present invention is not limited to these embodiments and examples. For example, in the above-described embodiments and examples, a disk-shaped silicon wafer has been described as an example. However, the silicon substrate of the present invention is not limited to a disk-shaped silicon wafer, and any substrate using a substrate cut from a silicon single crystal produced by the Chocrasky method, for example, a rectangular plate shape, The present invention can also be applied to a silicon substrate having other shapes such as an octagonal plate shape obtained by obliquely cutting four corners of a quadrangle.

  In addition to a high-resistance substrate, a silicon substrate as a base is selected to have a resistivity suitable for the device application to be formed, so that any silicon substrate having any resistivity can be used. Alternatively, a silicon substrate having a defect-free layer can be obtained.

  In addition, it goes without saying that the present invention can be implemented in various modifications within the scope defined by the claims.

1 wafer,
2 ring-shaped convex parts,
13, 41 silicon wafer,
10 Oxygen concentration reduced wafer,
20 bonded wafers,
21 Defect-free (DZ) silicon layer.

Claims (2)

The initial oxygen concentration Oi (atomic number / cm ³ ) of the silicon substrate cut out from the silicon single crystal produced by the Czochralski method is 5.0 × 10 ^{17 to} 9.0 × 10 ¹⁷ atomic number / cm ³ . and step (a) to working thickness Tsi of at least the device forming region portion of a said silicon substrate (c m) to ^{50 × 10 -4 ~200 × 10 -4} c m,
The ^{50 × 10 -4 ~200 × 10 -4} c m in processed silicon substrate annealing temperature T (° C.), annealing time t (seconds), and the silicon substrate initial oxygen concentration Oi (atoms pieces / cm ³⁾ When the following equations (1), (2)
t = f (Oi) ² (Tsi / 200) ² / [4D (T)] (1)
Here, D (T) in the formula (1) is a thermal diffusion coefficient (unit: cm ² / s) of oxygen atoms depending on the annealing temperature, and is given by the following formula (2).
D (T) = 0.13exp [-2.94 × 10 4 / (273 + T)] ... (2)
F (Oi) in the above formula (1) is 1.43 × 10 ⁻⁶⁹ Oi ⁴ −3.35 × 10 ⁻⁵¹ Oi ³ + 2.51 × 10 ⁻³³ Oi ² −3.99 × 10 ⁻¹⁶ Oi -83.43,
(B) annealing at a temperature T (° C.) in the range of 450 ° C. to 1250 ° C.
A method for producing a silicon substrate, comprising: Said step (a) forms a ring-shaped convex portion and the thickness of the unprocessed silicon substrate of the outer peripheral portion thickness ^{300 × 10 -4 c m~1000 × 10} -4 c m of the silicon substrate before the processing Te method of manufacturing a silicon substrate according to claim 1, wherein processing the portion serving as the device forming region on the inner side in the thickness ^{50 × 10 -4 ~200 × 10 -4} c m.