JPH0786489A - Resin-molded semiconductor device - Google Patents
Resin-molded semiconductor deviceInfo
- Publication number
- JPH0786489A JPH0786489A JP5253786A JP25378693A JPH0786489A JP H0786489 A JPH0786489 A JP H0786489A JP 5253786 A JP5253786 A JP 5253786A JP 25378693 A JP25378693 A JP 25378693A JP H0786489 A JPH0786489 A JP H0786489A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor device
- lead
- lead pieces
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、樹脂モールド型半導体
装置に関し、特に樹脂モールド内部にリードフレームに
より形成された容量部を有する樹脂モールド型半導体装
置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin mold type semiconductor device, and more particularly to a resin mold type semiconductor device having a capacitor portion formed by a lead frame inside a resin mold.
【０００２】[0002]
【従来の技術】従来この種の半導体装置を印刷配線板等
に実装し、あるシステムを構成しようとする場合、例え
ば電源回路用バイパスコンデンサ、あるいは外部整合用
容量等各種容量を使用する必要がある。その一例として
図４に示すＳＰＤＴ（SinglePole Double Throw）スイ
ッチＩＣについて説明する。ＳＰＤＴスイッチＩＣは、
ＭＥＳＦＥＴで構成されるＧａＡｓＩＣを樹脂封止した
ものであり、図４（ａ）に示すように、樹脂モールドパ
ッケージＰＫからは、入力端子ＩＮ、電源端子Ｖｓ、制
御端子Ｖｃｏｎｔ、Ｖｃｏｎｔ＊（＊は上線の代わり、
以下同じ）、出力端子ＯＵＴ１、ＯＵＴ２が導出されて
おり、通常、Ｖｓ端子を接地し、制御端子Ｖｃｏｎｔ／
Ｖｃｏｎｔ＊に０Ｖ／−５Ｖまたは−５Ｖ／０Ｖの電圧
を与えて、図４（ｃ）に示すスイッチングを行わせるも
のである。2. Description of the Related Art Conventionally, when a semiconductor device of this type is mounted on a printed wiring board or the like to construct a system, it is necessary to use various capacitors such as a bypass capacitor for a power supply circuit or a capacitor for external matching. . As an example thereof, an SPDT (Single Pole Double Throw) switch IC shown in FIG. 4 will be described. The SPDT switch IC is
A GaAs IC composed of MESFETs is resin-sealed. As shown in FIG. 4A, from the resin mold package PK, the input terminal IN, the power supply terminal Vs, the control terminals Vcont, Vcont * (* are overlined. instead of,
The same applies hereinafter), output terminals OUT1 and OUT2 are derived, and normally, the Vs terminal is grounded and the control terminal Vcont /
A voltage of 0V / -5V or -5V / 0V is applied to Vcont * to perform the switching shown in FIG. 4 (c).
【０００３】しかるに−５Ｖ等の負電圧を含む電源回路
は、システムの電源回路構成を複雑にすることが多く、
システムの小型化、簡素化を図るユーザは、図４の
（ｂ）に示すように、電源端子Ｖｓを外付けのキャパシ
タＣで直流的に接地電位からフロートさせるとともに、
Ｖｓ＝５Ｖの電位に設定し、Ｖｃｏｎｔ／Ｖｃｏｎｔ＊
を５Ｖ／０Ｖまたは０Ｖ／５Ｖの正電圧のみでスイッチ
ングさせて使用することが多い。However, a power supply circuit including a negative voltage such as -5V often complicates the system power supply circuit configuration.
As shown in FIG. 4B, a user who wants to miniaturize and simplify the system causes the power supply terminal Vs to float DC from the ground potential with an external capacitor C, and
Set to Vs = 5V potential, Vcont / Vcont *
Is often used by switching only with a positive voltage of 5V / 0V or 0V / 5V.
【０００４】上記例に限らず、キャパシタを外付け部品
としてボード上に実装することは実装密度の低下を招
く。そこで、この実装密度の低下を回避するために、樹
脂モールドパッケージ内に容量部を取り込む手法が各種
提案されている。例えば、特開昭５９−４８９４９号公
報には、図５に示すように、ダイパッド３１ａ′上に半
導体チップ３２をマウントし、半導体チップ３２とリー
ド片３１ａ〜３１ｋとの間を金属ワイヤ３４にて接続
し、リード片間にチップ型キャパシタ３７ａ〜３７ｃを
搭載し、モールド樹脂３６にて封止することが提案され
ている。また、特開昭６３−１３２４５９号公報には、
図６に示すように、半導体チップを搭載する前に、半導
体チップ実装部のリード片が２層となるようにリードフ
レームを整形し、その２層のリード片４１ａ−４１ｂ間
に誘電体層４８を介在させて容量部を形成し、しかる後
一方のリード片４１ｂ上に半導体チップ４２をマウント
し、金属ワイヤ４４にて配線することが記載されてい
る。Not limited to the above example, mounting a capacitor as an external component on a board causes a reduction in mounting density. Therefore, in order to avoid the reduction in the mounting density, various methods of incorporating the capacitance portion in the resin mold package have been proposed. For example, in JP-A-59-48949, as shown in FIG. 5, a semiconductor chip 32 is mounted on a die pad 31a ', and a metal wire 34 is provided between the semiconductor chip 32 and the lead pieces 31a to 31k. It is proposed that the chip capacitors 37a to 37c are connected between the lead pieces and mounted and then sealed with the mold resin 36. Further, JP-A-63-132459 discloses that
As shown in FIG. 6, before mounting the semiconductor chip, the lead frame is shaped so that the lead pieces of the semiconductor chip mounting portion have two layers, and the dielectric layer 48 is formed between the two-layer lead pieces 41a-41b. It is described that a capacitor portion is formed by interposing, the semiconductor chip 42 is then mounted on one of the lead pieces 41b, and wiring is performed by a metal wire 44.
【０００５】[0005]
【発明が解決しようとする課題】前述したパッケージ内
部にキャパシタを設けた従来の半導体装置においては、
特開昭５９−４８９４９号公報に記載されたものでは、
樹脂モールドパッケージ内部における実装部品点数が増
加し、モールド型半導体装置そのものの製造工程が複雑
になるという問題点があった。また、特開昭６３−１３
２４５９号公報のものでは、エッチングまたはプレス等
により形成したリードフレームをさらに整形加工し、か
つ誘電体層をリード片間に挟むことが必要とためにリー
ドフレームの製造工程が複雑になるという問題点があっ
た。したがって、従来例では、工数が多くかかり、結果
的にコストの増加を招くという不都合があった。In the conventional semiconductor device in which the capacitor is provided inside the package described above,
In the one disclosed in JP-A-59-48949,
There has been a problem that the number of mounted components inside the resin mold package increases and the manufacturing process of the mold type semiconductor device itself becomes complicated. Also, JP-A-63-13
In the case of Japanese Patent No. 2459, it is necessary to further shape the lead frame formed by etching or pressing and to sandwich the dielectric layer between the lead pieces, which complicates the manufacturing process of the lead frame. was there. Therefore, the conventional example has a disadvantage that it takes a lot of man-hours, resulting in an increase in cost.
【０００６】[0006]
【課題を解決するための手段】上記問題点を解決するた
め、本発明によれば、複数のリード片（１１ａ〜１１
ｇ；２１ａ〜２１ｆ）と、前記リード片に電極が接続さ
れた半導体チップ（１２；２２）とがモールド樹脂（１
６；２６）にて封止されたものであって、少なくとも１
対のリード片（１１ａ−１１ｂ；２１ｂ−２１ｄ、２１
ｃ−２１ｅ）はその一部分において狭い間隙を介して側
面同士が対向しており、その狭い間隙のある部分で容量
部（１５；２５ａ、２５ｂ）が形成されている樹脂モー
ルド型半導体装置が提供される。そして、好ましくは、
前記狭い間隙は前記半導体チップを封止するモールド樹
脂によって充填される。In order to solve the above problems, according to the present invention, a plurality of lead pieces (11a-11) are provided.
g; 21a to 21f) and the semiconductor chip (12; 22) having electrodes connected to the lead pieces are molded resin (1
6; 26), at least 1
Paired lead pieces (11a-11b; 21b-21d, 21
c-21e) is provided with a resin mold type semiconductor device in which the side surfaces are opposed to each other with a narrow gap in a part thereof, and the capacitor section (15; 25a, 25b) is formed in the part with the narrow gap. It And preferably,
The narrow gap is filled with a molding resin that seals the semiconductor chip.
【０００７】[0007]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。図１（ａ）は、本発明の第１の実施例を示
す平面図であり、図１（ｂ）はその断面図である（但
し、図１（ａ）では図を見やすくするためモールド樹脂
パッケージの上半分の除去された状態で示されてい
る）。同図に示されるように、本実施例の半導体装置に
は、リード片１１ａ〜１１ｇが備えられており、リード
片１１ａに設けられたダイパッド１１ａ′上には、半導
体チップ１２が、ＡｕＳｎ等のロー材１３を介してロー
付けされており、半導体チップ１２上に形成されたボン
ディングパッドとリード片１１ａ、１１ｃ〜１１ｇとの
間はＡｕ線等の金属ワイヤ１４で接続されている。Embodiments of the present invention will now be described with reference to the drawings. 1 (a) is a plan view showing a first embodiment of the present invention, and FIG. 1 (b) is a sectional view thereof (however, in FIG. 1 (a), a mold resin package is shown for the sake of clarity. (Shown in the top half removed). As shown in the figure, the semiconductor device of this embodiment is provided with lead pieces 11a to 11g, and the semiconductor chip 12 such as AuSn is formed on the die pad 11a 'provided on the lead piece 11a. It is brazed via the brazing material 13, and the bonding pad formed on the semiconductor chip 12 and the lead pieces 11a, 11c to 11g are connected by a metal wire 14 such as an Au wire.
【０００８】リード片１１ａと１１ｂとの間には容量形
成部１５が設けられている。容量形成部１５は、リード
片１１ａとリード片１１ｂとが櫛歯状のギャップ１１ｈ
を介してに対向する形で形成されており、このギャップ
１１ｈは、本実施例では幅１００μｍ、長さ３５ｍｍと
なっている。これらリード片１１ａ〜１１ｇは、厚さ
０．１５ｍｍの４５アロイを用い、エッチング法にて形
成したリードフレームのリードとして形成されたもので
ある。半導体チップ１２がマウントされ、金属ワイヤ１
４による繋線の施されたリードフレームは、樹脂モール
ド金型内において、エポキシ等のモールド樹脂１６によ
り封止される。このときモールド樹脂はギャップ１１ｈ
にも充填される。比率電率約４．５のエポキシ樹脂を用
いた場合、上記サイズのギャップにより容量形成部１５
において約３．５ｐＦの容量が形成できる。A capacitance forming portion 15 is provided between the lead pieces 11a and 11b. In the capacitance forming portion 15, the lead piece 11a and the lead piece 11b have a comb-shaped gap 11h.
The gap 11h has a width of 100 μm and a length of 35 mm in this embodiment. These lead pieces 11a to 11g are formed as leads of a lead frame formed by an etching method using 45 alloy having a thickness of 0.15 mm. The semiconductor chip 12 is mounted and the metal wire 1
The lead frame connected by the wire 4 is sealed with a mold resin 16 such as epoxy in a resin mold. At this time, the mold resin has a gap of 11h.
Is also filled. When an epoxy resin having a specific electric conductivity of about 4.5 is used, the capacity forming portion 15 is formed due to the gap having the above size.
At, a capacitance of about 3.5 pF can be formed.
【０００９】図２は、本発明の第１の実施例の樹脂モー
ルド型半導体装置を製造する際に用いられるリードフレ
ームの平面図である。このリードフレーム１１は、厚さ
０．１５ｍｍの４２アロイの平板にエッチングレジスト
を形成し、湿式エッチング法にてパターニングした後、
銀等のメッキを施して形成したものである。図２に示さ
れるように、リードフレーム１１において、リード片１
１ａ〜１１ｇは、フレーム外枠１１ｉとフレーム内枠１
１ｊに囲まれた領域内に形成されている。フレーム外枠
１１ｉには、搬送、位置決めのためにパイロットホール
１１ｋが開孔されている。このように形成されたリード
フレームに前述したように半導体チップ１２をロー付け
し、金属ワイヤ１４にて配線した後樹脂封止を行い、そ
の後余分な金属部を切断除去し、リード整形を行って本
実施例の樹脂モールド型半導体装置が完成する。FIG. 2 is a plan view of a lead frame used in manufacturing the resin mold type semiconductor device of the first embodiment of the present invention. The lead frame 11 is formed by forming an etching resist on a flat plate of 42 alloy having a thickness of 0.15 mm and patterning it by a wet etching method.
It is formed by plating silver or the like. As shown in FIG. 2, in the lead frame 11, the lead piece 1
1a to 11g are the frame outer frame 11i and the frame inner frame 1
It is formed in a region surrounded by 1j. A pilot hole 11k is formed in the frame outer frame 11i for transportation and positioning. As described above, the semiconductor chip 12 is brazed to the lead frame formed in this way, wiring is performed with the metal wires 14, resin sealing is performed, and then excess metal portions are cut and removed, and lead shaping is performed. The resin mold type semiconductor device of this embodiment is completed.
【００１０】この第１の実施例におけるの半導体チップ
の機能は、従来の技術の最初に記したＳＰＤＴスイッチ
であり、図１に示されるように、リード片１１ａは電源
端子Ｖｓとして、リード片１１ｂは接地端子ＧＮＤとし
て、リード片１１ｃは制御端子Ｖｃｏｎｔ＊として、１
１ｄは出力端子ＯＵＴ２として、リード片１１ｅは出力
端子ＯＵＴ１として、リード片１１ｆは制御端子Ｖｃｏ
ｎｔとして、リード片１１ｇは入力端子ＩＮとして用い
られている。したがって、本実施例において、電源端子
Ｖｓを＋５Ｖに設定し、制御端子Ｖｃｏｎｔ／Ｖｃｏｎ
ｔ＊に５Ｖ／０Ｖまたは０Ｖ／５Ｖを入力することによ
り、負電圧を使わないスイッチング動作で入力端子ＩＮ
に入る信号を出力端子ＯＵＴ１またはＯＵＴ２から出力
させることができる。The function of the semiconductor chip in the first embodiment is the SPDT switch described at the beginning of the prior art. As shown in FIG. 1, the lead piece 11a serves as the power supply terminal Vs and the lead piece 11b. Is a ground terminal GND and the lead piece 11c is a control terminal Vcont *.
1d is the output terminal OUT2, the lead piece 11e is the output terminal OUT1, and the lead piece 11f is the control terminal Vco.
As nt, the lead piece 11g is used as an input terminal IN. Therefore, in this embodiment, the power supply terminal Vs is set to + 5V, and the control terminal Vcont / Vcon is set.
By inputting 5V / 0V or 0V / 5V to t *, the input terminal IN can be operated by switching operation without using negative voltage.
The incoming signal can be output from the output terminal OUT1 or OUT2.
【００１１】図３（ａ）は、本発明の第２の実施例を示
す平面図であり（但し、図３（ａ）では図を見やすくす
るためモールド樹脂パッケージの上半分の除去された状
態で示されている）、図３（ｂ）はその等価回路図であ
る。同図に示されるように、本実施例の半導体装置に
は、リード片２１ａ〜２１ｆが備えられており、リード
片２１ａに設けられたダイパッド２１ａ′上には、ロー
材２３を介して半導体チップ２２がロー付けされてい
る。半導体チップ２２上に形成されたボンディングパッ
ドとリード片２１ｂ、２１ｆとの間は金属ワイヤ２４
ａ、２４ｂで接続されている。また、リード片２１ｂと
リード片２１ｃとの間は金属ワイヤ２４ｃにより接続さ
れている。FIG. 3A is a plan view showing a second embodiment of the present invention (however, in FIG. 3A, in order to make the drawing easy to see, the upper half of the mold resin package is removed. FIG. 3B is an equivalent circuit diagram thereof. As shown in the figure, the semiconductor device of this embodiment is provided with lead pieces 21a to 21f, and the semiconductor chip is provided on the die pad 21a 'provided on the lead piece 21a via the brazing material 23. 22 is brazed. A metal wire 24 is provided between the bonding pad formed on the semiconductor chip 22 and the lead pieces 21b and 21f.
They are connected by a and 24b. Further, the lead piece 21b and the lead piece 21c are connected by a metal wire 24c.
【００１２】リード片２１ｂと２１ｄとの間およびリー
ド片２１ｃと２１ｅとの間には櫛歯状ギャップをもつ容
量形成部２５ａと２５ｂが設けられている。先の実施例
の場合と同様に、半導体チップ２２はモールド樹脂２６
により封止されるが、この封止時において、上記櫛歯状
のギャップはモールド樹脂によって充填される。これに
より、各容量形成部２５ａ、２５ｂにおいてモールド樹
脂を誘電体層とするキャパシタが形成される。Capacitance forming portions 25a and 25b having a comb-shaped gap are provided between the lead pieces 21b and 21d and between the lead pieces 21c and 21e. As in the case of the previous embodiment, the semiconductor chip 22 has a mold resin 26.
The comb-shaped gap is filled with mold resin at the time of sealing. As a result, a capacitor having the mold resin as a dielectric layer is formed in each of the capacitance forming portions 25a and 25b.
【００１３】この実施例では、半導体チップ２２はＭＥ
ＳＦＥＴの形成されたＧａＡｓ半導体素子である。そし
て、図３（ａ）に示されるように、リード片２１ａ、２
１ｄおよび２１ｅは接地端子ＧＮＤとして、リード片２
１ｂは中継端子として、リード片２１ｃは入力端子ＩＮ
として、リード片２１ｆは出力端子ＯＵＴとして用いら
れている。この第２の実施例は、図３（ｂ）に示すよう
に、高周波増幅器の入力インピーダンス整合回路を、容
量形成部２５ａ、２５ｂに形成されたキャパシタと金属
ワイヤ２４ａ、２４ｃで形成されるインダクタンスにて
構成し、樹脂モールド型半導体装置内に収容したもので
ある。In this embodiment, the semiconductor chip 22 is an ME
It is a GaAs semiconductor device in which an SFET is formed. Then, as shown in FIG. 3A, the lead pieces 21a, 2
1d and 21e are used as the ground terminal GND and the lead piece 2
1b is a relay terminal, and the lead piece 21c is an input terminal IN.
As a result, the lead piece 21f is used as the output terminal OUT. In the second embodiment, as shown in FIG. 3B, the input impedance matching circuit of the high frequency amplifier is connected to the inductance formed by the capacitors formed in the capacitance forming portions 25a and 25b and the metal wires 24a and 24c. And is housed in a resin mold type semiconductor device.
【００１４】以上好ましい実施例について説明したが、
本発明はこれら実施例に限定されるされるものではな
く、特許請求の範囲に記載された本願発明の要旨内にお
いて各種の変更が可能である。例えば、実施例では、半
導体素子としてＧａＡｓによるＭＥＳＦＥＴを用いたも
のについて説明したが、これに代えシリコンの半導体素
子を用いることができる。また、半導体チップの実装手
段についても、ＴＡＢ方式等他の実装方式を採用するこ
とができる。さらに、ギャップの形状として櫛歯状に代
え波形や鋸歯状のものとすることができる。The preferred embodiment has been described above.
The present invention is not limited to these examples, and various modifications can be made within the scope of the present invention described in the claims. For example, in the embodiment, the case where the MESFET made of GaAs is used as the semiconductor element has been described, but a silicon semiconductor element can be used instead. Also, as the mounting means of the semiconductor chip, another mounting method such as the TAB method can be adopted. Further, the shape of the gap may be a wave shape or a saw tooth shape instead of the comb tooth shape.
【００１５】[0015]
【発明の効果】以上説明したように、本発明による樹脂
モールド型半導体装置は、容量を形成しようとする２つ
のリード片間に所望の容量値に応じた長さのギャップを
設けたものであり、そして容量部の誘電体として封止時
のモールド樹脂を用いるものであるので、本発明によれ
ば、従来の製造工程や従来のパッケージ構造に特別な変
更を加えることなく、パッケージ内に容量素子を形成す
ることができる。したがって、本発明によれば、従来製
法のままで、応用機器の実装密度を向上させることがで
きるとともに組み立て工数および部品点数を削減するこ
とができるため、結果的にコストダウンを図ることがで
きる。As described above, in the resin mold type semiconductor device according to the present invention, a gap having a length corresponding to a desired capacitance value is provided between two lead pieces for forming a capacitance. Further, since the mold resin at the time of encapsulation is used as the dielectric of the capacitance part, according to the present invention, the capacitance element is packaged in the package without any special modification to the conventional manufacturing process or the conventional package structure. Can be formed. Therefore, according to the present invention, the packaging density of the applied device can be improved and the number of assembling steps and the number of parts can be reduced with the conventional manufacturing method, resulting in cost reduction.
【図１】 本発明の第１の実施例の平面図と断面図。FIG. 1 is a plan view and a sectional view of a first embodiment of the present invention.
【図２】 本発明の第１の実施例に用いられるリードフ
レームの平面図。FIG. 2 is a plan view of a lead frame used in the first embodiment of the present invention.
【図３】 本発明の第２の実施例の平面図と等価回路
図。FIG. 3 is a plan view and an equivalent circuit diagram of a second embodiment of the present invention.
【図４】 第１の従来例の平面図と機能説明図。FIG. 4 is a plan view and a function explanatory view of a first conventional example.
【図５】 第２の従来例の平面図。FIG. 5 is a plan view of a second conventional example.
【図６】 第３の従来例の断面図。FIG. 6 is a sectional view of a third conventional example.
１１ リードフレーム １１ａ〜１１ｇ、２１ａ〜２１ｆ、３１ａ〜３１ｋ、４
１ａ、４１ｂ リード片 １１ｈ ギャップ １１ｉ フレーム外枠 １１ｊ フレーム内枠 １１ｋ パイロットホール １２、２２、３２、４２ 半導体チップ １３、２３ ロー材 １４、２４ａ〜２４ｃ、３４、４４ 金属ワイヤ １５、２５ａ、２５ｂ 容量形成部 １６、２６、３６ モールド樹脂 ３７ａ〜３７ｃ チップ型キャパシタ ４８ 誘電体層11 lead frames 11a to 11g, 21a to 21f, 31a to 31k, 4
1a, 41b Lead piece 11h Gap 11i Frame outer frame 11j Frame inner frame 11k Pilot hole 12, 22, 32, 42 Semiconductor chip 13, 23 Brazing material 14, 24a-24c, 34, 44 Metal wire 15, 25a, 25b Capacitance formation Part 16, 26, 36 Mold resin 37a-37c Chip type capacitor 48 Dielectric layer
Claims (5)
が接続された半導体チップとがモールド樹脂にて封止さ
れてなる樹脂モールド型半導体装置において、少なくと
も１対のリード片はその一部分において狭い間隙を介し
て側面同士が対向しており、その狭い間隙のある部分で
容量部が形成されていることを特徴とする樹脂モールド
型半導体装置。1. A resin-molded semiconductor device in which a plurality of lead pieces and a semiconductor chip having electrodes connected to the lead pieces are sealed with a molding resin, wherein at least one pair of lead pieces is partially formed. A resin mold type semiconductor device characterized in that side surfaces are opposed to each other with a narrow gap therebetween, and a capacitor portion is formed in a portion having the narrow gap.
するモールド樹脂によって充填されていることを特徴と
する請求項１記載の樹脂モールド型半導体装置。2. The resin-molded semiconductor device according to claim 1, wherein the narrow gap is filled with a molding resin that seals the semiconductor chip.
つに形成されたダイパッド上にマウントされ、半導体チ
ップ上に形成された電極が金属ワイヤによりリード片と
接続されていることを特徴とする請求項１記載の樹脂モ
ールド型半導体装置。3. The semiconductor chip is mounted on a die pad formed on one of the lead pieces, and an electrode formed on the semiconductor chip is connected to the lead piece by a metal wire. The resin mold type semiconductor device according to claim 1.
おいて互いにジグザグ状に入り組んでいることを特徴と
する請求項１記載の樹脂モールド型半導体装置。4. The resin-molded semiconductor device according to claim 1, wherein the pair of lead pieces are intertwined with each other in a zigzag shape in the narrow gap portion.
ことを特徴とする請求項１記載の樹脂モールド型半導体
装置。5. The resin-molded semiconductor device according to claim 1, wherein the narrow gap is formed in a comb shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5253786A JP2541475B2 (en) | 1993-09-16 | 1993-09-16 | Resin mold type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5253786A JP2541475B2 (en) | 1993-09-16 | 1993-09-16 | Resin mold type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0786489A true JPH0786489A (en) | 1995-03-31 |
| JP2541475B2 JP2541475B2 (en) | 1996-10-09 |
Family
ID=17256135
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5253786A Expired - Fee Related JP2541475B2 (en) | 1993-09-16 | 1993-09-16 | Resin mold type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2541475B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1168444A3 (en) * | 2000-06-30 | 2002-05-15 | Alcatel | Electronic or opto-electronic device in a package made from plastic and method of variation of the impedance of a connection wiring conductor of such a device |
| US6608375B2 (en) | 2001-04-06 | 2003-08-19 | Oki Electric Industry Co., Ltd. | Semiconductor apparatus with decoupling capacitor |
| JP2005524995A (en) * | 2002-05-09 | 2005-08-18 | メイコム インコーポレイテッド | Integrated circuit having internal impedance matching circuit |
| JP2007157877A (en) * | 2005-12-02 | 2007-06-21 | Sony Corp | Passive-element package and its manufacturing method, semiconductor module, and mounting structures of them |
| DE10334384B4 (en) * | 2003-07-28 | 2014-03-27 | Infineon Technologies Ag | chip device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02144951A (en) * | 1988-11-26 | 1990-06-04 | Mitsubishi Electric Corp | Semiconductor device |
-
1993
- 1993-09-16 JP JP5253786A patent/JP2541475B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02144951A (en) * | 1988-11-26 | 1990-06-04 | Mitsubishi Electric Corp | Semiconductor device |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1168444A3 (en) * | 2000-06-30 | 2002-05-15 | Alcatel | Electronic or opto-electronic device in a package made from plastic and method of variation of the impedance of a connection wiring conductor of such a device |
| US6608375B2 (en) | 2001-04-06 | 2003-08-19 | Oki Electric Industry Co., Ltd. | Semiconductor apparatus with decoupling capacitor |
| US6806564B2 (en) | 2001-04-06 | 2004-10-19 | Oki Electric Industry Co., Ltd. | Semiconductor apparatus with decoupling capacitor |
| US7173335B2 (en) | 2001-04-06 | 2007-02-06 | Oki Electric Industry Co., Ltd. | Semiconductor apparatus with decoupling capacitor |
| US7459765B2 (en) | 2001-04-06 | 2008-12-02 | Oki Electric Industry Co., Ltd. | Semiconductor apparatus with decoupling capacitor |
| US7714434B2 (en) | 2001-04-06 | 2010-05-11 | Oki Electric Industry Co., Ltd. | Semiconductor apparatus with decoupling capacitor |
| US8018055B2 (en) | 2001-04-06 | 2011-09-13 | Oki Electric Industry Co., Ltd. | Semiconductor apparatus with decoupling capacitor |
| JP2005524995A (en) * | 2002-05-09 | 2005-08-18 | メイコム インコーポレイテッド | Integrated circuit having internal impedance matching circuit |
| DE10334384B4 (en) * | 2003-07-28 | 2014-03-27 | Infineon Technologies Ag | chip device |
| JP2007157877A (en) * | 2005-12-02 | 2007-06-21 | Sony Corp | Passive-element package and its manufacturing method, semiconductor module, and mounting structures of them |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2541475B2 (en) | 1996-10-09 |
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