JPH0786359A - Evaluation of semiconductor layer - Google Patents

Abstract

PURPOSE:To enable a semiconductor layer to be accurately evaluated high in operating efficiency in a short time by a method wherein a semiconductor layer is evaluated by the leakage resistances of the surface and the bulk of a P-N junction without using a sample semiconductor layer large in P-N junction area. CONSTITUTION:The P-N junction resistances of a first sample semiconductor layer 101a and a second sample semiconductor layer 101b which are different from each other in area and formed in a P-type measuring wafer 101 are measured, the above measured values are used as a parallel-connected resultant resistance of a surface leakage resistance approximated through a first function wherein the peripheral length of a P-N junction serves as a variable and an inside leakage resistance approximated through a second function wherein the base area of a P-N junction serves as a variable, whereby first parameters A and b which detemine the above functions are extracted to evaluate a semiconductor layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for evaluating a semiconductor layer, and in particular, a semiconductor layer formed on a substrate made of a predetermined semiconductor material of an actual device is treated with a surface leak current flowing through a surface portion of its pn junction surface. , Pn junction bulk part,
That is, the present invention relates to a method of evaluating the ratio of the pn junction surface to the leak current of the bulk portion flowing in the portion located inside the substrate.

[0002]

2. Description of the Related Art FIG. 6 schematically shows a sectional structure of a pn junction portion of a conventional semiconductor device. In FIG. 6, reference numeral 1 denotes a p-type semiconductor substrate which constitutes a semiconductor device 200 such as a photodiode. An n-type semiconductor layer 2 serving as a light receiving portion or the like is formed on the surface portion of the n-type semiconductor substrate 1.
A pn junction surface 3 is formed between the type semiconductor layer 2 and the surrounding p-type semiconductor substrate region.

In such a PN junction surface 3, a depletion layer is formed in a region in the vicinity thereof, and in the region where the depletion layer spreads in this way, electrons generated by the incidence of light from the outside and positive electrons are generated. The holes are separated by the internal electric field and become photocurrent. Therefore, the photodiode used for optical communication,
In semiconductor devices such as solar cells and infrared detectors,
Although a pn junction is used, in any case, obtaining a pn junction with a small leak current is the most important issue in order to obtain a high-performance device.

Here, the leakage current IJ at the pn junction portion is, as shown in FIG. 6, the bulk portion 3 of the pn junction surface 3.
a, that is, a leak current (hereinafter referred to as a bulk leak current) I generated in a portion of the pn junction 3 located inside the semiconductor substrate 1
JB and the surface leak current IJS generated in the exposed surface portion 3b of the pn junction surface 3 can be roughly classified into two. Usually, since crystalline dangling bonds exist in the exposed surface portion 3b of the pn junction surface 3, the level density in the forbidden band width becomes much larger than that in the bulk portion 3a of the pn junction surface 3. Therefore, the tunnel current component and generated recombination (G
R; generation recombination) The current component is very large, and the surface leakage current IJS is the bulk leakage current IJB.
It may be larger than.

Since the surface leak current IJS and the bulk leak current IJB are different from each other in order to reduce the leak current, the leak current I of the entire pn junction surface 3 is reduced.
It is necessary to know which one of the surface leakage current IJS and the bulk portion leakage current IJB is dominant in J. Conventionally, as one of the evaluation methods for semiconductor devices, the surface leakage current IJS Bulk leak current I
There is a method of evaluating a semiconductor device based on the ratio with JB.

The evaluation method will be described below. First, the principle of this evaluation method will be described. When the semiconductor layer to be evaluated has a plane circular pn junction surface 3 with a radius r like the n-type semiconductor layer 2 shown in FIG.
The bonding area of the side surface portion 3c of the n-bonded surface 3 is the bottom surface portion 3a.
The area of the pn junction surface 3 in the bulk portion of the semiconductor substrate 1 can be approximated to the area of the bottom surface portion 3a of the semiconductor substrate 1 because the area is smaller than the junction area. In this case, the bulk leakage current IJB is proportional to the area (πr ² ) of the n-type semiconductor layer 2, and the surface leakage current IJS is proportional to the peripheral length 2πr of the n-type semiconductor layer 2. Therefore, pn Bonding surface 3
As the radius r becomes larger, the bulk leakage current IJB becomes dominant in the overall leakage current IJ of the semiconductor device, and the influence of the surface leakage current IJS becomes smaller. Therefore, the surface leakage current IJS is negligible,
By measuring the leak current IJ of the large sample semiconductor layer, the bulk leak current IUJB per unit area is measured.
Can be calculated.

As a result, by measuring the leak current IJ of a sample semiconductor layer having a magnitude enough to exert the influence of the surface leak current IJS, the leak current IJS is measured based on the measured value and the bulk part leak current per unit area. Thus, the surface leak current IJS and the bulk leak current IJB can be obtained.

Next, a specific evaluation method will be described.
First, a plurality of first n-type sample semiconductor layers 201a having a large radius ra such that the surface leak current IJS can be ignored are formed on the first p-type measurement wafer 201 (FIG. 12 (a)). Next, the leak current is measured for each sample semiconductor layer 201a of the measurement wafer 201, and the average value IJ1 of the leak currents is taken as the leak current of the first sample semiconductor layer 201a having the radius ra. Here, when CdHgTe is used as the semiconductor material, the sample semiconductor layer 201a has a pn junction surface outer diameter of 5
It is necessary to form a film having a thickness of about 00 μm. Then, the average value of the leakage current IJ1 is divided by the surface area (πra ² ) of the sample semiconductor layer to obtain the bulk leakage current IUJB per unit area.

On the other hand, a plurality of second sample semiconductor layers 202a having the same radius rb as the semiconductor layer to be evaluated are formed on the second p-type measuring wafer 202 (FIG. 12).
(b)) Similarly to the above, the leak current is measured for each sample semiconductor layer 202a, and the average value IJ2 is taken as the leak current of the second sample semiconductor layer 202a having the radius rb. Although the size of the sample semiconductor layer 202a varies depending on the semiconductor layer to be evaluated, the sample semiconductor layer 202a is formed so that the diameter of the pn junction surface is about several tens of μm. Since the second sample semiconductor layer has almost the same size as the semiconductor layer used in the actual device, the size is such that the influence of the surface leak current IJS sufficiently appears.

The bulk sample leakage current IUJB per unit area is added to the second sample semiconductor layer 202a.
By multiplying the surface area (πrb ² ) of the sample to obtain the bulk leakage current IJB2, which is the above measured leakage current IJ2.
Then, the surface leak current IJS2 of the second sample semiconductor layer 202a is obtained. As a result, the surface leak current IJS and the bulk leak current IJB can be obtained for the semiconductor layer to be evaluated, and the semiconductor layer can be evaluated.

[0011]

However, according to the conventional method for evaluating a semiconductor layer, the leak current of the first sample semiconductor layer having a large area where the surface leak current is sufficiently negligible is measured, and the bulk per unit area is measured. Leakage current IJB
After obtaining U, the leak current of a small second sample semiconductor layer of the same size as the semiconductor layer to be evaluated is measured, and the surface leak current of the semiconductor layer to be evaluated is obtained. Therefore, there is a problem that it takes time to evaluate the semiconductor layer. In particular, with respect to the first sample semiconductor layer, the size at which the surface leakage current can be sufficiently ignored differs depending on the semiconductor material. Therefore, the size of the area to be set depends on the size formed in advance. It is necessary to measure and determine the leak currents of some sample semiconductor layers, which takes time.

Further, when obtaining the leak current of the bulk portion per unit area, in order to minimize the measurement error, a plurality of first sample semiconductor layers are formed, and the leak current is calculated from the average value of the respective measured values. Therefore, for a large area such as the first sample semiconductor layer described above, the number that can be formed in one measurement wafer is small, and in some cases it is necessary to prepare a plurality of measurement wafers. There was also a problem that work efficiency was poor.

Further, a pn junction surface (sample semiconductor layer)
The larger the area, the higher the probability that a lattice defect will enter one pn junction surface, and the pinhole leakage current due to the lattice defect increases.
In the case of using the sample semiconductor layer of 1), there was a problem that the evaluation accuracy of the semiconductor layer deteriorated due to the leak current.

The present invention has been made to solve the above-mentioned problems, and the semiconductor layer can be evaluated by the leak current without using a sample semiconductor layer having a large pn junction area. An object of the present invention is to provide a semiconductor layer evaluation method capable of evaluating a semiconductor layer with good work efficiency in a short time and with high accuracy.

[0015]

A method for evaluating a semiconductor layer according to the present invention is characterized in that a surface region of a semiconductor substrate of a first conductivity type is
A step of forming a plurality of second-conductivity-type sample semiconductor layers having a size similar to that of the semiconductor layer to be evaluated and different bottom areas from each other; and between the sample semiconductor layers and the semiconductor substrate Applying a bias, and measuring the PN junction resistance of each of the sample semiconductor layers based on the leak current flowing between the two by the bias application,
The measured value of the PN junction resistance of each of the sample semiconductor layers is given by P
Combined resistance value by parallel connection of the surface leak resistance approximated by the first function having the perimeter of the N junction as a variable and the internal leak resistance approximated by the second function having the bottom area of the PN junction as the variable To extract the first parameter for determining the first function and the second parameter for determining the second function, and to extract the surface leak resistance and the second parameter derived from the first function. The semiconductor layer to be evaluated is evaluated by calculating the ratio with the internal leak resistance derived from the function.

According to the present invention, in the method for evaluating a semiconductor layer, as the second conductivity type sample semiconductor layer, two kinds of first area different bottom areas formed in a first conductivity type wafer are used.
And a second sample semiconductor layer, and a third resistance value representing the combined resistance value with the peripheral length and the bottom area of the PN junction portion as variables.
Is derived from the first and second functions, and the third function
From the simultaneous equations obtained by substituting the measured values of the peripheral length and bottom area of the first and second sample semiconductor layers and the PN junction resistance into the equation showing the function of
The parameters that determine the function of are extracted.

In the semiconductor layer evaluation method of the present invention, as the second conductivity type sample semiconductor layer, three or more kinds of sample semiconductor layers having different bottom areas formed in the first conductivity type wafer are used, and PN A third function, which represents the combined resistance value with the perimeter and the bottom area of the joint portion as variables, is derived from the first and second functions, and the total resistance of the combined resistance value derived by the third function is Under the condition that the square of the difference between the total sum of the sample semiconductor layers of all types and the measured sum of the PN junction resistances of the sample semiconductor layers of all the types is minimized, the first and second functions are calculated. The parameters to be determined are extracted.

According to the present invention, in the method of evaluating a semiconductor layer, the PN junction resistance of each sample semiconductor layer is measured.
The value of the bias applied between each of the sample semiconductor layers and the semiconductor substrate is changed to perform a plurality of bias values, and the parameters for determining the first and second functions are the plurality of measured values. Extract one corresponding to each bias value, corresponding to the plurality of bias values,
The semiconductor layer to be evaluated is evaluated from the ratio of the surface leak resistance and the internal leak resistance.

In the method for evaluating a semiconductor layer according to the present invention, the value of the reverse bias applied between the sample semiconductor layer and the semiconductor substrate when the PN junction resistance of each sample semiconductor layer is measured is defined as follows. Increase until breakdown occurs at the PN junction of each sample semiconductor layer,
The semiconductor layer to be evaluated is evaluated from the ratio of the surface leak resistance to the internal leak resistance and the breakdown voltage.

According to the present invention, in the method for evaluating a semiconductor layer, the PN junction resistance of each sample semiconductor layer is measured.
The semiconductor layer is evaluated at a plurality of different set temperatures of the semiconductor substrate, and the semiconductor layer to be evaluated is evaluated from the ratio of the surface leak resistance and the internal leak resistance at each of the set temperatures.

[0021]

According to the present invention, the PN junction resistance of various sample semiconductor layers having different bottom areas formed in the first conductivity type semiconductor region is measured, and this measured value is used as the perimeter of the PN junction portion. A surface leak resistance approximated by a first function which is a variable, and a second which is a bottom area of the PN junction part is a variable.
A first resistance that is used as a combined resistance value by parallel connection with an internal leak resistance approximated by the function
And the second parameter for determining the second function are extracted to evaluate the semiconductor layer. Therefore, the surface leak current is sufficient as the sample semiconductor layer for measuring the pn junction resistance. It is not necessary to form a sample semiconductor layer having a negligibly large area, sample semiconductor layers having different areas can be formed on the same measurement semiconductor substrate, and the pn junction resistance of various sample semiconductor layers having different sizes can be measured. Can be done at the same time.

As for the sample semiconductor layer formed on the measurement semiconductor substrate, a sample semiconductor layer close to the size of the semiconductor layer to be evaluated may be used by appropriately setting its surface area. Is easy.

When a plurality of sample semiconductor layers of each size are formed in order to minimize the measurement error, the size of the sample semiconductor layer is as small as the size of the semiconductor layer used in the actual device. Therefore, a sufficient number of sample semiconductor layers can be formed in one measurement wafer, and the pn junction resistance can be measured with good workability. Furthermore, as described above, since the size of each sample semiconductor layer is as small as the semiconductor layer used in the actual device, the number of crystal defects contained in the sample semiconductor layer is also reduced, and pinhole leakage due to crystal defects is caused. The current is also reduced, and the evaluation accuracy of the semiconductor layer can be improved.

In the present invention, two kinds of sample semiconductor layers having different bottom areas are used as the sample semiconductor layers, and the third function expressing the above-mentioned combined resistance value with the peripheral length of the PN junction and the bottom area as variables is Derived from the first and second functions, the equation showing the third function is added to the first
And the parameters for determining the first and second functions are extracted from the simultaneous equations obtained by substituting the measured values of the peripheral length and the bottom area of the second sample semiconductor layer and the PN junction resistance, so that there are two types. The semiconductor layer can be easily evaluated only by forming the sample semiconductor layer of 1.

In the present invention, three or more kinds of sample semiconductor layers having different bottom areas formed in the first conductivity type wafer are used as the sample semiconductor layers, and the peripheral length and the bottom area of the PN junction portion are used as variables. A third function representing the combined resistance value is derived from the first and second functions, and the least squares method is applied to the third function to obtain the first and second functions.
Since the parameter that determines the function of is extracted, the semiconductor layer can be evaluated more accurately.

In the present invention, the PN junction resistance of each sample semiconductor layer is measured for a plurality of bias values by changing the value of the bias applied between each sample semiconductor layer and the semiconductor substrate. As parameters for determining the first and second functions, those corresponding to each of the plurality of bias values measured above are extracted, and the evaluation of the semiconductor layer to be evaluated is performed corresponding to the plurality of bias values. Since it is performed by the ratio of the surface leak resistance and the internal leak resistance, the semiconductor layer can be widely evaluated for each value of the bias applied to the pn junction.

In the present invention, when measuring the PN junction resistance of each sample semiconductor layer, the value of the reverse bias applied between each sample semiconductor layer and the semiconductor substrate is defined as the PN value of each sample semiconductor layer. Since it increases until the breakdown occurs at the junction, the semiconductor layer can be widely evaluated not only from the surface leak resistance and internal leak resistance but also from the breakdown voltage included in it. .

In the present invention, the PN junction resistance of each of the various sample semiconductor layers is measured at a plurality of different set temperatures of the semiconductor substrate, so that it becomes possible to analyze the leak current component according to the cause thereof. Thus, the semiconductor layer can be evaluated with high accuracy.

[0029]

EXAMPLES Example 1. FIG. 1 shows the structure of a measuring wafer used in the method for evaluating a semiconductor layer according to the first embodiment of the present invention. FIG. 1 (a) is a plan view of the measuring wafer.
(b) is the Ib-Ib line sectional view, FIG.1 (c) is the Ic-
It is an Ic line sectional view. In the figure, 101 is a measurement wafer used in the semiconductor layer evaluation method of the present embodiment, and has a surface similar to the semiconductor layer 2 to be evaluated shown in FIG. A plurality of different first and second sample semiconductor layers 101a and 101b are formed, respectively. Here, the planar shape of the semiconductor layer to be evaluated is circular, and the radii of the first and second sample semiconductor layers 101a and 101b are values r1 close to the radius of the semiconductor layer 2 to be evaluated, respectively. It is r2. Further, 103a and 103b are the first and the first, respectively.
At the pn junction surface of the second sample semiconductor layer 101b, 13
Reference numeral 1 is a bottom surface portion of the pn junction surface, 132 is a surface portion of the pn junction surface, 133 is a side surface portion of the pn junction surface, and IJB is a bulk leakage current flowing through the bottom surface portion and the side surface portion of the pn junction surface. , IJS is a surface leak current flowing on the surface of the pn junction surface.

FIG. 2 shows an equivalent circuit of the leak resistance at the pn junction portion of the semiconductor layer to be evaluated shown in FIG. 6, and RJB is the bottom surface portion 31 and the side surface portion 33 of the pn junction surface 3. Bulk leakage resistance, RJS is pn junction surface 3
The surface leakage resistance of the exposed surface portion 32 is defined as the combined resistance value RJ of the bulk leakage resistance RJB and the surface leakage resistance RJS connected in parallel to each other as the leakage resistance at the pn junction of the semiconductor layer.

The depth of the pn junction surface 3 of the semiconductor layer 2 to be evaluated is about several μm, while the diameter of the junction bottom surface portion 31 of the pn junction surface 3 is several tens μm. ,
If the junction area of the bulk portion of the pn junction surface 3 is approximated to the junction area of the bottom portion 31 ignoring the junction area of the side surface portion 33 of the bulk portion, the bulk leakage resistance RJB becomes pn.
Since it is inversely proportional to the bottom area (πr ² ) of the joint surface 3, A
Is expressed as RJB = A / (πr ² ) ... (1), and the surface leak resistance RJS is inversely proportional to the peripheral length 2πr of the exposed surface portion 32 of the pn junction surface 3, so that b, A Is used as a coefficient (parameter), and RJS = bA (2πr) (2).

The leak resistance R of the entire pn junction surface 3 of the semiconductor layer 2 to be evaluated is represented by the combined resistance value of the bulk leak resistance RJB and the surface leak resistance RJS connected in parallel,

[0033]

[Equation 1]

It becomes Therefore, the bulk leak resistance RJB and the surface leak resistance RJS can be obtained for the semiconductor layer having a predetermined radius to be evaluated by obtaining the parameters A and b of the equation (3).

Next, a method of evaluating the semiconductor layer will be described. First, on the prepared p-type measurement wafer 101, the first sample semiconductor layer 101a having a radius r1 and the radius r2 are formed.
A plurality of second sample semiconductor layers 101b are formed (see FIG. 1A).

Next, the leak resistances RJ1 and RJ2 of the first and second sample semiconductor layers 101a and 101b are measured while the measurement wafer 101 is kept at a predetermined temperature.

Specifically, the first sample semiconductor layer 10
For each of 1a, a constant bias is applied to the pn junction portion, the leak current flowing through the pn junction portion is measured by this bias to obtain the leak resistance, and the average value of the leak resistances of all the sample semiconductor layers 101a is First
Measured value RJ1 of the leak resistance of the sample semiconductor layer 101a
And

Also for the second sample semiconductor layer 101b, the leak resistance is calculated for all the sample semiconductor layers 101b in the same manner as for the first sample semiconductor layer 101a, and the average thereof is measured value R of the sample semiconductor layer 101b.
J2. Then, in the above equation (3), the measured value R of the radius r1 of the first sample semiconductor layer 101a and its leak resistance is given.
Substituting J1,

[0039]

[Equation 2]

Then, the radius r2 of the second sample semiconductor layer 101b and the measured value RJ2 of its leak resistance are substituted into the above equation (3),

[0041]

[Equation 3]

Create These expressions (4) and (5)
Are solved as simultaneous equations for unknowns A and b to obtain the coefficients A and b in the above equations (4) and (5), and these are substituted into the above equations (1) and (2). , A function representing the bulk leak resistance RJB and the surface leak resistance RJS of the semiconductor layer to be evaluated is determined.

As a result, the bulk leak resistance RJB and the surface leak resistance RJS of the semiconductor layer to be evaluated are obtained from the radius r of the semiconductor layer, and thus the bulk leak resistance RJB and the surface leak resistance RJS are obtained. Can be derived and the leak resistance of the semiconductor layer can be evaluated.

As described above, in this embodiment, the PN junction resistances of the first and second sample semiconductor layers 101a and 101b formed in the p-type measuring wafer 101 and having different areas are measured, and the measured value RJ is calculated. , A surface leak resistance approximated by a first function having a perimeter of the PN junction as a variable, and PN
A first parameter A for determining the first function by using as a combined resistance value by parallel connection with an internal leak resistance approximated by a second function having a bottom area of a junction as a variable;
Since the second parameter Ab that determines the second function is extracted and the semiconductor layer is evaluated, the sample semiconductor layers 101a and 10a for measuring the pn junction resistance are obtained.
As 1b, it is not necessary to form a sample semiconductor layer having a large area where surface leak current can be sufficiently ignored, sample semiconductor layers having different areas can be formed on the same measurement semiconductor substrate, and each sample semiconductor layer 101a, 101b can be formed.
The pn junction resistance can be measured at the same time.

The size of the sample semiconductor layers 101a and 101b formed on the measurement wafer 101 does not need to be specified. Therefore, a sample semiconductor layer close to the size of the semiconductor layer to be evaluated is appropriately selected. The surface area is set and used, and the work of determining the size of the sample semiconductor layer can be omitted, so that the work of forming the sample semiconductor layer is simplified.

Further, each of the sample semiconductor layers 101a,
Since the size of 101b is as small as the size of the semiconductor layer used in the actual device, even if a plurality of sample semiconductor layers of each size are formed in order to minimize the measurement error, one measurement A sufficient number of sample semiconductor layers can be formed in the wafer, and the pn junction resistance can be measured with good workability. Furthermore, as described above, since the size of each sample semiconductor layer is as small as the semiconductor layer used in the actual device, the number of crystal defects contained in the sample semiconductor layer is also reduced, and pinhole leakage due to crystal defects is caused. The current is also reduced, and the evaluation accuracy of the semiconductor layer can be improved.

Further, as sample semiconductor layers, two kinds of sample semiconductor layers 101a and 101b having different bottom areas are used.
And the third function representing the combined resistance value with the peripheral length and the bottom area of the PN junction as variables,
Is derived from the function of
Since the first and second parameters A and b are extracted from the simultaneous equations obtained by substituting the measured values of the peripheral length and the bottom area of the second and second sample semiconductor layers and the PN junction resistance, there are two types. The semiconductor layer can be easily evaluated only by forming the sample semiconductor layer.

In the above embodiment, the parameter of the equation (1) is A and the parameter of the equation (2) is A and b. However, this is the parameter of the equation (1) and the parameter of the equation (2), respectively. AJ and RJB = A / (πr ² ) ... (6) RJS = B / (2πr) (7), respectively. In this case, the same effect as that of the first embodiment can be obtained.

By the way, in this embodiment, the coefficients A and b of the above equation (3) are set to the two sample semiconductor layers 101a and 101a.
Since it is determined by the measured value of the leak resistance of 01b,
When the leak resistance of the semiconductor layer having a predetermined radius is calculated by the equation (3) in which the coefficient is thus determined, the error between the actual measurement value and the calculation value may be large.

For example, FIG. 3 (a) shows an example of a measured value of the leak resistance corresponding to the radius of the pn junction in the circular sample semiconductor layer by a table, and FIG. 3 (b) shows the above semiconductor layer. And the graph of the relationship between the calculated value of the leak resistance of the semiconductor layer obtained from the above formulas (1) to (3), and the relationship between the junction radius and the measured value of the leak resistance in the above table. Shows the points. In this case, as shown in FIG. 3 (b), semiconductors of various radii can be obtained by using the above equation (3) in which the coefficients A and b are determined from the measured values of the junction radius and the leak resistance at the two points a and b. When the leak resistance of a layer is obtained, the error between the calculated value and the measured value of the leak resistance at point C may become large.

Therefore, in order to eliminate such an error in the method of evaluating the semiconductor layer, the coefficient A of the above equation (3) is calculated by the least squares method from the measured values of three or more kinds of semiconductor layers having different junction radii. , B will be described below as a second embodiment.

Example 2. FIG. 4 shows a measuring wafer used in the method for evaluating a semiconductor layer according to the second embodiment of the present invention. In the figure, reference numeral 102 denotes a measuring wafer used in the method of the present embodiment, on the surface of which, Plural first to sixth sample semiconductor layers 102a to 102f having different radii are formed.

Next, a method of evaluating the semiconductor layer will be described. First, on the prepared p-type measurement wafer 102, first to sixth sample semiconductor layers 102a having radii r1 to r6 are formed.
Each of a plurality of layers 102 to 102f is formed (see FIG. 4).

Next, with the measurement wafer 102 kept at a predetermined temperature, the first to sixth sample semiconductor layers 1 are formed.
The leak resistances RJ1 to RJ6 are measured for 02a to 102f. The leak resistances RJ1 to RJ6 for each of the sample semiconductor layers are average values of the measured values of all sample semiconductor layers of the same size, as in the first embodiment.

Then, the radii (junction radii) r1 to r6 of the first to sixth sample semiconductor layers and the leak resistances RJ1 to RJ6 measured for the respective sample semiconductor layers are used by the least squares method (3). Determine the parameters A and b of the formula.

More specifically, the joining radii r1 to r6 will be described below.
If any one of them is defined as ri and any one of the leak resistances RJ1 to RJ6 is defined as Ri, the square of the difference between both sides of the above equation (3) is

[0057]

[Equation 4]

And the denominator of the above equation (8) is

[0059]

[Equation 5]

If we put, the above equation (8) becomes

[0061]

[Equation 6]

It becomes Then, when the sum of fi (A, b) for each joining radius ri is differentiated with respect to A and b, respectively,

[0063]

[Equation 7]

[0064]

[Equation 8]

It becomes When the right side of the equations (11) and (12) is set to 0, the following equations (13) and (14) are obtained.

[0066]

[Equation 9]

[0067]

[Equation 10]

When the above equation (13) is modified with respect to A,

[0069]

[Equation 11]

Substituting equation (15) into equation (14) and transforming it,

[0071]

[Equation 12]

It becomes Substituting the measured leak resistances RJ1 to RJ6 of each semiconductor layer and the radii r1 to r6 of each semiconductor layer into the equation (16), the right side and the left side of the equation (16) are made equal to each other. B by selecting a value
The value of can be derived.

Next, the value of A can be obtained by substituting the derived b into the above equation (15). In addition,
Here, the number n of sample semiconductor layers having different junction radii is 6
However, as the number n of the sample semiconductor layers increases, A,
The value of b can be derived very accurately.

In this embodiment, as the sample semiconductor layers, six kinds of sample semiconductor layers 102a to 102f formed in the measurement wafer and having different bottom areas are used, and the peripheral length and the bottom area of the PN junction are determined. A third function of the equation (3) representing the combined resistance value as a variable is derived from the first and second functions of the equations (1) and (2), and a third function of the equation (3) is derived. Applying the method of least squares to the function, the coefficients A and b for determining the first and second functions
Therefore, in addition to the effect of the first embodiment, the coefficients A and b can be extracted extremely accurately, and the evaluation accuracy of the semiconductor layer in the development of the actual device can be significantly improved.

Example 3. FIG. 3 is a diagram showing a measurement wafer used in a semiconductor layer evaluation method according to a third embodiment of the present invention. The evaluation method of this embodiment is the same as the semiconductor wafer evaluation method of the first embodiment. The bias resistance is changed to measure the leak resistance at the pn junction, and at this time,
The value of the reverse bias to be applied is increased until the breakdown occurs at the PN junction portion of each sample semiconductor layer, and the breakdown voltage is measured.

Therefore, the measuring wafer 103 used in the method of this embodiment is replaced by the first and second sample semiconductor layers having the plane circular shape in the first embodiment, as shown in FIG. 5 (a). A sample semiconductor layer having a rectangular planar shape is formed. That is, in such a rectangular sample semiconductor layer 103a, when a measurement bias is applied between the sample semiconductor layer and the measurement wafer as shown in FIG. This is because, as shown in the drawing, the interval between the equipotential surfaces 105a is narrower than that in the straight line portion, and the electric field is likely to be concentrated, so that the breakdown voltage is easily measured.

An evaluation method when the shape (junction shape) of the semiconductor layer to be evaluated is a rectangle will be described below. If the length of one side of the above-mentioned junction shape is r and the length of one side that does not face this side is cr (c is a constant), the junction area (bottom area of the sample semiconductor layer) is expressed as cr ² , The perimeter (perimeter of the sample semiconductor layer) is 2 (1
+ C) It is represented as r. Therefore, similarly to the first embodiment, the bulk leak resistance RJ11 and the surface leak resistance RJ12 are respectively

[0078]

[Equation 13]

[0079]

[Equation 14]

And the leakage resistance RJ10 of the pn junction.
Is

[0081]

[Equation 15]

It becomes This has the same form as the equation (3) shown in the first embodiment, and the unknowns A and b can be obtained by the same method as in the first and second embodiments. Can be evaluated.

The evaluation method of this embodiment is the same as the evaluation method of the semiconductor layer of the first embodiment, except that the PN junction resistance of each of the sample semiconductor layers is measured.
3a, 103b and the semiconductor substrate, the bias value applied between the semiconductor substrate is changed to perform a plurality of bias values. The first and second parameters A and b are set to the plurality of bias values measured. Those corresponding to each are extracted, and the semiconductor layer is evaluated from the ratio of the surface leak resistance and the internal leak resistance corresponding to the plurality of bias values.

Further, in this embodiment, when measuring the PN junction resistance of the first and second sample semiconductor layers 103a and 103b, a reverse bias applied between the sample semiconductor layers and the semiconductor substrate is applied. The value is increased until breakdown occurs at the PN junction portion of each sample semiconductor layer, and the semiconductor layer to be evaluated is evaluated from the ratio of surface leak resistance to internal leak resistance and the breakdown voltage.

As described above, in this embodiment, the PN junction resistance of each of the sample semiconductor layers is measured for a plurality of bias values by changing the value of the bias applied between each of the sample semiconductor layers and the semiconductor substrate. Then, as the first and second parameters A and b, those corresponding to each of the plurality of bias values measured above are extracted, and the semiconductor layer is evaluated corresponding to the plurality of bias values. Since it is performed by the ratio of the surface leak resistance and the internal leak resistance, the semiconductor layer can be widely evaluated for each value of the bias applied to the pn junction.

In measuring the PN junction resistance of each sample semiconductor layer, the value of the reverse bias applied between each sample semiconductor layer and the semiconductor substrate is measured at the PN junction portion of each sample semiconductor layer. Since the breakdown voltage is increased until the breakdown occurs, the semiconductor layer can be widely evaluated not only by the surface leak resistance and the internal leak resistance but also by including the breakdown voltage.

Example 4. In the semiconductor device evaluation methods according to the first to third embodiments, the leak resistance is measured with the temperature of the element (sample semiconductor layer) kept constant, but the measurement is performed by changing the temperature of the element. It may be carried out, and such a measuring method will be described below as a fourth embodiment of the present invention.

The semiconductor layer evaluation method according to the fourth embodiment is the same as the semiconductor layer evaluation method according to the first embodiment, except that the PN junction resistance of each sample semiconductor layer is measured by a plurality of wafers for measurement. Set to the temperature of
The evaluation of the semiconductor layer is performed by using the first
Is performed using the ratio of the surface leak resistance by the function of and the leak resistance of the bulk portion by the second function.

In this case, it becomes possible to analyze the leakage current component of the pn junction. That is, the leak current at the pn junction of the semiconductor layer has several components, and for example, the diffusion current component Idiff is

[0090]

[Equation 16]

Further, the Gr current component I Gr is

[0092]

[Equation 17]

It is represented by These equations (20) and (2
From 1), it can be seen that the rate of change of each current component varies depending on the temperature. Therefore, by evaluating the leak current of the pn junction while changing the temperature, it is possible to know what components each of the bulk leak current and the surface leak current is composed of.

In this embodiment, since the leak current is measured and the leak current is evaluated while changing the temperature of the semiconductor element, a more detailed analysis of the leak current can be performed. As a result, more detailed evaluation of the semiconductor layer can be performed.

In each of the above embodiments, the case where the planar shape of the sample semiconductor layer is circular or rectangular is shown, but the shape of the sample semiconductor layer is not limited to this, and the sample formed on the measurement wafer is not limited to this. The plane shape of the semiconductor layer does not need to be similar to the plane shape of the semiconductor layer to be evaluated in the actual device, as long as its bottom area is approximately the same as the semiconductor layer of the actual device, Also in this case, the same effect as that of each of the above-described embodiments can be obtained.

[0096]

As described above, according to the semiconductor layer evaluation method of the present invention, the PN junction resistance of each sample semiconductor layer formed in the first conductivity type semiconductor region and having a different area is measured, and The surface leakage resistance obtained by approximating the measured value by a first function having the perimeter of the PN junction as a variable, and PN
The first and second parameters for determining the first and second functions are used by using the combined resistance value obtained by parallel connection with the internal leak resistance approximated by the second function whose variable is the bottom area of the junction. Since the semiconductor layer is extracted and evaluated, it is not necessary to form a sample semiconductor layer having a large area where surface leak current can be sufficiently ignored as a sample semiconductor layer for measuring the pn junction resistance. The sample semiconductor layers having different areas can be formed on the same measurement semiconductor substrate, and the pn junction resistance of each sample semiconductor layer can be simultaneously measured.

As for the sample semiconductor layer to be formed on the measurement substrate, a sample semiconductor layer close to the size of the semiconductor layer to be evaluated may be used by appropriately setting the area thereof. It has the effect of being simple.

When a plurality of sample semiconductor layers having different sizes are formed in order to minimize the measurement error, the size of each sample semiconductor layer is as small as the size of the semiconductor layer used in the actual device. Therefore, a sufficient number of sample semiconductor layers can be formed in one measurement wafer, and the pn junction resistance can be measured with good workability. Furthermore, as described above, since the size of each sample semiconductor layer is as small as the semiconductor layer used in the actual device, the number of crystal defects contained in the sample semiconductor layer is also reduced, and pinhole leakage due to crystal defects is caused. The current is also reduced, and the evaluation accuracy of the semiconductor layer can be improved.

According to the present invention, two kinds of sample semiconductor layers having different bottom areas are used as the sample semiconductor layers, and the third function expressing the combined resistance value with the peripheral length and the bottom area of the PN junction portion as variables. Is derived from the first and second functions, and the first expression is added to the relational expression showing the third function.
And the parameters for determining the first and second functions are extracted from the simultaneous equations obtained by substituting the measured values of the peripheral length and the bottom area of the second sample semiconductor layer and the PN junction resistance, so that there are two types. There is an effect that the semiconductor layer can be easily evaluated only by forming the sample semiconductor layer.

According to the present invention, as the sample semiconductor layer, three or more kinds of sample semiconductor layers having different bottom areas formed in the first conductivity type wafer are used, and the peripheral length and the bottom area of the PN junction portion are varied. As a result, a third function representing the combined resistance value is derived from the first and second functions, and the least squares method is applied to the third function to determine the first and second functions. Since the parameters are extracted, there is an effect that the semiconductor layer can be evaluated more accurately.

According to the present invention, the PN junction resistance of each sample semiconductor layer is measured for a plurality of bias values while changing the value of the bias applied between each sample semiconductor layer and the semiconductor substrate. As parameters for determining the first and second functions, ones corresponding to each of the plurality of measured bias values are extracted, and the surface leak resistance and the internal leak resistance corresponding to the plurality of bias values are extracted. Since the semiconductor layer to be evaluated is evaluated based on the ratio, the semiconductor layer can be evaluated widely depending on the value of the bias applied to the pn junction.

According to the present invention, when the PN junction resistance of each sample semiconductor layer is measured, the value of the reverse bias applied between each sample semiconductor layer and the semiconductor substrate is
Since the breakdown voltage is increased until the PN junction portion of each sample semiconductor layer is generated, the semiconductor layer can be evaluated more widely than that including not only the surface leak resistance and the internal leak resistance but also the breakdown voltage. There is an effect that can be done.

Further, according to the present invention, since the PN junction resistance of each sample semiconductor layer is measured at a plurality of different set temperatures of the semiconductor substrate, it becomes possible to analyze the component of the leak current according to the cause thereof. Thus, there is an effect that the semiconductor layer can be evaluated with high accuracy.

[Brief description of drawings]

FIG. 1 is a diagram showing a structure of a measuring wafer used in a method for evaluating a semiconductor layer according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an equivalent circuit of a leak resistance used in the semiconductor layer evaluation method of the first embodiment.

FIG. 3 is a diagram for explaining a problem in the semiconductor layer evaluation method according to the first embodiment.

FIG. 4 is a diagram showing a structure of a measurement wafer used in a semiconductor layer evaluation method according to a second embodiment of the present invention.

FIG. 5 is a diagram showing a structure of a measurement wafer used in a semiconductor layer evaluation method according to a third embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a structural example of a conventional semiconductor device.

FIG. 7 is a diagram showing a structure of a measurement wafer used in a conventional semiconductor layer evaluation method.

[Explanation of symbols]

 1 p-type semiconductor substrate 2 n-type semiconductor region 3, 103a pn junction surface 31, 131 pn junction surface bottom portion 32, 132 pn junction surface exposed portion 33, 133 pn junction surface side portion 101, 102 measurement wafer 101a, 103a No. 1 sample semiconductor layer 101b, 103b Second sample semiconductor layer 102a to 102f First to sixth sample semiconductor layer 105 pn junction surface corner portion 105a Equipotential surface 200 Semiconductor device IJ pn junction leakage current IJS surface leakage current IJB bulk Leakage current RJ pn junction leakage resistance RJS surface leakage resistance RJB bulk leakage resistance

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] October 28, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0004

[Correction method] Change

[Correction content]

Here, the leakage current IJ at the pn junction portion is, as shown in FIG. 6, the bulk portion 3 of the pn junction surface 3.
1 , that is, a leak current (hereinafter referred to as a bulk leak current) I generated in a portion of the pn junction 3 located inside the semiconductor substrate 1
And JB, can be divided into two surface leakage current IJS generated by the surface-exposed portion 3 2 of the pn junction plane 3. Normally, the exposed surface 3 2 of the pn junction plane 3, the number of dangling bonds of the crystal is present, as compared to the bulk portion 3 1 of the pn junction plane 3, so many state density in the forbidden band width Therefore, the tunnel current component and generated recombination (G
R; generation recombination) The current component is very large, and the surface leakage current IJS is the bulk leakage current IJB.
It may be larger than.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction content]

The evaluation method will be described below. First, the principle of this evaluation method will be described. When the semiconductor layer to be evaluated has a plane circular pn junction surface 3 with a radius r like the n-type semiconductor layer 2 shown in FIG.
The bonding area of the side surface portion 3 3 of the n-bonding surface 3 is the bottom surface portion 3 1
Since small compared to the bonding area, the area of the pn junction plane 3 in the bulk portion of the semiconductor substrate 1 can be approximated by the area of the bottom portion 3 1. In this case, the bulk leakage current IJB is proportional to the area (πr ² ) of the n-type semiconductor layer 2, and the surface leakage current IJS is proportional to the peripheral length 2πr of the n-type semiconductor layer 2. Therefore, pn Bonding surface 3
As the radius r becomes larger, the bulk leakage current IJB becomes dominant in the overall leakage current IJ of the semiconductor device, and the influence of the surface leakage current IJS becomes smaller. Therefore, the surface leakage current IJS is negligible,
By measuring the leak current IJ of the large sample semiconductor layer, the bulk leak current IUJB per unit area is measured.
Can be calculated.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction content]

Next, a specific evaluation method will be described.
First, a plurality of first n-type sample semiconductor layers 201a having a large radius ra such that the surface leakage current IJS can be ignored are formed on the first p-type measurement wafer 201 (FIG. 7 (a)). Next, the leak current of each sample semiconductor layer 201a of the measurement wafer 201 is measured,
Let the average value IJ1 of the leak current be the leak current of the first sample semiconductor layer 201a having the radius ra. Here, when CdHgTe is used as the semiconductor material, the sample semiconductor layer 201a has a pn junction surface outer diameter of 500.
It is necessary to form a film having a size of about μm. Then, the average value of the leakage current IJ1 is divided by the surface area (πra ² ) of the sample semiconductor layer to obtain the bulk leakage current IUJB per unit area.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0031

[Correction method] Change

[Correction content]

The depth of the pn junction surface 3 of the semiconductor layer 2 to be evaluated is about several μm, while the diameter of the junction bottom surface portion 31 of the pn junction surface 3 is several tens μm. ,
If the junction area of the bulk portion of the pn junction surface 3 is approximated to the junction area of the bottom portion 31 ignoring the junction area of the side surface portion 33 of the bulk portion, the bulk leakage resistance RJB becomes pn.
Since it is inversely proportional to the bottom area (πr ² ) of the joint surface 3, A
Is expressed as RJB = A / (πr ² ) ... (1), and the surface leak resistance RJS is inversely proportional to the peripheral length 2πr of the exposed surface portion 32 of the pn junction surface 3, so that b, A Is used as a coefficient (parameter), and RJS = bA / (2πr) (2).

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0075

[Correction method] Change

[Correction content]

Example 3. FIG. 5 is a diagram showing a measurement wafer used in the semiconductor layer evaluation method according to the third embodiment of the present invention. The evaluation method of this embodiment is the same as that of the semiconductor layer evaluation method of the first embodiment. The bias resistance is changed to measure the leak resistance at the pn junction, and at this time,
The value of the reverse bias to be applied is increased until the breakdown occurs at the PN junction portion of each sample semiconductor layer, and the breakdown voltage is measured.

Claims (6)

[Claims] 1. A surface region of a semiconductor substrate of the first conductivity type,
A step of forming a plurality of second-conductivity-type sample semiconductor layers having a size similar to that of the semiconductor layer to be evaluated and different bottom areas from each other; and between the sample semiconductor layers and the semiconductor substrate A bias is applied, and based on the leak current flowing between the two due to the bias application, the PN of each sample semiconductor layer is
A step of measuring a leak resistance at the junction portion, and a step of setting a measured value of the leak resistance at the PN junction portion of each of the sample semiconductor layers as a variable with the peripheral length of the PN junction portion
The first function is determined by using as a combined resistance value obtained by parallel connection of the surface leak resistance approximated by the function of and the bulk leak resistance approximated by the second function in which the bottom area of the PN junction is used as a variable. For extracting the first parameter and the second parameter for determining the second function, and for the semiconductor layer having various bottom areas to be evaluated, the surface leak resistance by the first function, Deriving an internal leak resistance by a second function, calculating a ratio of surface leak resistance to bulk leak resistance in the measured leak resistance, and evaluating the semiconductor layer. Evaluation method of semiconductor layer. 2. The method for evaluating a semiconductor layer according to claim 1, wherein the sample semiconductor layer of the second conductivity type has two types of first and second different bottom areas formed in a wafer of the first conductivity type. Using the sample semiconductor layer of, the third function representing the combined resistance value with the perimeter and the bottom area of the PN junction portion as variables is derived from the first and second functions, and the relationship showing the third function is shown. Where the perimeter and bottom area of the first and second sample semiconductor layers, and PN
From the simultaneous equations obtained by substituting the measured values of the junction resistance,
A method for evaluating a semiconductor layer, comprising extracting a parameter for determining the first and second functions. 3. The method for evaluating a semiconductor layer according to claim 1, wherein as the second conductivity type sample semiconductor layer, three or more kinds of sample semiconductor layers formed in a first conductivity type wafer and having different bottom areas are used. Using the perimeter of the PN junction and the bottom area as variables, a third function expressing the above-mentioned combined resistance value is derived from the above-mentioned first and second functions, and the combined resistance value derived by the above-mentioned third function is calculated. , The sum of the above-mentioned sample semiconductor layers of all types,
Under the condition that the square of the difference between the measured value of the PN junction resistance and the sum of the above-mentioned sample semiconductor layers of all types is the minimum,
A method for evaluating a semiconductor layer, comprising extracting a parameter for determining the first and second functions. 4. The method for evaluating a semiconductor layer according to claim 1, wherein the PN junction resistance of each sample semiconductor layer is measured by changing a bias value applied between each sample semiconductor layer and the semiconductor substrate. For multiple bias values,
As the parameters for determining the first and second functions, those corresponding to each of the plurality of bias values measured as described above are extracted, and the semiconductor layer to be evaluated is evaluated by the plurality of bias values. A method for evaluating a semiconductor layer, which is performed by a corresponding ratio of surface leak resistance and internal leak resistance. 5. The method for evaluating a semiconductor layer according to claim 4, wherein a value of a reverse bias applied between each sample semiconductor layer and the semiconductor substrate when measuring the PN junction resistance of each sample semiconductor layer. Is increased until breakdown occurs at the PN junction portion of each sample semiconductor layer, and the semiconductor layer to be evaluated is evaluated based on the ratio of surface leak resistance to internal leak resistance and the breakdown voltage. And a method for evaluating a semiconductor layer. 6. The method for evaluating a semiconductor layer according to claim 1, wherein the PN junction resistance of each sample semiconductor layer is measured at a plurality of different set temperatures of the semiconductor substrate, and the semiconductor layer to be evaluated is evaluated. A method for evaluating a semiconductor layer, which is performed using a ratio of the surface leak resistance and the internal leak resistance at each of the set temperatures.