JPH0784996A - Double-precision product sum arithmetic unit - Google Patents

Abstract

PURPOSE:To provide a double-precision product sum arithmetic device which performs product sum arithmetic with double precision without any overhead. CONSTITUTION:This unit is equipped with an accumulator which stores a product sum arithmetic result found by a cumulative multiplier 6, a shifter 7 which shifts the bits of the product sum arithmetic result stored in the accumulator, 1st data buses DB0 and DB1 which transfer the product sum arithmetic result stored in the accumulator to the cumulative multiplier 6 and shifter 7, a saving register R3 wherein the product sum arithmetic result stored in the accumulator is saved, and 2nd data buses DB2 and DB3 which transfer the product sum arithmetic result stored in the accumulator to the saving register R3; and a multiplicand and a multiplier stored in a multiplicand register R1 and a multiplier register R2 are multiplied by the cumulative multiplier 6, which cumulates the current multiplication result found by itself and the last product sum arithmetic result stored in the accumulator to perform the product sum arithmetic.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a double precision product-sum calculation device capable of high-speed product-sum calculation.

[0002]

2. Description of the Related Art In a conventional double-precision multiplication device, a result having a length larger than a word length of a multiplier and a multiplicand is generally generated. For example, a calculation using a multiplier having a 32-bit word length and a multiplicand. In the system, 64-bit results can be obtained. FIG. 3 shows a schematic configuration of a double-precision product-sum calculation device that executes a product-sum calculation using such a multiplication device.

In FIG. 3, reference numeral 21 is an array multiplier for performing multiplication based on the multiplicand X and multiplier Y, and 22 is a multiplier register for inputting the multiplier Y. For example, when the input multiplier Y is 32 bits, The upper 16-bit portion is stored in the multiplier upper register 22a side, and the lower 16-bit portion is stored in the multiplier lower register 22b side. Reference numeral 23 is a multiplicand register for inputting the multiplicand X. For example, when the input multiplicand X is 32 bits, the upper 16-bit part thereof is on the multiplicand upper register 23a side, and the lower 16-bit part is on the multiplicand lower register 23b side. Stored in each.

Reference numeral 24 is a first buffer for storing the upper 16 bits of the output result of the array multiplier 21, and 2
5 is a first adder for adding the output value of the first buffer 24 and a value stored in a first accumulator 26 described later, and 26 is a first adder for storing the output value of the first adder 25. Is the accumulator of.

27 is a second buffer for storing the lower 16 bits of the output result of the array multiplier 21;
Reference numeral 8 denotes a second adder for adding the output value of the second buffer 27 and the output value of the first shift device 29a or the second shift device 29b described later, and 29a denotes the first accumulator 26. A first shift device for shifting the stored value, 29b a second shift device for shifting the value of the second accumulator 30, and 30 stores the output value of the second adder 28. A second accumulator, 31 is a third buffer that stores the output value of the second accumulator 30, and 32
Is a third adder for adding the result of the product-sum operation stored in advance in the multiplication result register 33 described later and the output value of another product operation executed immediately after the product-sum operation, and 33 is a 64-bit This is a multiplication result register for storing the result of the product-sum operation consisting of lengths. The multiplication result register 33 is divided into 16-bit lengths, and the product-sum calculation up to that point represented by 16-bit length data is performed. The resulting δ, γ, β, and α (where δ, γ, β, and α are 0 or 1
It is value data. ) Is stored.

In such a configuration, between the 32-bit multiplicand X and the 32-bit multiplier Y, the upper bit portion Y _H of the multiplier Y is in the multiplier upper register 22a and the lower bit portion Y _L thereof is in the multiplier lower register 22b. At the same time, the high-order bit part X _H of the multiplicand X is input to the multiplicand high-order register 23 a, and the low-order bit part X _L thereof is input to the multiplicand low-order register 23 b.
Includes a multiplier upper register 22a and a multiplier lower register 22.
b, the bit parts of the multiplicand upper register 23a and the multiplicand lower register 23b are alternately input.

[0007]

[Equation 1]

As a result, the array multiplier 21 executes the calculation of the equation (2) based on the equation (1). That is,
Expression (1) shows eight partial products for performing double precision multiplication, and Expression (2) shows which partial products are added to obtain the multiplication result. Four
The two separate 16-bit parts are:

Least significant 16-bit part = a next least significant 16-bit part = (b + c + e) + carry-in next higher 16-bit part = (d + f + g) + carry-in most significant 16-bit part = h + carry-in It represents a carry generated by a 16-bit sum operation.

Next, a method for realizing the addition of partial products will be described with reference to FIG. 3, Expression (1), and Expression (2). The multiplication result register 33 stores 64
Δ, γ, β, and α, which are the results of the sum of products of bit lengths, are divided into 16-bit lengths and stored in advance as binary data.

First, in the first step, the array multiplier
21 is the lower bit part X of the multiplicand X _L, And under the multiplier Y
Place bit part Y_LAs a result of being input and multiplied respectively,
The lower bit part of the value multiplied by becomes the partial product a,
In addition, the upper bit portion of the same becomes a partial product b. And part
The product a is the final product of the multiplication results as shown in equation (2).
The second buffer as a partial product of the least significant 16-bit part
27, and the partial product b is stored in the first buffer 24.
Stored in.

In the second step, the partial product a stored in the second buffer 27 is stored in the second accumulator 30 via the second adder 28 and also in the first
The partial product b stored in the buffer 24 is stored in the first accumulator 26 via the first adder 25.

At the same time, the high-order bit part X _{H of} the multiplicand X and the low-order bit part Y _L of the multiplier Y are input to the array multiplier 21 and multiplied. As a result, the low-order bit part of the multiplied value is a partial product. c, and the high-order bit portion thereof is a partial product d. The partial product d is stored in the first buffer 24, and the partial product c is stored in the second buffer 27.

In the third step, the partial product a stored in the second accumulator 30 is stored in the third buffer 3
Sent to 1.

At the same time, the partial product b stored in the first accumulator 26 is shifted by 16 bits in the lower direction by the first shift device 29a and the second adder 2
8 is sent. As a result, the second adder 28
The partial product c of the second buffer 27 and the shifted partial product b
And are added, and this value (b + c) is stored in the second accumulator 30. The partial product d stored in the first buffer 24 is stored in the first accumulator 26 via the first adder 25.

[0016] Then, the lower bit portion X _L of the multiplicand X to the array multiplier 21, and the multiplier Y higher bit portion Y _H is multiplied by the inputted result of the lower bit portion partial product thereof multiplied had a value e, and the higher-order bit portion thereof is a partial product f. Then, the partial product f is stored in the first buffer 24,
The partial products e are stored in the second buffer 27, respectively.

In the fourth step, the partial product f stored in the first buffer 24 and the partial product d stored in the first accumulator 26 are stored in the first adder 25.
, The first adder 25 adds the partial product d and the partial product f, and this value (d + f) is stored in the first accumulator 26.

On the other hand, the value of the second accumulator 30 (b
+ C) is sent to the second adder 28, which causes the second adder 28 to output the value (b + c) and the second buffer 2
The partial product e of 7 is added, and this value (b + c + e) is the second
Stored in the accumulator 30.

After that, the high-order bit part X _{H of} the multiplicand X and the high-order bit part Y _H of the multiplier Y are input to the array multiplier 21 and multiplied. As a result, the low-order bit part of the multiplied value is the partial product. In addition to becoming g, the upper bit part becomes a partial product h. Then, the high-order bit portion h is stored in the first buffer 24, and the low-order bit portion g is stored in the second buffer 27.

In the fifth step, the sum (d + f) of the partial products stored in the first accumulator 26 is shifted by 16 bits in the lower direction by the first shift device 29a and the second adder is shifted. 28. Second adder 28
Adds the partial product g of the second buffer 27 and the value (d + f) shifted by the first shift device 29a, and the sum (d + f + g) of this partial product is added to the second accumulator 30.
Stored in.

The partial product a and the sum of partial products (b + c)
Since + e) indicates the final product of the multiplication result and the next lower 16-bit part of the final product as shown in Expression (2),
Each of the second accumulator 30 to the third buffer 31
Stored in. As a result, the least significant 16 bits a of the final product and the next lower bit portion (b + c + e) are stored in the third buffer 31.

On the other hand, the partial product h stored in the first buffer 24 is sent to the first accumulator 26 via the first adder 25.

In the sixth step, the sum (d + f + g) of the partial products stored in the second accumulator 30.
Is shifted by 16 bits in the upper direction by the second digit shift device 29b and stored in the third buffer 31, and
The partial product h stored in the first accumulator 26 is shifted by 16 bits in the upper direction by the first shift device 29a and stored in the second accumulator 30. Therefore, in the third buffer 31, the partial product a, the partial product sum (b + c + e), and the partial product sum (d +
f + g), and the partial product h is stored in the second accumulator 30, respectively. In the seventh step to the tenth step, which will be described later, the product sums up to that point stored in advance in the multiplication result register 33 are stored. Result of calculation δ, γ, β and α
Are added respectively.

That is, in the seventh step, the third adder 32 adds the partial product a and the least significant bit part of the result of the product-sum calculation up to that point stored in the multiplication result register 33. Then, the first product-sum operation result (α + a) is obtained and then stored in the multiplication result register 33.

Also in the eighth and ninth steps, the same operation as in the seventh step is performed, and the second product-sum operation result (β + b + c + e) and the third product-sum operation result (γ + d +)
f + g) is calculated and stored in the multiplication result register 33.
At the same time, the partial product h stored in the second accumulator 30 is sent to the third buffer 31.

Also in the final tenth step, the same operation as in the seventh step is performed, and the third adder 32 adds the partial product h and the partial product sum δ, and the fourth product-sum operation is performed. After the result (δ + h), it is stored in the multiplication result register 33,
The multiplication result register 33 stores the result (α +
a), (β + b + c + e), (γ + d + f + g), and (δ + h) will be stored.

Next, in order to perform another multiplication, the same operation as the above-mentioned first multiplication is performed, and the multiplication results are sequentially obtained.
Stored in the multiplication result register 33 while aligning digits,
The value finally stored in the multiplication result register 33 becomes the final result of the product-sum operation.

As described above, in order to execute the product-sum operation, the result of the product-sum operation up to that point is temporarily stored in the multiplication result register 33, added to the result of the next product operation, and again stored in the multiplication result register 33. Was executed by repeating the storage of.

However, when executing the above-described product-sum operation, the result of the product-sum operation up to that point stored in the multiplication result register 33 and the next multiplication result are summed, and then the multiplication result register is again added. There was an overhead problem because it had to be stored in 33.

[0030]

SUMMARY OF THE INVENTION Therefore, the present invention has been made in view of the above problems, and provides a double-precision product-sum calculation apparatus capable of executing double-precision product-sum calculation without overhead. The purpose is to provide.

[0031]

A double-precision product-sum calculation apparatus of the present invention is connected to a multiplicand register for storing a multiplicand, a multiplier register for storing a multiplier, the multiplicand register, and a multiplier register, and performs cumulative multiplication. A cumulative multiplier to be executed, an accumulator for storing the product-sum operation result obtained by the accumulator, a shifter for bit-shifting the product-sum operation result stored in the accumulator, and an accumulator stored in the accumulator. A first data bus for transferring the product-sum operation result stored in the accumulator and the shifter, a save register for storing the product-sum operation result stored in the accumulator, and a product-sum operation stored in the accumulator A second data bus for transferring the result to the save register, which is stored in the multiplicand register and the multiplier register. The multiplier and the multiplier are multiplied by the cumulative multiplier, and the current multiplication result obtained by the cumulative multiplier and the product-sum operation result stored in the accumulator up to immediately before are accumulated by the cumulative multiplier. It is characterized in that the sum of products operation is executed by accumulating at.

Further, the double-precision product-sum calculation apparatus of the present invention multiplies the multiplicand register represented by the high-order bit portion and the low-order bit portion, and the multiplicand stored in the multiplier register, and the respective bit portions of the multiplier. This is characterized in that the sum of products operation is executed.

The cumulative multiplier of the double-precision product-sum calculation apparatus of the present invention is characterized by executing signed or unsigned product-sum calculation of the multiplicand and the multiplier.

[0034]

According to the above-described double-precision product-sum calculation device, the multiplicand register, the multiplicand and the multiplier stored in the multiplier register are multiplied by the cumulative multiplier, and the current multiplication obtained by the cumulative multiplier is calculated. The result and the cumulative multiplication result up to the immediately preceding time stored in the accumulator are digit-matched and accumulated by the cumulative multiplication unit.

At this time, the above digit adjustment is performed by sending the cumulative multiplication result stored in the accumulator to the shifter.

[0036]

Embodiments of the present invention will be described with reference to FIGS. 1 and 2.

FIG. 1 is a schematic block diagram of a double precision product-sum calculation apparatus of the present invention.

In FIG. 1, R1 is a multiplicand register for storing the multiplicand X. For example, the input multiplicand X is 3
In the case of 2 bits, the upper 16-bit portion thereof is stored in the multiplicand upper register R1a side of the multiplicand register R1, and the lower 16-bit portion thereof is stored in the multiplicand lower register R1b side of the multiplicand register R1.

R2 is a multiplier register for storing the multiplier Y. For example, when the input multiplier Y is 32 bits, the upper 16-bit portion is on the multiplier upper register R2a side of the multiplier register R2 and the lower 16-bit portion. Are respectively stored in the multiplier lower register R2b side of the multiplier register R2.

R3 is a save register for storing a partial product in the multiplication, specifically, the value of the formula (1) shown in the conventional example. The save register R3 is a save register for storing the upper bit part of the partial product. It comprises R3a and a save register R3b for storing the lower bit part.

Reference numeral 4 is a first multiplexer for selecting the upper bit portion of the multiplicand upper register R1a or lower bit portion of the multiplicand lower register R1b, and 5 is the upper bit portion of the multiplier upper register R2a or the multiplier lower register R2.
a second multiplexer for selecting the lower bit part of b, 6
First multiplexer 4, or higher bit portion of the multiplicand X selected in second multiplexer 5 X _H, or lower bit portion X _L, and the multiplier Y higher bit portion Y _H of,
Alternatively, after accumulating after multiplying the lower bit parts Y _{L respectively} , 7 is a cumulative multiplier, 7 is a shifter for bit-shifting the input value by a desired digit in an upper direction or a lower direction, and 8 is a result of a product-sum operation. This register 8 is composed of an upper register 8a for storing the upper 32 bit portion of the result of the product-sum operation and a lower register 8b for storing the lower 32 bit portion.

Data bus DB0 and data bus 1
Is the cumulative multiplication result of the multiplication result register 8
And a first data bus for transferring to the shifter 7, and the data bus DB2 and the data bus 3 for transferring the cumulative multiplication result of the multiplication result register 8 to the save register R3.
It constitutes a data bus.

The operation when the sum of products operation is executed between the 32-bit multiplicand X and the 32-bit multiplier Y in such a configuration will be described. In the multiplication result register 8, the result of the 64-bit product sum operation performed up to immediately before is divided into 16-bit lengths, and the 16-bit δ and γ are stored in the upper register 8a. Further, β and α having a 16-bit length are stored in the lower register 8b.

First, in the first step, the first multiplexer 4 outputs the lower bit portion X _L of the multiplicand X and the second
The multiplexer 5 selects the lower bit part Y _L of the multiplier Y, and these values are input to the accumulating multiplier 6. The cumulative multiplier 6 performs multiplication to obtain a partial product a and a partial product b.

Here, in the lower register 8b of the multiplication result register 8, the least significant 16-bit part and the next least significant 16-bit part of the 64-bit-long cumulative multiplication result performed up to immediately before are calculated. Products α and β are stored, and these values are sent to the cumulative multiplier 6 via the data bus DB1 and added to the partial products a and b, respectively, and the partial product sums (a + α) and (β + b) ) Is calculated and then stored in the lower register 8b.

In the second step, the partial product a is given by the equation (2).
Since the final product of the multiplication result is determined as the least significant 16-bit part as shown in (4), the sum (a + α) of the partial products is sent to the lower register R3b of the save register R3 via the data bus DB2 and temporarily stored. It

On the other hand, the sum of partial products (β + b) is sent from the lower register 8b to the shifter 7 via the data bus DB0, is shifted in the lower direction by 16 bits by the shifter 7, and is aligned with the digits, and then the multiplication result register. It is stored again in 8b.

In the third step, the first multiplexer 4 selects the high-order bit part X _H of the multiplicand X and the second multiplexer 5 selects the low-order bit part Y _L of the multiplier Y, and these values are cumulatively multiplied. Input to the container 6. The cumulative multiplier 6 performs multiplication to obtain a partial product d and a partial product c.
Sum of partial products stored in lower register 8b (β +
b) is sent to the cumulative multiplier 6 via the data bus DB1, the sum of partial products (β + b + c) is obtained here, and the partial product sum γ stored in the lower register 8b is sent via the data bus DB1. Is sent to the cumulative multiplier 6, and the sum (γ + d) of the partial products is obtained here. Thereafter, the sum of partial products (β + b + c) and the sum of partial products (γ + d) are sent to the lower register 8b.

In the fourth step, the first multiplexer 4
It is a lower bit portion X _L of the multiplicand X, and the second multiplexer 5 selects the bit portion Y _H of the multiplier Y, these values are input s to the cumulative multiplier 6 respectively. Cumulative multiplier 6
Performs multiplication to obtain a partial product f and a partial product e.

Here, the sum (β + b + c) of the partial products temporarily stored in the lower register 8b is the data bus DB.
After being sent to the cumulative multiplier 6 via 1 and added with the partial product e to calculate the sum of partial products (β + b + c + e),
It is sent to the lower register 8b.

The sum of partial products (γ + d) temporarily stored in the lower register 8b is sent to the cumulative multiplier 6 and added to the partial product f to sum of partial products (γ + d + f).
Is calculated and then sent to the lower register 8b.

In the fifth step, the sum of partial products (β + b
Since + c + e) represents the next 16-bit part of the least significant 16-bit part in the multiplication result, the sum (β +
b + c + e) is sent to the save register R3a of the save register R3 via the data bus DB2 and temporarily saved.

On the other hand, the sum of partial products (γ + d + f) is sent from the lower register 8b to the shifter 7 via the data bus DB0, and the shifter 7 shifts the value in the lower direction by 16 bits to perform digit alignment and then the lower register 8b. Stored again in.

In the sixth step, the save register R3b
The sum (α + a) of the partial products stored in is the data bus D
B2 and the sum (β + b + c + e) of the partial products stored in the save register R3a are returned to the lower register 8b via the data bus DB3.

On the other hand, the sum (γ + d + f) of the partial products stored in the lower register 8b is sent from the cumulative multiplier 6 to the upper register 8a via the data bus DB0.

In the seventh step, the first multiplexer 4
Is selected as the high-order bit part X _H of the multiplicand X, and the second multiplexer 5 is selected as the high-order bit part Y _H of the multiplier Y, and these values are input to the cumulative multiplier 6. Cumulative multiplier 6
Is multiplied to obtain a partial product h and a partial product g.

Here, the sum of partial products (γ + d + f) temporarily stored in the upper register 8a is sent to the accumulating multiplier 6 and added to the partial product g to obtain the sum of partial products (γ + d).
After + f + g) is calculated, it is sent to the upper register 8a. Further, δ stored in the upper register 8a is sent to the cumulative multiplier 6, is added to the partial product h, the sum of partial products (δ + h) is calculated, and then sent to the upper register 8a.

Thus, the multiplication result register 8 sequentially stores (α + a), (β + b + c + e), from the least significant bit portion.
(Γ + d + f + g) and (δ + h) are stored.

The above is the description of the operation when one multiplication result is added to the result of the product-sum operation, but several product-sum operations can be executed by sequentially repeating the above operation.

As described above, in the product-sum calculation apparatus of the present invention, it takes only 7 steps to perform one product calculation, and the processing speed is improved in repeatedly performing the product-sum calculation. To do.

In addition, in the product-sum operation in the above-described embodiment, the multiplicand and the sign relating to the multiplier are not considered at all, but the presence or absence of the sign is indicated in the leading 1 bit of the multiplicand and the multiplier. , Signed or unsigned sum-of-products operation can be executed.

[0062]

As is clear from the above description, when accumulating the result of the product-sum operation which has been operated and the subsequent multiplication result, the multiplication result in which the result of the product-sum operation which has been operated is stored. Since the result of the sum-of-products operation which has already been operated is directly input from the register to the accumulator via the first data bus, high-speed processing becomes possible and the problem of overhead is eliminated.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a double-precision product-sum calculation apparatus of the present invention.

FIG. 2 is an operation explanatory chart according to the present invention.

FIG. 3 is a schematic configuration diagram of a double-precision product-sum calculation device that executes a product-sum calculation using a conventional multiplication device.

[Description of Codes] R1 Multiplicand register R2 Multiplier register R3 Evacuation register 4 First multiplexer 5 Second multiplexer 6 Cumulative multiplier 7 Shifter 8 Multiplication result register 8a Upper register 8b Lower register

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Akira Yoshida 2-18 Keihan Hondori, Moriguchi City, Osaka Sanyo Electric Co., Ltd.

Claims (3)

[Claims] 1. A multiplicand register that stores a multiplicand, a multiplier register that stores a multiplier, a cumulative multiplier that is coupled to the multiplicand register and the multiplier register, and that performs cumulative multiplication, and is calculated by the cumulative multiplier. Accumulator for storing the product-sum operation result, a shifter for bit-shifting the product-sum operation result stored in the accumulator, and transfer of the product-sum operation result stored in the accumulator to the accumulator and the shifter A first data bus, a save register for storing the product-sum operation result stored in the accumulator, and a second data bus for transferring the product-sum operation result stored in the accumulator to the save register. The multiplicand register and the multiplicand and multiplier stored in the multiplier register are multiplied by the cumulative multiplier. A product-sum operation is performed by accumulating, in the accumulator, the current multiplication result obtained by the accumulator and the product-sum operation result stored in the accumulator up to immediately before. A double-precision product-sum calculation device. 2. A sum-of-products operation is performed by multiplying the multiplicand register represented by the high-order bit portion and the low-order bit portion, and the multiplicand stored in the multiplier register and the respective bit portions of the multiplier. The double-precision product-sum calculation apparatus according to claim 1. 3. The double-precision product-sum calculation apparatus according to claim 1, wherein the cumulative multiplier executes signed or unsigned product-sum calculation of the multiplicand and the multiplier.