JPH0782759B2 - Sound recording / playback device - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to an acoustic recording / reproducing apparatus capable of generating an arbitrary acoustic signal by digitally recording an external sound and appropriately reading it.

[Conventional example of the invention and its problems]

A conventional electronic device with a PCM recording function, for example, a sampler, as shown in FIG. 9, is a waveform memory in which a sound input from an external sound input terminal 12 is converted into a digital signal by an A / D conversion circuit 13 under the control of a CPU 11. Recorded on 14 and played back by DMAC (Cire
DM from the waveform memory 14 to the FIFO (First in First Out) buffer 16 under the control of the ct Memory Access Controller 15
A transfer is performed, and DMA transfer is performed in the sea when the FIFO buffer 16 is empty, and the frequency corresponding to the key of the keyboard 17 is VCO18.
And output to the D / A conversion circuit 19 from the FIFO buffer 16 according to the set frequency of the VCO 18, so that the sound corresponding to the sound signal waveform recorded in the waveform memory 14 is output to the output terminal 20. Has become.

However, with this type of sampler, the DMA transfer is frequently performed, which puts a heavy load on the CPU, and when the playback is performed at a high frequency or polyphonic, the CPU does not
There was a problem that it was monopolized for MA processing and the time for other processing was lost.

In addition, when recording a certain sound, the timing of the recording start operation with respect to the rising of the sound is difficult, and there is a problem that the head part is cut off or the silent part is lengthened.

[Object of the Invention]

The present invention has been made in view of the above circumstances, and an object thereof is to provide an acoustic recording / reproducing apparatus capable of recording / reproducing at the start of recording so that the head portion is not cut.

[Main points of the invention]

The feature of the present invention is that pre-recording is executed by a pre-recording command,
When the main recording is started by the main recording command and the loop reproduction is performed, the above-mentioned portion and the main recording portion are continuously provided to obtain a sound without a break.

Example of Invention

FIG. 1 shows the overall configuration of an embodiment in which the present invention is applied to a sampler. In the figure, 31 is a CPU and a keyboard 3
The control of generating the corresponding musical tone is performed by the key operation of 2, and the recording and reproduction are controlled according to the key input of the key switch group 33. 34 is a sound source control circuit for recording / playing a musical sound, which includes a CPU 31, an address bus AB, a data path DB,
It is connected via the control bus CB, and records external sound input via the external sound input terminal 35 and the A / D conversion circuit 36 according to the instruction from the CPU 31, and the D / A conversion circuit 37 and VCA.
Play through 38 _{0 to} 38 ₃ and output terminals 39 _{0 to} 39 ₃ . In this embodiment, four-tone polyphonic sound is used, and VCA 38 _{0 to} 38 ₃
The time-division timing signals T _{0 to} T ₃ of four channels are input to and the time-division operation is performed by the channel switching circuit provided in the preceding stage of the VCA. Also, channel switching signals CH _{0 to} CH ₃ are supplied from the CPU 31 to output musical tones only to designated channels. It should be noted that φ _REC is a block for sampling an external sound, and φ _S is a waveform read clock, both of which are generated in the tone generator control circuit 34.

FIG. 2 is a diagram showing a block configuration of the sound source control circuit 34, which comprises an interface section 41, a main control section 42, an address control section 43, a waveform memory section 44, and an interpolation section 45. The interface section 41 is the address path A from the CPU 31.
B, data bus DB, control bus CB, CPU
31 The interface between the sound source control circuit 34 and the data in the sound source control circuit 34. Various control signals are sent to the internal control bus ICB.
The initial data such as the start address and pitch are sent to the main control unit 42 via the internal data bus.
It is sent to the address control unit 43 via the IDB. In addition, the waveform data is transferred to and from the waveform memory unit 44 via the RAM data bus RD. The RAM data bus RD is also a path for waveform data input from the A / D conversion circuit 36 via the gate 46, and this waveform data is sent to the interpolation section 45. The main control unit 42 is a circuit that controls the entire sound source control circuit 34. As shown in FIG. 3, the command control circuit 421 decodes a control signal sent via the internal control path ICB to perform various operations. The command is sent to the address control unit 43 and also to the internal trigger control circuit 422. This trigger control circuit 422
As will be described later in detail, is a circuit that realizes a delay trigger function for performing pre-recording and main recording so that the head portion is not cut off at the start of recording. A command is also sent from the trigger control circuit 422 to the address control unit 43,
Further, the gate open signal GAD is sent to the gate 46. Further, it has a timing control circuit 423 inside and generates various timing signals. The relationship of each timing signal is as shown in FIGS. 8 (1) to 8 (8). Furthermore,
424 is a DMA control circuit, which outputs a DMA request signal RQ via the internal control bus ICB and also a DMA permission signal AK.
It is a circuit that receives and controls the DMA. Then, the command control circuit 421 gives a signal for determining the direction of DMA and a DMA start command. The signal BS output from the command control circuit 421 is a switching signal for switching the data movement direction of the data bus when the data is being read by the CPU 31 via the internal data bus IOB.

The address control unit 43 is a circuit for designating an address of a waveform memory 441 (described later) in the waveform memory unit 44. The address is updated under the control of the main control unit 42, and when the update is completed, the END signal is sent to the main control unit 42. Output to the trigger control circuit 422 of. The address data output from the address control unit 43 has an integer part supplied to the waveform memory unit 44 and a decimal part supplied to the interpolation unit 45.

The waveform memory section 44 records the waveform data supplied from the A / D conversion circuit 36 and stores the recorded waveform data in the RAM data bus R
It is a circuit for outputting to the CPU 31 or the interpolation unit 45 via D.

The interpolation unit 45 is a circuit that performs linear interpolation on the waveform data read from the waveform memory unit 44 and outputs it to the D / A conversion circuit 37.

Next, details of the address control unit 43 are shown in FIG. In the figure, 51 is a pitch register for storing pitch data, 52 is a temporary storage register for storing the address of the waveform memory 441, 53 is an end register for storing the final value of the content update of the temporary storage register, and 54 is a repeatedly designated address. Loop start register that stores the start address of
55 is a loop end register for storing the final value of the repetitive designated address, 56 is a play flip-flop for controlling the start / stop of updating the contents of the temporary storage register 52, and 57 is a loop on for controlling the on / off of the repetitive addressing. Flip-flops, 58 are inverse flip-flops for inverting the polarity of the pitch read from the pitch register 51, and the above 51 to 58 are each composed of a four-stage shift register, and shift in synchronization with the timing signal φs. There is. That is, it has a 4-channel 4-tone polyphonic structure, and is time-divisionally driven at the timings of T ₀ , T ₁ , T ₂ , and T ₃ . Pitch data is supplied to the bit register 51 via the internal data bus IDB, and a command "PITCH" applied from the main control unit 42 is supplied.
The "WRITE" opens the gate 59 and closes the gate 61 via the inverter 60 to set the pitch data. The set pitch data circulates through the gate 61 and is input to the AND gate 63 through the exclusive OR gate 62. In the temporary storage register 52,
The address data is supplied via the internal data bus IDB, and the command “TEMP WRITE” output from the main control unit 42 is applied to the gate 65 via the AND gate 64 and to the gate 67 via the NOR gate 66. When the gate 65 is opened and the gate 67 is closed, the address data is set. The set address data is input to the adder 68, added to the pitter data input via the AND gate 63, input to the comparator 69, and returned to the temporary storage register 52 via the gate 67. . The 17 bits of the integer part are output to the waveform memory 441 as addressing data, and the 13 bits of the decimal part are output to the interpolation part 45 as interpolation data. Further, when the command "TEMP READ" is applied from the main control unit 42, the gate 70 is opened and the contents of the temporary storage register 52 are output to the internal data bus IDB. The end address data is supplied to the end register 53 via the internal data bus IDB, and the command “END WRITE” output from the main control unit 42 opens the gate 71 and closes the gate 73 via the inverter 72. The data is set. The set end address data is
The timing signal φ _S is input to the comparator 69 via the gate 75 applied via the inverter 74. Then, the comparator 69 compares the end address output from the end register 53 with the address data of the temporary storage register 52 output via the adder 68, and the address data output from the adder 68 is compared. The signal LOOP is output when is greater than or equal to. This signal LOOP is input to the AND gate 76 and is buffered in synchronization with the timing signal φ _W.
Read in 77. The output signal END of this buffer 77 is
It is sent to the main control unit 42 as an end signal and is also input to the NOR gate 78. The loop start address data is supplied to the loop start register 54 via the internal data bus IDB, and the main control unit 42
The loop start address data is set by the command "LS WRITE" output from the gate opening gate 79 and opening the gate 81 via the inverter 80. This set loop start address data normally circulates through the gate 81, and the LOOP signal opens the gate 82 through the AND gate 76 and closes the AND gate 64 through the inverter 83 and the NOR gate 66. When the gate 67 is closed via, the temporary storage register 52 is set via the gate 82. The loop end register 55 is supplied with the rape end address data via the internal data bus IDB, and the command “LE WRITE” output from the main control unit 42 opens the gate 84 and the inverter 85.
Loop end address data is set by closing gate 86 via. The set loop end address data circulates through the gate 86 and is input to the comparator 69 through the gate 87 that opens when the timing signal φ _S is applied. Therefore, the data input to the comparator 69 and compared with the temporary storage register 52 is
When the timing signal φ _S is applied, it means the contents of the loop end register 55, and when there is no timing singo φ _S , it means the contents of the end register 53. The play flip-flop 56 is set when the command “START” is input to the NOR gate 88 from the main control unit 42, and is reset when the command “STOP” or the end signal from the buffer 77 is input to the NOR gate 78. The output of this play lip flop 56 is a NOR gate 88.
And the gate is opened by inputting it to the AND gate 63. In addition, the command “ST
When output to "ATUS READ", the gate 89 is opened and the output of the play flip-flop 56 is output to the internal data bus IDB. The loop-on flip-flop 57 is set when the command “LOOP ON” is input from the main control unit 42 to the NOR gate 90, and the command “LOOP OF” is set.
It is reset when "F" is input to the NOR gate 91.
The output of this loop-on flip-flop 57 is a NOR gate
The gate is returned to 90 and input to AND gate 76 to open the gate. In the inverse flip-flop 58, the commanded “INV ON” from the main control unit 42 is NOR gate 9
Set when input to 2, command "INV OFF"
Is reset when NOR gate 93 is input. The output of this inverse flip-flop 58 is the NOR gate.
While being returned to 92, the pitch data from the pitch register 51 is inverted by being input to the exclusive OR gate 62.

FIG. 5 is a diagram showing details of the trigger control circuit 422 in the main control section 24. In the figure, 101 is a recording flip-flop, and the command “R
When "EC START" is input to the NOR gate 102, it is set in synchronization with the timing signal φ _R , and the command "REC STO
It is reset when "P" is input to the NOR gate 103.
The Q side output of this recording flip-flop 101 is NOR gate 1
It becomes the REC ON signal which is returned to 02 and is output through the NOR gate 104. The side output is NOR gate 105.
The signal is output via the REC OFF signal and is input to the NOR gate 106. On the other hand, the output of the NOR gate 103 is input to the NOR gate 105 and the NOR gate 104 via the inverter 107. The REC ON signal is input to the NAND gate 108 to which the timing signal T ₀ is input at one input end, and the REC OFF signal is the timing signals T ₀ and T
NAND gate where ₁ is input via OR gate 109
Entered in 110. 111 is a trigger flip-flop, which is set in synchronization with the timing signal φ _R when the command “REC TRIG” is input to the NOR gate 112 from the command control circuit 421, and the command “REC START” is input to the NOR gate 113. When reset. The Q side output of this trigger flip-flop 111 is NOR gate 1
12 and the timing signal T ₁
NOR gate through the AND gate 114 which is being input 1
Entered in 15. Further, the side output is input to the NOR gate 115 via the AND gate 116 to which the timing signal T ₀ is input to one input end, and the output of the NOR gate 113 is input to one input end. 1
It becomes a TRIG ON signal via 17. The output of the NOR gate 115 is input to the NOR gate 106 and the buffer 1
It is given to 18 as a read signal. This buffa 118
Is supplied with the END signal from the buffer 77 of the address control unit 43, and its output is read into the buffer 119 with the timing signal φ _R. And the output of buffer 119 is
It is input to the NOR gate 103. The TRIG ON signal output from the AND gate 117 is input to the NAND gate 121 via the NAND gate 120 to which the timing signal T ₁ is input at one input end, and the timing signal T ₀ is input to one input end. It is input to the NAND gate 123 via the supplied NAND gate 122. Above NAND gate 121
The output of the NAND gate 108 is input to the other input terminal of the NAND gate 123, the output of the NAND gate 110 is input to the other input terminal of the NAND gate 123, and the output of the NAND gate 121 is input to one input terminal from the command control circuit 421. PLAY ”is input to the address control section 43 as a START signal via the OR gate 124, and the NAND gate 123
Is output to the address control unit 43 as a STOP signal via the OR gate 125 to which the command “STOP” is input from the command control circuit 421 at one input end. On the other hand, the timing signal φ _REC is input to the NOR gate 106 to which the output of the NOR gate 115 and the output of the recording flip-flop 101 are input, which is applied to the gate 46 as its output GAD signal, and the gate is opened to open the A / D. The waveform data from the conversion circuit 36 is loaded into the RAM data bus RD.

FIG. 6 shows details of the waveform memory unit 44 and the interpolation unit 45. Of the address data output from the address control unit 43, 17 bits of the integer part are given to the waveform memory 441 via the gate 443 to which the timing signal φ _W is given via the inverter 442, and are incremented by 1 in the +1 circuit 444. Gate opened by timing signal φ _W after
It is given to the waveform memory 441 via 445. The waveform memory 441 is supplied with the read / write signal R / from the main control unit 42.

The waveform data output from the specified address of the waveform memory 441 is read into the register 451 via the RAM data bus RD in synchronization with the timing signal φ _S , and
After being read into the latch 452 in synchronization with the timing signal φ _W , it is read into the register 453 in synchronization with the timing signal φ _S. The data read into the register 451 is the subtractor 454.
Then, the data read in the register 453 is subtracted and supplied to the multiplier 455. The fractional part of the address data is given to the multiplier 455 from the address control unit 43, and the fractional part data and the data supplied from the subtractor 454 are multiplied and output to the adder 456. The output of the register 453 is supplied to the adder 456, and both are added and output to the D / A conversion circuit 37.

Next, the operation of the present embodiment configured as described above is
This will be described with reference to the drawings and FIG. FIG. 7 is a flowchart showing the recording operation. To record an external sound, first turn on the recording key of the key switch group 33 (step S ₁ ). Next, an arbitrary initial value is set. This initial value is the data that is set in advance in each register of the address control unit 43, and key data such as the bit data of the channel used, the start address data, the loop start address data, the loop end address data, the end address data, and the loop on data are the keys. Input from switch group 33 (step S ₂ ). At this time, as shown in FIG. 8 (1), the CPU 31 outputs the 16-bit data in two steps of lower 8 bits and upper 8 bits. In addition, this
The operation timing of the CPU 31 is asynchronous with the timing in the sound source control circuit 34 shown in FIGS. 8 (1) to 8 (8). Then, for example, if the pitch data of one channel is input, channel 1 designation data and pitch designation data are output following the pitch data. The output data is taken into the sound source control circuit 34 by referring to FIGS. 8 (10) to (13).
The read signals WR _{0 to} W ₃ generated by the command control circuit 421 as shown in FIG. The read signal WR ₀ causes lower 8-bit data and the higher-order 8 bit data than WR ₁ to be fetched into the internal data bus IDB via the interface unit 41, and the WR ₃ outputs a BUSY signal from the command control circuit 421 to the CPU 31. Prohibit the execution of the next instruction. Then, the output φ of this BUSY signal
It is the timing for synchronizing the CPU 31 and the sound source control circuit 34 by _R , and the command synchronization signal rises in the main control unit 42. The command from the main control 42 is output during the generation of the command synchronization signal. Then,
The command control circuit 421 of the main control unit 42 at the timing of the timing signal T ₁ command "PITCH
WRITE ”is output. On the other hand, the command sync signal falls at the next timing signal φ _R , and BU falls at this fall.
The SY signal falls. Now, when the command “PITCH WRITE” is output from the command control circuit 421, the gate 59 of the address control unit 43 opens and the internal data path IDB
The pitch data output to is set in the 1-channel pitch register 51 in synchronization with the timing signal φ _S. The setting operation is the same for the other registers.

Suppose here that the initial values are set as follows.

PITCH (0) = 0.25 PITCH (1) = 0.25 TEMP (0) = 00000 LOOP START (0) = 00000 LOOP END (0) = 01000 LOOP ON (0) = Set TEMP (1) = 01000 END (1) = [08000] Here, (0) and (1) indicate channels, and TEMP indicates the temporary storage register 52.

Thus, when the set of initial data is completed, CPU31 generates a recording start instruction in step S _3. This recording start command is fetched by the read signal WR ₃ as in the above, and the command control circuit 421 outputs the command “REC START” at the output timing of the command synchronizing signal during the BUSY signal is being generated.
To occur. This command “REC START” is input to the recording flip-flop 101 via the NOR gate 102 and the NOR gate 103 of the trigger control circuit 422, and the recording flip-flop 101 is set by the next timing signal φ _R. Therefore, the Q-side output of the recording flip-flop changes from “0” to “1”, so that the REC ON signal is generated as shown in FIG. 8 (17), and the Q-side output of the recording flip-flop 101 is shown in (1) of FIG.
It becomes like 8). The above REC ON signal is the NAND gate 108
The output of the NAND gate 108 becomes “0” only at the timing of the timing signal T ₀ , and this output is further transmitted through the NAND gate 121 and the OR gate 124 to the “START” command (START signal shown in FIG. 8 (19)). ) Is output to the address control unit 43. On the other hand, the command "REC
“START” is input to the trigger flip-flop 111 via the NOR gate 113 and resets it in synchronization with the timing signal φ _R. Therefore trigger flip-flop 11
The Q-side output of 1 is as shown in FIG. 8 (20), and the timing signal ₀ is output through the AND gate 116, NOR gate 115, and NOR gate 106 and sent to the gate 46 as the gate open signal GAD. As a result, at every T ₀ timing
The waveform data sampled by the A / D conversion circuit 36 is taken into the RAM data bus RD via the gate 46.

Then, the command "START" (START signal) output from the trigger control circuit 422 is input to the play flip-flop 56 via the NOR gate 88 and the NOR gate 78 of the address control unit 43 and is synchronized with the timing signal φ _S. Set this. In this state, pre-recording starts, and when the play flip-flop 56 is set, its output opens the AND gate 63 and supplies the pitch data from the pitch register 51 to the adder 68. The initial value “00000” (address 0) is set in the temporary storage register 52, and the pitch data “0.
Since "25" is set, the adder 68 sequentially adds 0.25 to the contents of the temporary storage register. The added data is sent to the waveform memory unit 44 and sequentially specified from address 0 of the waveform memory 441. , The waveform data sampled by the A / D conversion circuit 36 is sequentially stored from address 0 of the waveform memory 441. On the other hand, “0100” is stored in the loop end register 55.
Since (address 1000) is set, the LOOP signal is output when the address data output from the adder 68 in the comparator 69 matches 1000. Also, since the loop-on flip-flop 57 is set, the AND gate 76
Opens and turns on gate 82 to turn on loop start register 81
The address data “00000” set in is transferred to the temporary storage register 52. After this, the address addition processing is continued again according to the pitch data. That is, the recording operation is performed by repeatedly designating from the loop start address stored in the loop start register 54 to the loop end address stored in the loop end register 55. This is the pre-recording state.

Next, operate the trigger key of the key switch group 33 or
When the recording level exceeds a certain level, CPU31
The EC TRIGGER command is output (steps S ₄ and S _{5 in} FIG. 7 and (9) in FIG. 8). Then, the read signal WR ₃ fetches the command, and the command control circuit 421 causes the command “R
"EC TRIG" is output. This command is input to the trigger flip-flop 111 via the NOR gate 112 and the NOR gate 113 of the trigger control circuit 422, and the timing signal φ
Set this in sync with _R. Also, AND Gate 11
As shown in FIG. 8 (22), the TRIG ON signal is output from 7 and input to the NAND gate 122. Therefore, the timing signal T ₀ is output as a STOP signal via the NAND gates 122 and 123 and the OR gate 125, and the address control unit
It is input to the NOR gate 78 of 43 and resets the play flip-flop 56 of channel 0 (Fig. 8 (23)). As a result, the gate of the AND gate 63 is closed and the address update is stopped. The TRIG ON signal is also input to the NAND gate 120, and the timing signal T ₁ is input to the NAND gates 120 and 12
1, output as a START signal via the OR gate 124 ((19) in FIG. 8). This START signal is input to the NOR gate 88 of the address control unit 43 and sets the 1-channel play flip-flop. "01000" is set in the temporary storage register 52 of one channel, "08000" is set in the end register 53, and "0.25" is set in the pitch register 51, and the address update operation starts from the 1000th address. Namely, the waveform data is written from address 1000 of the waveform memory set 441 (Step S _6). This is the actual recording operation. CPU31 periodically output the command "STATUS READ", read the set state of play flip-flop 56 (step S _7). And if the play flip-flop 56 is set, it does not move to the next processing it is determined that during recording (step S _8). Therefore, in the comparison period 69, the address data output from the adder 68 is the end register 53.
If it matches the address data “08000” output from,
Output the LOOP signal. At this time, the AND gate 76 is not opened because the loop-on flip-flop 57 of channel 1 is not set. On the other hand, the LOOP signal is read by the buffer 77 and output as the END signal, and is input to the NOR gate 78 to reset the play flip-flop and the trigger control circuit 42 of the main control unit 42.
It is input to the second buffer 118. As shown in FIG. 8 (24), when the END signal is input to the buffer 118, it is output from the Q side output of the trigger flip-flop 111 through the AND gate 114 and the NOR gate 115 to which "1" is supplied. Buffer at timing signal ₁ rising edge (T ₁ falling edge)
Read into 118 and buffer 119 with the next timing signal φ _R
And is supplied to the NOR gate 103. As a result, the recording flip-flop 101 is reset and its output becomes "1", so that the REC OFF signal is output through the NOR gate 105 ((25) to (27) in FIG. 8). Therefore, the timing signals T ₀ and T ₁ are supplied from the NAND gate 110 through the OR gate 109, and their outputs become ₀ and ₁ ,
A STOP signal is output at the timing of T ₀ and T ₁ via the NAND gate 123 and the OR gate 125 (FIG. 8 (23)). this
The STOP signal is input to the NOR gate 78 of the address control section 43, and the play flip-flop is set to 0 channel, 1
Reset both channels. Therefore, the AND gate 63 is closed and the address update is stopped. CPU31 is
The contents of the play flip-flop 56 are read by the command "STATUS READ", and when it is found that the play flip-flop 56 is reset, the next process is performed.

1000 of the steps repeated from address 0 of the waveform memory by the channel 0 by the processing up to S ₈ to 1000 address recording made (before recording), the waveform memory 441 by the channel 1
Although the recording was done from the address to the 8000 address (main recording), the process of connecting the pre-recording part and the main recording part is performed in the next process. First, the waveform data from the address 0 of the address 1000 of the waveform memory 441 which is recorded by the channel 0 by DMA at step S ₉ transferred to the memory in the CPU 31 (not shown). That is, the command control circuit 421 to the DMA control circuit 42
A DMA start signal and a signal indicating the direction of DMA (waveform memory 441 → CPU31 in this case) are given to 4, and the DMA control circuit 4
24 outputs a DMA request signal RQ to the CPU 31. When the CPU 31 finishes the processing currently in progress and becomes available for DMA processing, DMA
The enable signal AK is sent and DMA transfer starts. Then the CPU
The memory 31 stores waveform data address 10000 from the address of the waveform memory 441 rearranges the data to the correct order (step S _10). In other words, since recording is repeatedly performed from addresses 0 to 1000, if the position where the loop end signal is output and the pre-recording stops is address 600, the recorded data of one loop before will be left after address 601. Therefore, the addresses are sorted in the order of 601 → 1000, 0 → 600. Therefore, the content stored in the temporary storage register 52 of the address control unit 43 at this time is “00600”, and the loop start register 54 stores “0000”.
0 ", set the loop end register 55 to" 01000 "and the loop on register 57 to set the temporary storage register.
52 Contents are updated as 601 → 1000, 0 → 600, and waveform memory 44
Read from 1 in the correct order. The waveform memory 441
The addresses 0 to 1000 may be unconditionally read and rearranged in the memory in the CPU 31. To this end, the CPU 31 outputs the command "TEMP READ", opens the gate 70, and reads the contents of the temporary storage register 52. And its value is 60
If the address 0 is known, the above processing becomes possible. Next, in step S ₁₁ , the contents of the rearranged memory in the CPU 31 are DMA-transferred from the address of the waveform memory 441 to the address of 1000.

This completes the recording process. Next, the reproduction process will be described. There are two methods of playback: pressing a key on the keyboard 32 to play it at the pitch corresponding to that key, or playing the sound recorded by the monitor switch in the key switch group 33 as is, the former method here. Will be explained. First,
Press the play key of the key switch group 33 to enter the play mode,
Specify one of channels 0-4. In the above recording example, since a musical tone waveform is recorded at addresses 0 to 8000 on 1 channel, channel 1 is specified and "00000" is stored in the temporary storage register 52 (TEMP) and "08000" is stored in the endless 53 as initial values. Set. This set operation is the same as in the case of recording. Next, when you press a key on the keyboard 3,
Pitch data corresponding to the key is set in the pitch register 51. Then, when the CPU outputs the playback command,
The command control circuit 421 of the main control unit 42 outputs the command “PLAY”. This command “PLAY” is input to the address control unit 43 via the OR gate 124 of the trigger control circuit 422, and sets the play flip flip 56 via the NOR gates 88 and 78 in synchronization with the timing signal φ _S. Therefore with this set AND gate
63 opens, and at the time of recording, the address data of the temporary storage register 52 is updated according to the pitch data set in the pitch register 51. At this time, if the inverse flip-flop 58 is set by the command “INV ON”, the “1” signal is input from the inverse flip-flop 58 to the exclusive OR gate 62, and accordingly, the pitch register 51 is passed through the exclusive OR gate 62. The output data is inverted between "1" and "0". Therefore adder
In 68, the complement of the pitch data is added to the content of the temporary storage register 52, that is, the subtraction processing is performed, and the reverse reproduction from the waveform memory 441 becomes possible. The inverse flip-flop 58 is reset by the command "INV OFF".

Then, the address data output from the adder 68 is
The integer part 17 bits are supplied to the waveform memory part 44, and the decimal part 13 bits are supplied to the interpolation part 45. The address data input to the waveform memory unit 44 is +1 at the timing of φ _W.
The address of the waveform memory 441 is specified by being incremented by 1 by the circuit 444, and the waveform memory 441 is as it is at the timing of ▲ ▼.
Specify the address of. That is, an address that is time division and the next address are designated. And
The waveform data read from the waveform memory 441 is set in the latch 452 via the RAM data bus RD, the waveform data of the address incremented by 1 in synchronization with the timing signal φ _W.
The data of the latch 452 is read into the register 453 and the waveform data read by the address data which is not incremented by 1 is read into the register 452 in synchronization with the next timing signal φ _S. Then, the subtractor 454 subtracts the value of the register 453 from the value of the register 451 and the difference data is multiplied by the fractional part of the address data sent from the address control unit 43 by the multiplier 455 to obtain the integer part. The ratio of the fractional part to the waveform data specified by the address data of
Linear interpolation is realized by adding with the data stored in
Output to the D / A conversion circuit 37. In the D / A conversion path 37, the input digital waveform data is converted into an analog value and is output to the musical sound output terminal 39 ₁ via the VCA 38 ₁ activated by the channel 1 designation. If you continue to press the key, unless the loop-on flip-flop 56 is set, the sound stops when the stored waveform is read, but the loop-on flip-flop 56 is set and the loop start register 54 is set to the loop end. If the register 55 is set to an appropriate value, the sound will connect while the key is held down. If the rape-on register 57 is reset when the key is released, the waveform is read to the end and stopped.

〔The invention's effect〕

As described above in detail, according to the present invention, the pre-recording is performed at the start of recording, the main recording is performed by starting the trigger recording, and the pre-recorded portion and the main recording are continuously looped during playback. Since it is set, the head portion is not cut off at the start of recording, and there is an effect that a wasteful non-recorded portion can be prevented.

[Brief description of drawings]

1 to 8 show an embodiment of the present invention. FIG. 1 is an overall configuration diagram, FIG. 2 is a block configuration diagram of a sound source control circuit 34, and FIG. 3 is a detail of a main control unit 42. 4 and 5 are detailed diagrams of the address control unit 43, FIG. 5 is a detailed diagram of the trigger control circuit 422, and FIG. 6 is a waveform memory unit 44.
FIG. 7 is a detailed diagram of the interpolation unit 45, FIG. 7 is a flowchart for explaining the recording operation of the present invention, and FIG. 8 is a time chart for explaining the recording operation of the present invention. Further, FIG. 9 is a diagram for explaining a conventional example. 31 …… CPU, 32 …… Keyboard, 33 …… Key switch group, 34 …… Sound source control circuit, 36 …… A / D conversion circuit, 37 …… D / A conversion circuit, 41 …… Interface section, 42… … Main control section, 43 …… Address control section, 44 …… Waveform memory section, 45 …… Interpolation section, 421 …… Command control circuit, 422 …… Trigger control circuit, 441 …… Waveform memory.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroyuki Sasaki 3-2-1 Sakaemachi, Hamura-cho, Nishitama-gun, Tokyo Casio Computer Co., Ltd. Hamura Technical Center Examiner Saito Misao

Claims (1)

[Claims] 1. A waveform memory means capable of writing / reading an acoustic waveform signal, an address designating means for designating an address of the waveform memory means for writing / reading the acoustic waveform signal, and an address of the waveform memory means. The loop start storage means for storing the start address of the repeat designation, the loop end storage means for storing the end address of the repeat designation of the waveform memory means, and the pre-recording according to the pre-recording instruction given prior to the main recording. In order to carry out, the first sound writing means for writing the given acoustic waveform signal in the area of the waveform memory means corresponding to the address designated by the address designating means, and the main recording provided after the pre-recording. In order to perform the actual recording according to the instruction, the acoustic waveform signal given above is connected to the previous recording. Second writing means for writing in the area of the waveform memory means corresponding to the address designated by the address designating means, and the loop for the address designating means according to the reproduction instruction given after the main recording. By sequentially and repeatedly instructing an address within the address section defined by the start address stored in the start storage section and the final address stored in the loop end storage section, the waveform memory corresponding to this address section The acoustic waveform signal stored in the area of the means is repeatedly read, and the acoustic waveform signal recorded in the above-mentioned pre-recording and the acoustic waveform signal recorded in the above-mentioned actual recording are connected to each other to produce an unbroken acoustic waveform. A sound recording / reproducing apparatus comprising: a reading unit for obtaining a signal.