JPS61167998A - Musical interval controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pitch control device, and more particularly to a pitch control device that controls the pitch between an original sound and a reproduced sound by changing the frequency of an audio signal as desired. be.

The read data is obtained by sampling and digitizing the 1N audio signal, sequentially writing it into a storage means such as RAM (Random Access Memory), and changing the reading cycle of the written data according to a command. The applicant of the present application has proposed a pitch control device that controls pitch by changing the frequency of a reproduced audio signal obtained from a music player.

FIG. 1 is a schematic block diagram of such a device. In the figure, 1 is an adder that adds a predetermined constant value M or N to the read address of the RAM, and 2 is the output of the adder 1 and the RAM.
3 is a control circuit that generates a cross-fade control signal based on the cross-fade start signal output from comparator 2; 4 is a RAM and latch as a storage device, which compares the write address and read address; has inputs and has two read addresses R and K (R' = R
+M or R+N: M and N are arbitrary fixed integers) to latch each data. Reference numeral 6 denotes a cross fader which reads two data from the RAM and the latch 4 according to the output of the control circuit 3 to obtain an output signal.

In this configuration, a read address is input to the RAM 4 through the multiplexer 5, and data corresponding to the address R is latched. On the other hand, the read address is added with a constant value M or N by the adder 1, and this becomes the address R'(R' - R+M or R+N), which is input to the RAM 4 through the multiplexer 5, and the data corresponding to the address R' is added. Latch. Further, when the output R' obtained from the adder 1 and the write address become the same, a cross-fade signal of H level or L level is output. This predicts discontinuities due to differences in write and read clock speeds. This matter will be explained in detail below with reference to FIGS. 2 and 3.

For example, if the read clock speed is faster than the write clock speed, set R'(R' = R + M) ahead of the read address R as shown in Figure 2, and if this becomes the same as the write address. , address R is approaching address W of the write clock. On the other hand, if the write clock speed is faster, as shown in Figure 3, it is sufficient to provide a detection address R'(R'-R+N) after the read address R, and R' is at the rear. Being located in the RAM means subtraction, but since addresses are considered to circulate within the RAM, in circuit terms, for example, the maximum address capacity of the RAM minus M (R
AM capacity - M) may be added as N. In both cases, compare! ! It is possible to detect that the read address and the write address are close to each other by the output of 2, so from that point on, a cross fade control signal is generated to apply the cross fade, and the data corresponding to the address R obtained in RAM 4 and the detection address R are generated. A cross-fade is performed using the data corresponding to .

FIG. 4 shows an embodiment showing the specific configuration of FIG. 1. First, the basic clock is input to three branching units 71, 72, 73 to create a write clock W1, a control clock C, and a read clock R. The clock is timing circuit 8
is input. The timing circuit 8 outputs signals for switching between write and address signals and read address signals, switching between two address signals R9R', and controlling switches. A write address is supplied from the timing circuit 8 to the write counter 10 by the write clock W to create a write address, and a read address R is created by the timing circuit 8 to the read counter 11 by the read clock.

The read address R is directly input to the multiplexer 5, and the detected address R' is obtained through the adder 1, which is input to the multiplexer 5. The outputs of the write counter 10 and the multiplexer 5 are input to the multiplexer 9, and the outputs of the write counter 10 and the adder 1 are compared by the comparator 2. Each multiplexer 5.9 is switched and controlled by a control clock C from a timing circuit 8.

On the other hand, the input signal is digitally converted by the A/D converter 12 and supplied to the RAM 4 through the 3-state buffer 13. Data in the RAM 4 is supplied to two transmission lines for read address R and detection address signals. That is, latch 14R114R', D/A latch 15R,
Analog data corresponding to each address is obtained by 15R' and D/A converters 16R and 16R', and is input to the crossfate circuit.

The operation of this configuration will be explained with reference to the timing charts shown in FIGS. 5(a) to 5(q).

The multiplexer 9 selects the write address W and the read address R or R' from the RAM at the timing shown in FIG. 5(a).
At this timing, a write operation or a read operation of the RAM 4 is performed in response to a control signal from the timing circuit 8. Furthermore, the latch 14R transfers the address R from the RAM 4 at the rising edge timing shown in FIG. 5(b).
Latch the data corresponding to . Then, a little later than this timing, the multiplexer 5 switches the read address from address R to R' at the timing shown in FIG. At the timing shown in FIG. 5(d), the data in RAM4 corresponding to address R' is latched to 14R.
’ latches this. And each latch 14R, 14
The data latched in R' is latched in D/A latches 15R and 15R' at the rising edge of g> in FIG. It is input to circuit 6.

On the other hand, when the multiplexer 9 switches to the write W side shown in FIG. 5(a), the digital input signal is sent to the RAM 4 from the A/D converter 12 at the timing shown in FIG.
4, it is written to the location corresponding to the write address W.

Therefore, the addresses of the RAM 4 are arranged in the order shown in FIG. 5(f).

Then, the write counter 10 and the detection address R' which is the output of the adder 1 are compared, and if they match, it is output to the cross-fade control circuit, and this output is input to 6 to write the RAM for addresses R and R'. Crossfade and output the data.

Such a cross-fade is shown in FIG.
This is an example where the read address R has a higher frequency than the write address W. It can be seen that there is a cross-fade state between times t1 and t3, and new data (R') appears after t3.

In such conventional devices, a certain integer N (or M) is added to the address R to obtain the read address R', so a dip occurs in the output data at a specific frequency, resulting in a so-called tremolo sound. Sometimes it happens. In other words, if the signals read by these two addresses R and R' are in opposite phases to each other, the cross-fade coefficient (attenuation coefficient)
is exactly equal on both sides, the cross-fade output may become zero.

SUMMARY OF THE INVENTION An object of the present invention is to provide a pitch control device that reduces the occurrence of tremolo sounds during such crossfading.

The pitch control device according to the present invention converts an analog audio signal into a digital signal, writes this digital signal into a storage device, and changes the successive output speed for reading the digital signal from the storage device with respect to this blue-in speed. The target is a pitch control device that can freely control the pitch of an analog audio signal by detecting a discontinuous point in the read data caused by the difference between the writing speed and the reading speed, and storing it before and after the discontinuous point. The reading means includes reading means for reading mutually different first and second data from the device, and cross-fade control means for cross-fading the first and second read data, the reading means for reading the first data. , a random data generating means for generating random data, and an arithmetic means for operating the address and the random data, and the output data of the arithmetic means is used as the read address of the second data. It's about doing.

Example Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 7 is a block diagram of an embodiment of the present invention, and parts equivalent to those in FIG. 1 are designated by the same reference numerals. In the figure, the difference from FIG. 1 is that 20 is a random signal generation circuit, and the control circuit 3 controls the start of random signal generation. This random signal is added to the read address in the adder 1 and becomes R-.

The other configurations are the same as those shown in FIG. 1, and their explanation will be omitted.

With this configuration, the read address R- during the 13 cross-fade period is not the sum of R and the constant N, but the sum of random data, so when a continuous signal is cross-fade, at 1 nos R An opposite phase relationship will not occur continuously between the signals (R, R') read out by R' and R'. Therefore, it is possible to reduce the occurrence of tremolo sound. 8th
The figure shows the relationship between the occurrence of cross-fade and the number of additions (random numbers) in adder 1. Even if R and R' are in opposite phases during the first cross-fade, the following When cross-fading, the number of additions N is N
1 to N2, and the probability that both signals will be in an opposite phase relationship again is low.

FIG. 9 shows a specific example of the random signal generation circuit 20, in which the lower two bits of the digital output of the audio signal are
FF (delayed flip 70 knob) is latched by 21 and 22, and the latch output is sent to A in the bit adder 24.
n-4, An-3 Used as manual power. and other AOs
~An-5゜An-2, An input is set to low level, An
- Increase the level of one-manpower to a high level.

Address data R of the read address counter 23 is applied to the other bit input 8O-Bn of the bit adder 24. This addition output becomes the single power of the multiplexer 5.

Here, since the lower bits of the digital output of the audio signal can be regarded as almost irregular data, the DFF 21.
The latch output of No. 22 can become part of the target random data.

FIG. 10 is a block diagram of another embodiment of the present invention, and parts equivalent to those in FIG. 7 are designated by the same reference numerals. In this example, crossfading is performed not at the analog signal stage but at the digital signal stage.

Read data from the RAM 4 is input to a crossfader 17, crossfaded, and converted into an analog signal by a D/A converter 18. In response to the IIIIl signal from the crossfade IIilJgE circuit 3, the address generation circuit 26 operates to sequentially derive the corresponding constants A and B from the memory 27 and supply them to the crossfader 17. In this crossfader 17, read data R, R= from the RAM 4 and a constant A.

B and are respectively multiplied and input to the D/A converter 18.

FIG. 11 is a block diagram showing a specific example of a portion related to the crossfader 17 in FIG. 10, and portions equivalent to those in FIG. 10 are designated by the same reference numerals. Read data R from RAM,
R'' is a constant (coefficient) A derived from the memory 27 in the multipliers 81 and 82.

A-R and 8-R' are obtained by multiplying by B, respectively. These multiplication results are added together in an adder 83 and A−R+
BR', and this addition result is supplied to the D/A converter 18. A plurality of multiplication coefficients A and B for digital data are stored in advance in the memory 27, and these coefficients are sequentially derived and multiplied by the digital data between t1 and t3 in FIG.

Therefore, in this case, the coefficients A for the data R are set to become successively more conducive, and the coefficients B for the data R' are set to become successively larger.

This makes it possible to perform the crossfade shown in FIG. The length of t1 to t3) can be adjusted freely. As a method for controlling the address generation speed, for example, the generation speed (frequency) of the clock that is input to the address counter may be freely controlled.

Furthermore, by changing the values of the coefficients A and B, the shape of the crossfade is not limited to a straight line, but can also be curved. In this method, the derivation coefficients A and B may be selected by appropriately selecting the address counter for address generation and changing the read coefficients A and B in the memory 27.

Effects of the Invention According to the present invention, the address difference between the data R to be faded out and the data R- to be faded in when performing a crossfade is made into irregular data, which eliminates the problem of tremolo sound during a crossfade, which has been a problem in the past. It has the effect of reducing the occurrence.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a pitch control device proposed by the applicant, FIGS. 2 and 3 are diagrams showing the positional correspondence of read addresses and write addresses in RAMh for explaining the operation of FIG. 1, FIG. 4 is a diagram showing a specific example of the blocks in FIG. 1, FIGS. 5 and 6 are diagrams for explaining the operation of FIG. 4, and FIG. 7 is a block diagram of an embodiment of the present invention.
8 is a diagram explaining the operation of the blocks in FIG. 7, FIG. 9 is a diagram showing a specific example of some of the blocks in FIG. 7, and FIG. 10 is another block diagram of the embodiment of the present invention. FIG. 11 is a diagram that does not show specific examples of some of the blocks in FIG. 10. Explanation of symbols of main parts 1... Adder 2... Comparator 3
......Crossfade control circuit 4...R
AM and latch 5...Multiplexer 17...Cross fader 18...D/A converter 20...Random data generation circuit Applicant
Pioneer Co., Ltd. Representative Patent Attorney Motohiko Fujimura Figure 1, Red, 2, Fluffy, 5, Breasts, Bee R, Bee F,
? Figure 7

Claims (2)

[Claims] (1) Converting an analog audio signal into a digital signal, writing the digital signal in a storage device, and changing a read speed for reading the digital signal from the storage device with respect to this writing speed, converting the analog audio signal into a digital signal. The pitch control device is capable of freely controlling the pitch of a pitch, wherein the pitch control device detects a discontinuous point in the read data caused by a difference between the writing speed and the reading speed, and records different first and second pitches from the storage device before and after the discontinuous point of the read data. The reading means includes a reading means for reading data, and a cross-fade control means for cross-fading the first and second read data, and the reading means sequentially generates addresses for reading the first data. means, random data generating means for generating random data, and calculating means for calculating the address and the random data,
A pitch control device characterized in that the output data of the calculation means is used as a read address of the second data. (2) The pitch control device according to claim 1, wherein the random data generating means is configured to generate random data from a part of the digital signal.