JPH0782049B2 - Spectrum display - Google Patents

Description

TECHNICAL FIELD The present invention relates to a spectrum display device for displaying a frequency distribution of an input signal.

BACKGROUND ART A spectrum display device is known as a device for displaying a frequency distribution of an input signal such as an audio signal, and is disclosed in, for example, Japanese Patent Publication No. 58-43700. Such a conventional spectrum display device is provided with a level detection means including a BPF (bandpass filter), a detection circuit, and an LPF for each of a plurality of predetermined frequency bands, and detects the signal level of each band by them. , Each detection level is displayed on a display in association with a frequency band.

Therefore, in the conventional spectrum display device, there is a drawback that the structure is complicated because it is necessary to provide level detection means for the number of frequency bands in order to display the frequency distribution finely.

SUMMARY OF THE INVENTION [Object of the Invention] An object of the present invention is to provide a spectrum display device that does not need to provide level detection means for the number of frequency bands in order to display the frequency distribution finely.

[Structure of the Invention] The spectrum display device of the present invention is provided with a plurality of band variable filters that pass only the components in the input signal in the band indicated by the supplied band specifying signal, and detects a plurality of output levels of the band variable filters. Level detection means, and designation signal generation means for generating a band designation signal indicating one of a plurality of different frequency bands at a predetermined timing and supplying the band designation signal to the plurality of level detection means in a predetermined order. And a control means for reading the detection level by the level detection means after a lapse of a predetermined time from the supply of the band designation signal and displaying the read detection level on the display means in association with each band. The number is smaller than the number of different frequency bands.

Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

In the spectrum display apparatus as one embodiment of the present invention shown in FIG. 1, an analog audio signal to be measured is supplied to an A / D converter 1 and converted into a digital signal. A DSP 2 is connected to the output of the A / D converter 1. DSP
2 is an arithmetic processing unit 3 for performing arithmetic processing according to a program
And an interface 4 for relaying coefficient data, signal delay time data and program data supplied from a microcomputer 7, which will be described later, and start and stop commands for arithmetic processing to the arithmetic processing unit 3, and the arithmetic processing unit 3. Output registers 5 and 6 for holding the output calculation result are provided. The arithmetic processing unit 3 performs an operation equivalent to the operation of circuits such as a BPF, a detection circuit, an LPF, a switch and an adder as described later. The shift of data output from the output register 6 is performed in synchronization with the clock pulse supplied from the MPX (multiplexer) 8. The MPX8 is supplied with the first and second clock pulses, and either one of the first and second clock pulses is selectively output according to a command from the microcomputer 7. The first clock pulse is a pulse that has a synchronous relationship with a pulse that controls the operation timing of the arithmetic processing unit 3, and is generated from the clock generator 12. The second clock pulse is a pulse that is in synchronization with the pulse that controls the operation timing of the microcomputer 7, and its frequency is lower than that of the first clock pulse. The output register 5 is supplied with the first clock pulse. The D / A converter 10 is connected to the output register 5, and the D / A converter 10
In the DSP 2, for example, a digital audio signal subjected to a predetermined sound field control process is supplied. On the other hand, the output of the output register 6 is connected to the microcomputer 7.

The microcomputer 7 is provided as control means, and although not shown, a microprocessor, interface, RA
It is composed of M, ROM and a clock generator for generating a second clock pulse. In addition, the microcomputer 7
A display 9 and a keyboard 11 are connected to the. As shown in FIG. 2, the display 9 displays vertical bars of T (9 bands in the figure) of the number of bands, and is composed of, for example, an LCD or an LED.

In such a configuration, the digital signal supplied from the A / D converter 1 to the DSP 2 is arithmetically processed by the arithmetic processing unit 3 according to the program. By this arithmetic processing, a circuit is formed as shown in FIG. That is, A / D converter 1
Filter circuits F ₁ and F ₂ as two detection means for detecting the signal level of only the component in the input signal in the band indicated by the supplied band designation signal are connected to the output of the. Filter circuit F ₁ is an input switch BPF32, detection circuit 33, LPF34 and output switch The filter circuit F ₂ consists of BPF37, detection circuit 38, LPF39 and output switch Consists of. The BPFs 32 and 37 are provided as band variable filters capable of changing the pass band, and the pass band is f _{1 to} f _T (T represents the number of bands and is an integer greater than 2).
Any one of them is selectively set by changing the coefficient data group as described later. The adder 41 to the output of the filter circuit F _1, F ₂ are connected, the detection level by the filter circuit F _1, F ₂ is adapted to be added. The added level is supplied to and held in the output register 6 for each band.

For example, when a spectrum display start command is issued to the microcomputer 7 by operating the keyboard 11, the microcomputer 7 starts the spectrum display operation. In this spectrum display operation, the microcomputer 7 issues a command to the DSP 2 such as a command to form each element such as BPF and a command to turn on / off the input and output switches. In response to these commands, the DSP ₂ forms filter circuits F ₁ and F ₂ according to a program and performs a level detection arithmetic operation of each band.

That is, in the spectrum display operation, the microcomputer 7 sets the variable m to 1 and sets the flag F to 1 as shown in FIG. 4 (step S1). And DSP2
BPF the BPF32 and band the band and f _m and f _{m + 1} with respect to
37 is formed with the detection circuits 33, 38 and LPFs 34, 39 (step S2), and the input switch On, output switch Turn off (step S3). As a result, the DSP ₂ starts the level detection operation of the band f _m component of the input signal in the filter circuit F ₁ and the level detection operation of the band f _{m + 1} component of the input signal in the filter circuit F ₂ according to the program.

Next, it is determined whether the flag F is 0 (step
S4). If F = 0, output switch Is turned on (step S5). Therefore, the filter circuit
The band f _m (however, band f _n from the second execution of steps S5 to S15) component of the input signal detected by F ₁ is supplied as data to the output register 6 and held therein. Therefore, the microcomputer 7 reads the detection level from the output register 6 (step S6).

When reading the detection level, the microcomputer 7 generates a second clock switching command as shown in FIG. 5 (step S31), and this second clock switching command is supplied to the MPX8. Although not shown, the second clock switching command is supplied to the output register 6 and the switching command disables data input to the output register 6. MPX8 is second
The second clock pulse is supplied to the output register 6 in response to the clock switching command. As a result, the output register 6 shifts and outputs the detection level data, which is the held data, in synchronization with the supplied second clock pulse. The detection level data shifted and output is synchronized with the operation timing of the microcomputer 7. Therefore, the microcomputer 7 reads the detection level data from the output register 6 (step S32) and finishes the reading (step S3).
3), the first clock switching command is generated (step S3
Four). The MPX8 supplies the first clock pulse to the output register 6 again in response to the first clock switching command.

After reading the detection level data from the output register 6, the microcomputer 7 sets all the coefficient data for forming the BPF 32 and LPF 34 to 0, and inputs the switch. Is turned off (step S7), and a spectrum analyzer is displayed by supplying a drive signal to the display device 9 according to the detection level data (step S7).
8). After displaying the spectrum analyzer, output switch Is turned off (step S9), 2 is added to the variable m, and the value obtained by the addition is set as the variable n (step S1).
0). It is determined whether or not the variable n is larger than the number of bands T (step S11). If n> T, T is subtracted from the variable n (step S12), and if m ≦ T, the value of the variable n is held as it is.

Next, a detection circuit 3 for the BPF 32 having a bandwidth f _n for the DSP 2
3 and LPF34 (step S13), input switch Is turned on (step S14). As a result, in the DSP 2, the level detection operation of the band f _n component of the input signal is started in the filter circuit F ₁ . Then, the flag F is set to 1 (step S15), 1 is added to the variable m (step S16), and it is determined whether or not m is larger than T (step S17). If m> T, the variable m is set to 1 (step S
18) If m ≦ T, the value of the variable m is held as it is.
After execution of step S17 or S18, the process proceeds to step 4.

When the process returns to step S4 after execution of step S17 or S18, F = 1, so step S19 is executed. Output switch in step S19 To turn on. Therefore, the band f _{m + 1} of the input signal detected by the filter circuit F ₂ (where the second step
From the execution of S19 to S29, the band f _n ) component is supplied to the output register 6 as data and held therein. Therefore, the microcomputer 7 reads the detection level from the output register 6 (step S20). When this detection level is read out, it is performed as in steps S31 to S34 described above.

After reading the detection level data from the output register 6, the microcomputer 7 sets all the coefficient data for forming the BPF 37 and LPF 39 to 0, and inputs the switch. Is turned off (step S21) and a drive signal is supplied to the display 9 in accordance with the detection level data to perform spectrum analyzer display (step S22). After displaying the spectrum analyzer, output switch Is turned off (step S23), 2 is added to the variable m, and the value obtained by the addition is set as the variable n (step S2).
Four). It is determined whether or not the variable n is larger than the number of bands T (step S25). If n> T, T is subtracted from the variable n (step S26), and if m ≦ T, the value of the variable n is held as it is.

Next, the detection circuit 3 for the BPF 37 whose band is f _n for DSP2
8 and LPF39 (step S27), input switch Is turned on (step S28). As a result, in the DSP ₂ , the level detection operation of the band f _n component of the input signal is started in the filter circuit F ₂ . Then, the flag F is reset to 0 (step S29), and the process proceeds to step S16.

In this manner, the microcomputer 7 repeats the operation to sequentially obtain the detection level of each band held in the output register 6 of the DSP 2 and generate a drive signal according to the detection level. Since the drive signal indicates the display level of the T vertical bars, the signal level of each band is displayed on the display 9 as shown in FIG. 2 according to the drive signal, and is read every time the detection level data is read. The band display level will be updated.

FIG. 6 shows the relationship between the operation in each of the above filter circuits and the level detection and display timing.

FIG. 7 shows a schematic configuration of the arithmetic processing unit 3 including the interface 4 and the output registers 5 and 6 in the DSP 2. A digital signal is supplied from the A / D converter 1 to the input register 13. A data bus 14 is connected to the input register 13, and the data bus 14 is connected to one input of a data memory 22 for temporarily storing a data group and a multiplier 15. A buffer memory 16 for holding coefficient data is connected to the other input of the multiplier 15. A coefficient RAM 17 is connected to the buffer memory 16, and a coefficient data group is stored in the RAM 17. One coefficient data is sequentially read from the coefficient data group stored in the RAM 17 according to a timing signal from the sequence controller 20 described later,
It is supplied to the buffer memory 16 and held therein. The coefficient data held in the buffer memory 16 is supplied to the multiplier 15. The ALU (adder) 18 is provided for accumulating the calculation output of the multiplier 15, the calculation output of the multiplier 15 is supplied to one input, and the other is connected to the data bus 14. An accumulator 19 is connected to the calculation output of the ALU 18, and an output of the accumulator 19 is connected to the data bus 14. A memory control circuit 24 that controls data writing and reading of the external memory 23 is connected to the data bus 14. A delay time RAM 25 that stores a delay time data group is connected to the memory control circuit 24, and the memory control circuit 24 delays the audio signal data by each delay time data stored in the delay time RAM 25.
The input audio signal data is written to and read from. Further, the output registers 5 and 6 are connected to the data bus 14.

The operations of the register 13, multiplier 15, coefficient RAM 17, ALU 18, accumulator 19, and memory control circuit 24 are controlled by the sequence controller 20. The sequence controller 20 operates according to the processing program written in the program memory 30, and operates according to a command from the microcomputer 7. Further, the microcomputer 7 controls the rewriting of the processing program and the rewriting of the coefficient data of the RAM 17 and the delay time data of the RAM 25 according to the key operation of the keyboard 11.

In the DSP 2 including the arithmetic processing unit 3 having such a configuration, it is supplied to and stored in the data memory 22 via the digital audio signal data input register 13. The sequence controller 20 reads the data from the input register 13, the timing of selectively transferring the data from the data memory 22 to the multiplier 15, the timing of outputting each coefficient data from the RAM 17, the multiplication operation timing of the multiplier 15, ALU18 addition operation timing, accumulator 19
The timing such as the timing for outputting the held data of is taken.

By taking these timings, the audio signal data input from the data memory 22 is read and supplied to the data memory 22 via the data bus 14 and stored therein. The signal data stored in the data memory 22 is sequentially read out and supplied to the multiplier 5. On the other hand, coefficient data is sequentially read from the RAM 17 and supplied to and held in the buffer memory 16. The coefficient data from the buffer memory 16 and the data from the data memory 22 are supplied to the multiplier 15, and the multiplier 15 multiplies them one after another. The value obtained by this multiplication is accumulated in the ALU 18 with the value up to the previous time (the value held in the accumulator 19), and the operation result is held in the accumulator 19.
By such arithmetic processing, the same operation as that of the above BPF or LPF can be obtained.

The BPF and LPF obtained in DSP2 are shown in the equivalent circuit.
As shown in the figure, it is configured as a second-order IIR type filter. In this filter, a counting multiplier 31 and a delay element 32 are connected to the input terminal to which the audio data signal is supplied. A coefficient multiplier 33 and a delay element 34 are connected to the output of the delay element 32. A coefficient multiplier 35 is further connected to the output of the delay element 34. Coefficient multiplier 31,33,35
Each output of is connected to the adder 36. A delay element 37 is connected to the output of the adder 36. A coefficient multiplier 38 and a delay element 39 are connected to the output of the delay element 37. A coefficient multiplier 40 is further connected to the output of the delay element 39.
The outputs of the coefficient multipliers 38 and 40 are also connected to the adder 36.

Each delay time of the delay elements 32, 34, 37, 39 corresponds to one sampling period. Therefore, the data supplied to the multiplier 33 is one sample before the data supplied to the multiplier 31, and the data supplied to the multiplier 35 is two samples before the data supplied to the multiplier 31. The data. Multiplier
The same applies to 38 and 40.

Depending on the setting of each coefficient of multiplier 31, 33, 35, 38, 40, BPF or LPF
Is obtained, and its frequency characteristic can be changed. Therefore, in DSP2, the coefficient RAM17 is stored in the BPF band f ₁
~ F _n and LPF coefficient data groups are stored respectively, the coefficient data are read out in a predetermined order, and the multiplier 15
To supply. That is, the coefficient data group is supplied to the multiplier 15 as a band command signal, whereby the band is set.

When such a second-order IIR filter is formed by DSP2 by digital processing, DSP2 operates as follows.

First, in the first step, the input audio signal data d _n is read from the address n of the data memory 12, and the RAM 17
The coefficient data a ₂ (corresponding to the coefficient of the multiplier 35) is read from the
To multiply. In the third step, which is two steps after the first step, 0 is added to the multiplication result a ₂ · d _n by the ALU 18, and the addition result is held in the accumulator 19.

In the second step, the signal data d _n-1 is read from the address n-1 of the data memory 12, and the read signal data
The multiplier 15 multiplies d _n−1 and the coefficient data a ₁ (corresponding to the coefficient of the multiplier 33) newly read from the RAM 17.
The multiplication result a ₁ · d _n-1 is ALU18 in the fourth step.
The value held in the accumulator 19 (addition result of the third step) is added by and the addition result is held in the accumulator 19. Next, in the third step, the input signal data IN is transferred from the interface 13 to the data memory.
Coefficient data a transferred to n-2 address 12 and multiplier 15
Multiply by ₀ (corresponding to the coefficient of the multiplier 31) by the multiplier 15. The multiplication result a ₀ · IN is AL in the fifth step.
The value held in the accumulator 19 (the addition result of the fourth step) is added by U18, and the addition result is held in the accumulator 19.

In the fourth step, the signal data d _{n + 2} is read from the address n + 2 of the data memory 12, and the read signal data d
_{n + 2} and coefficient data b ₂ (multiplier newly read from RAM17
(Corresponding to a coefficient of 40) is multiplied in the multiplier 15. In the sixth step, the held value of the accumulator 19 (the addition result of the fifth step) is added to the multiplication result b ₂ · d _{n + 2} , and the addition result is stored in the accumulator.
Held at 19. Then, in the fifth step, the signal data d _{n + 1} is read from the address n + 1 of the data memory 12,
Read signal data d _{n + 1} and read coefficient data
b ₁ (corresponding to the coefficient of the multiplier 38) is multiplied by the multiplier 15. In the seventh step, the holding value of the accumulator 19 (addition result of the sixth step) is added to the multiplication result b ₁ · d _{n + 1} and the addition result is held in the accumulator 19 as output data.

Further, in the DSP2, the detection circuit is formed by the operation of converting the sign of a negative data value into a positive value.

EFFECTS OF THE INVENTION As described above, according to the present invention, a plurality of band variable filters each having only a component in the input signal in the band indicated by the supplied band designation signal are provided to detect the output level of the band variable filter. Of the plurality of different frequency bands is generated at a predetermined timing, the band designation signal is supplied to the plurality of level detection units in a predetermined order, and the band designation signal is generated. The detection level detected by the level detection means after a lapse of a predetermined time after the signal is supplied is read, and the read detection level is displayed on the display means in association with the band. Therefore, it is not necessary to provide level detecting means for the number of frequency bands to be displayed, and at least two level detecting means are sufficient, so that the structure does not become complicated. In particular, if a DSP is used, level detecting means for different bands can be easily formed within a single element, so that there is an advantage that the entire apparatus can be made small.

Further, after a lapse of a predetermined time from supplying the band designation signal to the band variable filter, the level detected by the level detecting means having the band variable filter is read. That is, when the designated band is changed, the detection level is not read until the frequency characteristic of the band variable filter becomes stable, so that erroneous detection of the level can be prevented and accurate spectrum display can be performed.

Further, by using at least two level detecting means, for example, after changing the band of one level detecting means, the detection level is read from the other level detecting means and immediately the band of the other level detecting means is changed. Then, by reading the detection level from one of the level detection means and repeating it, it is possible to avoid the time loss until the above operation is stabilized.

[Brief description of drawings]

1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a display unit in the apparatus of FIG. 1, and FIG. 3 is formed by arithmetic processing by the DSP in the apparatus of FIG. FIG. 4 is a block diagram showing the circuit configuration, FIG. 4 is a flow chart showing the operation of the DSP, FIG. 5 is a flow chart showing the operation of the microcomputer, and FIG. 6 shows the operation in each filter circuit and the level detection and display timing. FIG. 7 is a block diagram schematically showing the configuration of the arithmetic processing section, and FIG. 8 is a diagram showing the configuration of the IIR type filter. Explanation of code of main part 2 …… DSP 3 …… Computational processing unit 7 …… Microcomputer 9 …… Display F ₁ , F ₂ …… Filter circuit

Claims (3)

[Claims] 1. A plurality of level detecting means each provided with a band variable filter for passing only a component in an input signal of a band indicated by a supplied band designation signal, for detecting an output level of the band variable filter, and a predetermined timing. The band designation signal is generated by generating the band designation signal indicating one of a plurality of different frequency bands and supplying the band designation signal to the plurality of level detection units in a predetermined order. And a control means for reading the detection level by the level detection means after a predetermined time has elapsed and displaying the read detection level on the display means in association with each band, and the number of the plurality of level detection means is the above-mentioned. A spectrum display device characterized by being smaller than the number of different frequency bands. 2. The spectrum display device according to claim 1, wherein said level detecting means is formed by an arithmetic processing step in a DSP (digital signal processor). 3. The level detecting means includes a detection circuit for detecting an output signal of the band variable filter in addition to the band variable filter, and an LPF for averaging output signals of the detection circuit.
The spectrum display device according to claim 1, further comprising (low pass filter).