JPH07104773B2 - Digital signal processor - Google Patents

Description

TECHNICAL FIELD The present invention relates to a digital signal processing device.

2. Description of the Related Art Recently, a DSP (digital signal processor) is known that can obtain an output equivalent to a circuit operation by high-speed arithmetic processing of a signal obtained by digitizing an analog signal such as four arithmetic operations. The DSP processes the input digital signal by the processing means. The arithmetic processing means basically comprises, for example, a data memory for storing input digital signal data and a coefficient memory for storing a plurality of coefficient data, and sequentially reads out signal data and coefficient data from the data memory and coefficient memory according to a program and multiplies them. The data value is multiplied by the calculator, and the value of the multiplication result for each multiplication is accumulated. The coefficient data stored in the coefficient memory is write-controlled by an external microcomputer, and is rewritten when the content of the arithmetic processing, for example, the filter characteristic applied to the signal obtained by the arithmetic processing is changed. The data of the processing result of the arithmetic processing means is output via the output register.

By the way, in the DSP, each component operates in synchronization with the clock pulse generated from the internal clock generator, and this clock pulse is data such as audio data that requires many steps of operation in a short time. Need to be fast when dealing with. However, if the frequency of the clock pulse is high, the data is output from the DSP at a high speed, so the output data cannot be read directly by a normal microcomputer, and the coefficient data in the coefficient memory can be rewritten according to the processing result of the DSP. However, there was a problem in that it was not possible to control the DSP.

SUMMARY OF THE INVENTION [Object of the Invention] It is an object of the present invention to provide a digital signal processing device capable of directly reading data output from a DSP and controlling the DSP according to a processing result of the DSP. .

[Configuration of the Invention] A digital signal processing apparatus of the present invention is a processing unit for processing an input digital signal at high speed according to a predetermined program and outputting the same, and output data of the processing unit is synchronized with a supplied clock pulse. A digital signal processing device comprising: holding means for outputting held data at the above timing; and clock pulse generating means for supplying to the holding means a first clock pulse synchronized with the operation timing of the arithmetic processing means. The control means includes control means for controlling the arithmetic processing means according to the output data, the control means generating a switching command when reading the output data of the holding means, and the clock pulse generating means having a frequency lower than that of the first clock pulse by the control means. The second clock pulse having a timing at which data can be read is supplied to the holding means in response to the switching command. It is characterized by supplying.

Embodiment Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

In the digital signal processing apparatus according to the embodiment of the present invention shown in FIG. 1, an analog audio signal is supplied to the A / D converter 1 and converted into a digital signal. A DSP 2 is connected to the output of the A / D converter 1. The DSP 2 includes an arithmetic processing unit 3 for arithmetically processing the supplied digital signal data according to a program, and a microcomputer 7 described later.
The interface 4 which relays and supplies the coefficient data, the signal delay time data and the program data supplied from
And output registers 5 and 6 for holding the calculation result output from the calculation processing unit 3. The shift of data output from the output register 6 is performed in synchronization with the clock pulse supplied from the MPX (multiplexer) 8. The MPX8 is supplied with the first and second clock pulses.
Either one of the second clock pulse and the second clock pulse is selectively output according to a command from the microcomputer 7. The first clock pulse is a pulse that controls the operation timing of the arithmetic processing unit 3 and is generated from the clock generator 12. The second clock pulse is a pulse that controls the operation timing of the microcomputer 7, and its frequency is lower than that of the first clock pulse. The output register 5 is supplied with the first clock pulse. D / A converters 9 and 10 are connected to the output registers 5 and 6, and the D / A converters 9 and 10 convert the supplied digital signals into analog signals. The output of the output register 6 is connected to the microcomputer 7.

The microcomputer 7 is provided as control means, and although not shown, a microprocessor, interface, RA
It is composed of M, ROM and a clock generator for generating a second clock pulse. In addition, the microcomputer 7
A keyboard 11 is connected to.

In such a configuration, the digital signal supplied from the D / A converter 1 to the DSP 2 is arithmetically processed by the arithmetic processing unit 3 according to the program. For example, the arithmetic processing unit 3 performs an arithmetic processing operation for obtaining a filter characteristic for controlling a sound field on an input digital audio signal and a processing operation such as detection of an average level of the input digital audio signal. The signal data as a result of the arithmetic processing is output register 5
Or 6 is supplied. The output register 5 is supplied with the first
The held signal data is shifted out in synchronization with the clock pulse. The output register 6 is normally supplied with the first clock pulse from the MPX8. Therefore, the output registers 5 and 6 shift-output the signal data held respectively and supply them to the D / A converters 9 and 10.

The microcomputer 7, for example, generates a second clock switching command as shown in FIG. 2 at every predetermined timing (step S1), and this second clock switching command is supplied to the MPX8. Although not shown, the second clock switching command is supplied to the output register 6 and the switching command disables data input to the output register 6. The MPX8 supplies the second clock pulse to the output register 6 in response to the second clock switching command. As a result, the output register 6 shifts and outputs the held signal data in synchronization with the supplied second clock pulse. The signal data output as the shift is synchronized with the operation timing of the microcomputer 7. Therefore, the microcomputer 7 outputs the output register 6
The signal data from (1) is read (step S2), and when the reading is completed (step S3), a first clock switching command is generated (step S4). The MPX8 supplies the first clock pulse to the output register 6 in response to the first clock switching command. After generating the first clock switching command, the microcomputer 7 determines whether or not the coefficient data needs to be changed according to the signal data read from the output register 6 (step S5). For example, if the read signal data is data indicating the input average level, if the input average level is equal to or higher than a predetermined value, it is determined whether the first coefficient data group is used, and the input level is set to the predetermined value. If it is smaller than the value, the second value that is larger than the first coefficient data group
It is determined whether the coefficient data group is used. When it is necessary to change the coefficient data, a new coefficient data group is read from the ROM in the microcomputer 7 and transferred to the arithmetic processing unit 3 (step S6). The arithmetic processing unit 3 has a coefficient RAM 17 as described later, and the coefficient RAM 17
The stored contents of 17 are updated by the transferred coefficient data group. As a result, the filter characteristic as the calculation result in the calculation processing unit 3 is corrected.

FIG. 3 shows a schematic configuration of the arithmetic processing unit 3 including the interface 4 and the output registers 5 and 6 in the DSP 2. A digital signal is supplied from the A / D converter 1 to the input register 13. A data bus 14 is connected to the input register 13, and the data bus 14 is connected to one input of a data memory 22 for temporarily storing a data group and a multiplier 15. A buffer memory 16 for holding coefficient data is connected to the other input of the multiplier 15. A coefficient RAM 17 is connected to the buffer memory 16, and a coefficient data group is stored in the RAM 17. One coefficient data is sequentially read from the coefficient data group stored in the RAM 17 according to a timing signal from the sequence controller 20 described later,
It is supplied to the buffer memory 16 and held therein. The coefficient data held in the buffer memory 16 is supplied to the multiplier 15. The ALU (adder) 18 is provided for accumulating the calculation output of the multiplier 15, the calculation output of the multiplier 15 is supplied to one input, and the other is connected to the data bus 14. An accumulator 19 is connected to the calculation output of the ALU 18, and an output of the accumulator 19 is connected to the data bus 14. A memory control circuit 24 that controls data writing and reading of the external memory 23 is connected to the data bus 14. A delay time RAM 25 that stores a delay time data group is connected to the memory control circuit 24, and the memory control circuit 24 delays the audio signal data by each delay time data stored in the delay time RAM 25.
The input audio signal data is written to and read from.

Further, the output registers 5 and 6 are connected to the data bus 14.

The operations of the register 13, multiplier 15, coefficient RAM 17, ALU 18, accumulator 19, and memory control circuit 24 are controlled by the sequence controller 20. The sequence controller 20 operates according to the processing program written in the program memory 30, and operates according to a command from the microcomputer 7. Further, the microcomputer 7 controls the rewriting of the processing program and the rewriting of the coefficient data of the RAM 17 and the delay time data of the RAM 25 according to the key operation of the keyboard 11.

In the DSP 2 including the arithmetic processing unit 3 having such a configuration, the digital audio signal data is supplied to the data memory 22 via the input register 13 and stored therein. The sequence controller 20 reads the data from the input register 13, the timing of selectively transferring the data from the data memory 22 to the multiplier 15, the timing of outputting each coefficient data from the RAM 17, the multiplication operation timing of the multiplier 15, ALU18 add operation timing, accumulator 1
From the output timing of 9, the timing of outputting the data of the calculation result is taken.

By taking these timings, the audio signal data input from the data memory 22 is read and supplied to the memory control circuit 24 via the data bus 14. The memory control circuit 24 sequentially writes the supplied signal data in the external memory 23. Meanwhile, sequence controller
The delay time data is sequentially read from the delay time RAM 25 according to the timing signal from 20, and the signal data is sequentially read by the memory control circuit 24 when the delay time designated by the delay time data has elapsed. Each read signal data is stored in the data memory via the data bus 14.
It is supplied to 22 and sequentially stored as delayed signal data.

The audio signal data stored in the data memory 22 or the delay signal data obtained by the above data delay processing is sequentially read and supplied to the multiplier 5. on the other hand,
The coefficient data is sequentially read from the RAM 17 and supplied to and held in the buffer memory 16. The coefficient data from the buffer memory 16 and the data from the data memory 22 are multiplied by the multiplier 15
, And they are successively multiplied in the multiplier 15. The value obtained by this multiplication is accumulated in the ALU 18 with the value up to the previous time (the value held in the accumulator 19), and the operation result is held in the accumulator 19. In this way, data such as initial reflected sound data and filter characteristic processing data is created.

In the above-described embodiment, the data held in the output register 6 is stored in the microcomputer 7 at every predetermined timing.
Is read by, for example, the arithmetic processing unit 3
The retained data may be read by the microcomputer 7 at the timing when the processing result is obtained.

Further, in the case where the data stored in the output register 6 read by the microcomputer 7 is the data indicating the average value of the input signal, the program of the DSP 2 causes the arithmetic processing unit 3 to generate the average value data in a part of the arithmetic processing operation. Preformed.

As described above, according to the present invention, the clock pulse for outputting the held data from the holding means for holding the output data of the arithmetic processing means is synchronized with the operation timing of the arithmetic processing means according to the switching command. From one clock pulse to the first
Switching to a second clock pulse having a lower frequency than the clock pulse is performed. Therefore, the data held by the holding means can be output at a lower speed than the processing timing of the DSP. Therefore, it becomes possible for the control means such as a microcomputer to directly read the data output from the DSP, and thus, for example, the contents of the coefficient memory and the delay time memory can be updated according to the read data, and the DSP can be further improved. It can be used effectively.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a flow chart showing the operation of a microcomputer, and FIG. 3 is a block diagram schematically showing the configuration of an arithmetic processing unit. Is. Description of main part code 1 …… A / D converter 2 …… DSP 3 …… Computational processing unit 4 …… Interface 5,6 …… Output register

Front page continuation (72) Inventor Kazuo Watanabe 465 Osato-cho, Kofu-shi, Yamanashi Pioneer Video Co., Ltd. Semiconductor factory (56) Reference JP 63-211826 (JP, A) JP 64-88616 (JP) , A)

Claims (1)

[Claims] 1. An arithmetic processing means for performing high-speed arithmetic processing on an input digital signal in accordance with a predetermined program and outputting the same, and holding data for holding the output data of the arithmetic processing means and outputting the held data at a timing synchronized with a supplied clock pulse. A digital signal processing device comprising a holding means and a clock pulse generating means for supplying to the holding means a first clock pulse synchronized with the operation timing of the arithmetic processing means, the digital signal processing apparatus according to the output data of the holding means. The control means controls the arithmetic processing means, the control means generates a switching command when reading the output data of the holding means, and the clock pulse generating means has a frequency lower than that of the first clock pulse and the data by the control means. The holding means holds the second clock pulse at a readable timing in response to the switching command. Digital signal processing device and supplying.