JPH0631996B2 - Audio signal data processor - Google Patents

Description

TECHNICAL FIELD The present invention relates to an audio signal data processing device.

BACKGROUND ART An audio signal data processing device capable of controlling a sound field to create a reverberant sound or a realistic sensation in a concert hall or a theater at home or in a car is well known, for example, JP-A-64-72615. It is shown in the publication. Such an audio signal processing device is provided with a DSP (digital signal processor) for performing sound field control by digitally processing an audio signal output from an audio signal source such as a tuner. The DSP is capable of repeatedly performing arithmetic processing such as four arithmetic operations at high speed.

However, in order to finely control the sound field, if the digital processing speed is increased, an expensive element needs to be used, and the cost reduction of the DSP has been a problem.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an audio signal data processing device capable of performing sound field control with sufficient accuracy even when a low-speed element is used.

The audio signal data processing device of the present invention comprises an input means for sequentially supplying the audio signal data, a first data memory, and a first data memory for writing the audio signal data to the first data memory and reading the audio signal data from the first data memory. The data memory control means, the second data memory, the second data memory control means for writing audio signal data to the second data memory and reading the audio signal data from the second data memory, and the first and second data memories. Arithmetic means for multiplying audio signal data written in at least one of them by a predetermined coefficient, output means for outputting audio signal data according to the arithmetic result of the arithmetic means, input means, output means, first and A first data bus for transferring audio signal data between the second data memory and the arithmetic means, and a delay Memory, delay memory control means for controlling writing and reading with respect to the delay memory so as to delay the audio signal data read from the second data memory by a predetermined time, and audio between the second data memory and the delay memory. And a second data bus for transferring signal data.

Embodiment Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

In the audio signal data processing apparatus according to the embodiment of the present invention shown in FIG. 1, the analog audio signal is A
It is supplied to the input / output interface 3 in the DSP 2 via the / D converter 1. A first data bus 4 is connected to the input / output interface 3. Two signal data RAMs 5 and 6 are connected to the first data bus 4 as data memories for storing audio signal data. A buffer memory 7 is connected to the data bus 4, and the output of the buffer memory 7 is connected to one input of the multiplier 8. A buffer memory 9 for holding coefficient data is connected to the other input of the multiplier 8, and the buffer memory 9 is further connected to a coefficient data RAM 10 for storing a plurality of coefficient data. ALU (calculator) 1
Reference numeral 1 is provided for performing calculation such as accumulation of the calculation output of the multiplier 8, and the calculation output of the multiplier 8 is supplied to one input. The output of the accumulator 12 holding the calculation output of the ALU 11 is supplied to the other input. The output of the accumulator 12 is connected to the data bus 4.

A memory control circuit 31 is connected to the signal data RAM 5. The memory control circuit 31 generates a control signal for controlling writing of data to a specified address of the RAM 5 and reading of data from the specified address. Signal data RAM
6 includes a memory control circuit 32 similar to the memory control circuit 31.
Are connected via the switching circuit 33. Switching circuit 33
Is a RAM 6 according to a control signal from the memory control circuit 31.
The writing is switched to the designated address and the data is read from the designated address. A memory control circuit 34 similar to the memory control circuit 31 is connected to the RAM 10.

The signal data RAM 6 is also connected to a second data bus 14 different from the first data bus 4. Specifically, as shown in FIG. 2, 3-state buffers 39a and 39b are provided between the RAM 6 and the first data bus 4, and RA is also provided.
Three-state buffers 40a and 40b are provided between M6 and the second data bus 14. Buffer 39a,
39b, 40a, 40b are individually turned on / off in response to a command signal from the sequence controller 18 described later. That is, the signal data from the first data bus 4 is transferred to the RAM 6
When writing to RA, the buffer 39a is turned on and RA
When reading the signal data from M6 to the first data bus 4, the buffer 39b is turned on. Similarly, when writing the signal data from the second data bus 14 to the RAM 6, the buffer 40a is turned on, and when reading the signal data from the RAM 6 to the second data bus 14, the buffer 40a is turned on.
b is turned on. In this way, the three-state buffers 39a, 39b, 40a, 40 which are turned on in response to the command signal are
It is always any one of b.

An interface 16 for data transfer with an external RAM 15 is connected to the data bus 14. External RAM1
Reference numeral 5 denotes a delay memory provided to create delayed signal data of audio signal data, and the larger the storage capacity, the longer the delay data can be created. A memory control circuit 35 is provided for designating write and read addresses of the RAM 15, and the delay time data RAM 17 is connected to the memory control circuit 35. Writing and reading of delay time data in the RAM 17 is controlled by the memory control circuit 38.

Interfaces 3, 16, multiplier 8, buffer memories 7, 9, ALU 11, accumulator 12, memory control circuits 31, 32, 34, 35, 38 and switching circuit 33.
The operation of is controlled by the sequence controller 18. Program RAM for the sequence controller 18
19 is connected and operates according to the program written in the program RAM 19. Program RAM
A program counter 20 is connected to 19 and the instruction code of the step corresponding to the new count value is added to the program RA every time the count value of the program counter 20 is added.
It is read from M19 and supplied to the sequence controller 18. Further, the sequence controller 18 is connected to a register 21 which holds a plurality of commands from a microcomputer 24 described later.

The program RAM 19 and the register 21 are the main bus 2
2 are each connected. A microcomputer 24 is connected to the main bus 22 via an interface 23. Further, the transfer buffer 2 is attached to the main bus 22.
6, 27 are connected. The transfer buffer 26 is a RAM for the coefficient data supplied from the microcomputer 24.
Hold temporarily for storage in 10. The transfer buffer 27 temporarily holds the delay time data supplied from the microcomputer 24 for storage in the RAM 17.

The microcomputer 24 is a microprocessor, RA
It is composed of an M, a ROM and an interface (both not shown). A keyboard 25 is connected to the microcomputer 24. The keyboard 25 has a plurality of mode keys for designating sound field modes such as hall 1, hall 2 having different sound field characteristics, a frequency band setting key for graphic equalizer adjustment, a level adjustment key and a mute key (both not shown). , Etc. are provided. In the ROM of the microcomputer 24, in addition to the DSP control program processed by the microcomputer 24 itself, a plurality of sequence control programs processed by the sequence controller 18, a plurality of coefficient data groups supplied to the RAM 10, and a read address setting supplied to the RAM 17. A plurality of delay time data groups are written in advance.

A clock generator 28 is provided in the DSP 2, and clock pulses are sent from the clock generator 28 to the sequence controller 18 and the program counter 20.
Is supplied to. A clock pulse generated from the clock generator 28 is supplied as a timing signal for sampling the A / D converter 1.

The audio signal data output from the interface 3 is supplied to the mute switch circuit 30. When the mute switch circuit 30 is turned on, the audio signal data is further supplied to the D / A converter 37 via the digital filter 36. ON / OFF of the mute switch circuit 30 is controlled by a command signal output from the sequence controller 18.

In such a configuration, the above-mentioned 3-state buffer 39
In addition to the command signals for turning on / off the a to 40b and the mute switch circuit 30, the sequence controller 18 transfers the command signal for transferring the coefficient data group held in the transfer buffer 26 to the RAM 10 and the address data group held in the transfer buffer 27. Command data to be transferred to the RAM 17, signal data R of audio signal data from the interface 3
RAM 10 for transferring instruction signals to designated addresses of AM 5 and 6 and signal data for reading signal data from designated addresses of RAM 5 and 6 and transferring to buffer memory 7.
Command signals for reading coefficient data from the designated address of the ALU 11 and transferring them to the buffer memory 9, various operation operation command signals of the ALU 11, and transfer of the signal data held in the accumulator 12 to the designated addresses of the signal data RAMs 5 and 6 or to the buffer memory 7. Command signal, transfer command signal from designated address of signal data RAM 6 to write designated address of external RAM 15, transfer command signal from delayed designated address of external RAM 15 to designated address of signal data RAM 6, RAM 5, 6 and external RAM 15 are initialized A command signal such as a reset command signal for performing the operation is generated. These command signals are generated at appropriate timing according to a command from the microcomputer 24 or a program stored in the program RAM 19. Since the command from the microcomputer 24 is held in the command register 21, the sequence controller 18 monitors the content of the command register 21 during the operation according to the program, and the interrupt signal causes the command signal to the command from the microcomputer 24. Occurs. The command held in the command register 21 is canceled by, for example, the sequence controller 18 when a command signal corresponding to the command is generated.

When one of the mode keys of the keyboard 25 is operated, the microcomputer 24 determines whether or not the mode key for designating a sound field mode different from the current sound field mode is operated as shown in FIG. 3 (step 41). When the sound field mode different from the current sound field mode is designated, the mute command is directly issued to turn off the mute switch circuit 30 to enter the mute state.
(Step 42), the sequence control program corresponding to the operated key, the coefficient data group α ₁ ,
α ₂ ...... α _n and delay time data group t ₁ , t ₂ ...... t _n
Is read from the ROM and transferred (steps 43 to 4).
5). Interface 2 for sequence control program
3, and is transferred to the RAM 19 via the main bus 22 and written by a memory write control circuit (not shown). The coefficient data group is transferred to the transfer buffer 26 via the interface 23 and the main bus 22. The delay time data group is transferred to the transfer buffer 27 via the interface 23 and the main bus 22. When the coefficient data and the delay time data are transferred to the transfer buffers 26 and 27 in this manner, the microcomputer 24 issues a data switching command to the sequence controller 18 (step 46) and further an initialization command (step 47). ). The sequence controller 18 generates a predetermined command signal to the memory control circuits 34 and 38 in response to the data switching command to write the coefficient data group transferred to the transfer buffer 26 into a predetermined area of the RAM 10, and also transfers the transfer buffer 27. The delay time data group transferred to is written in a predetermined area of the RAM 17. Further, since the sequence controller 18 generates the above reset command signal to the memory control circuits 31, 32 and 35 in response to the initialization command, the signal data RAMs 5 and 6 and the external RAM 15 are controlled by the memory control circuits 31, 32 and 35. "0" is written in all the storage areas of.

After execution of step 47, a mute release command for turning on the mute switch circuit 30 to release the mute state is issued to the sequence controller 18 (step 48). That is, the mute switch circuit 3
0 is turned off only during a period in which the data and programs in the RAMs 10, 17 and 19 are changed to switch the current sound field mode to another sound field mode. This is to prevent the output of a noise signal caused by a change in data or program.

It should be noted that the microcomputer 24 does not generate an initialization command, but the sequence controller 18 generates a command signal for data transfer to the RAMs 10 and 17 in response to the data switching command, and then generates a reset command signal. May be.

Next, the signal data processing operation in the DSP 2 will be described. The audio signal input to the A / D converter 1 is converted into a group of digital audio signal data d ₁ , d ₂ ... D _n at every sampling period synchronized with the clock pulse from the clock generator 28, and the audio signal data group is converted. Are supplied to the first data bus 4 via the interface 3. The signal data group supplied to the data bus 4 is supplied to and stored in the RAM 5 or 6.

The signal data written in the RAM 6 is sequentially transferred to an output register (not shown) in the interface 16 by the data bus 14, and the output register further outputs an external R signal.
It is designated by the write address of the AM 15 and written in the storage location. This write address is the memory control circuit 35.
The number of addresses corresponding to the number of storage positions of the external RAM 15 is controlled in accordance with each transfer signal data in a predetermined order. The signal data at the storage location designated by the read address is read in the external RAM 15 and transferred to an input register (not shown) in the interface 16. As the read address, since the delay time data stored in the RAM 17 is read by the memory control circuit 38 and supplied to the memory control circuit 35, the write address is used as a reference according to the delay time data supplied in the memory control circuit 35. Is set to. That is, the delay time causes a delay time between the write timing of one signal data to the RAM 15 and the read timing thereof. The signal data transferred and held in the input register in the interface 16 is transferred to the signal data RAM 6 by the data bus 14. This external RAM1
By the transfer operation with 5, the delayed audio signal data for controlling the sound field, that is, the initial reflected sound data is created.

On the other hand, the coefficient data read from the RAM 10 is supplied to and held in the buffer memory 9. The signal data is transferred from the RAM 5, 6 or the accumulator 12 to the buffer memory 6 by the sequence controller 18 taking appropriate timing, and the multiplier 8 holds the signal data held in the buffer memory 6 and the buffer memory 9. And the coefficient data thus obtained are multiplied. For example, the signal data groups d ₁ , d ₂ ... D _n and the coefficient data groups α ₁ , α
₂ ... When performing the multiply-accumulate operation with α _n , first, d ₁ is held and output to the buffer memory 6 and α is output to the buffer memory 9.
₁ is held and outputted, α ₁ · d ₁ is calculated in the multiplier 8, 0 is added to this α ₁ · d ₁ in the ALU 11, and the calculation result is held in the accumulator 12. Then, d ₂ is held and output to the buffer memory 6, α ₂ is held and output to the buffer memory 9, and the multiplier 8
When α ₂ · d ₂ is calculated in, the accumulator 12 outputs α ₁ · d ₁ and the ALU 11 outputs α ₂ · d _2.
1 · d ₁ + α ₂ · d ₂ is calculated. By repeating this Is calculated. this Is output from the interface 3.

As shown in FIG. 4, right channel graphic equalizer (GEQ) processing, left channel sound field control (SFC) processing, left channel graphic equalizer processing, and right channel sound field control. The processing is repeated in the order of processing. These four processes are processes using the first data bus 4. On the other hand, the above-described processing of creating delayed audio signal data is performed in parallel with the graphic equalizer processing and the sound field control processing.
That is, as shown in FIG. 4, during the graphic equalizer processing of the right channel and the sound field control processing of the left channel, a delayed audio signal for sound field control processing of the right channel is transferred from the external RAM 15 to the signal data RAM 6 by the second data bus. During the data transfer process, and during the graphic equalizer process for the left channel and the sound field control process for the right channel, the external RAM 1 is operated by the second data bus.
The transfer processing of the delayed audio signal data for the sound field control processing of the left channel from 5 to the signal data RAM 6 is performed.

In the case of the graphic equalizer processing, the RAM 10 stores the coefficient data corresponding to the level of each frequency band of the left and right channels which is preset by the key operation for the graphic equalizer. RA when calculating for each frequency band
The coefficient data is sequentially read from M10 and transferred to the buffer memory 9. On the other hand, the memory control circuit 31 specifies the read address of the RAM 5 for each execution step, and the signal data is read from the specified address and transferred to the buffer memory 7 via the data bus 4.

For example, the operation of the graphic equalizer for one frequency band is as follows. First, in the first step, the signal data d ₁₂ is read from the address 12 _H of the RAM 5, and the read signal data d ₁₂ and the set coefficient data α ₀ are transferred to the buffer memories 7 and 9, whereby the multiplier 8 To multiply. In the third step, which is two steps after the first step, 0 is added to the multiplication result α ₀ · d ₁₂ by the ALU 11, and the addition result is held in the accumulator 12.

In the second step, the signal data d ₁₁ is read from the address 11 _H of the RAM 5, and the multiplier 8 multiplies the read signal data d ₁₁ and the set coefficient data α ₀ . In the fourth step, the holding value of the accumulator 12 (addition result of the third step) is added to the multiplication result α ₀ · d ₁₁ and the addition result is held in the accumulator 12. Next, in the third step, the stored value (final calculation value of one frequency band) EQ _n-1 of the accumulator 12 three steps before is stored in the RAM 5
10 _H address and the buffer memory 7, and the coefficient data α ₀ is multiplied by the multiplier 8. The multiplication result α ₀ ·
In the fifth step, the holding value of the accumulator 12 (the addition result of the fourth step) is added to EQ _n-1 and the addition result is stored in the accumulator 12
Held in.

In the fourth step, the signal data d ₁₄ is read from the address 14 _H of the RAM 5, and the multiplier 8 multiplies the read signal data d ₁₄ and the set coefficient data α ₀ . The value held in the accumulator 12 (addition result in the fifth step) is added to the multiplication result α ₀ · d ₁₄ by the ALU 11 in the sixth step, and the addition result is held in the accumulator 12. And in the fifth step read signal data d ₁₃ from 13 _H address of RAM 5, thereby multiplying the signal data d ₁₃ coefficient data alpha ₀ which is set and read by the multiplier 8. In the seventh step, the ALU 11 adds the holding value of the accumulator 12 (the addition result of the sixth step) to the multiplication result α ₀ · d ₁₃ , and the addition result is held in the accumulator 12. In this way, audio signal data for one frequency band of the graphic equalizer is obtained, and the same operation as above is performed for the set frequency band. Although not shown, a shifter is provided in the output stage of the multiplier 8 so that the multiplication result of the multiplier 8 is supplied to the ALU 11 at an appropriate timing.

Next, the switching operation of the switching circuit 33 will be described. When the processing operation of the DSP 2 is changed by a key operation, the microcomputer 24 operates as shown in FIG.
It is determined whether or not the process uses 5 (step 5).
1). For example, when the sound field control process described above is performed, the external RAM 15 is used, and only the graphic equalizer process or the filter process is performed by the external RAM 1.
This is a process that does not use 5. In the case of processing using the external RAM 15, a memory independent use command is issued to the sequence controller 18 (step 52) and the external RA is used.
If the process does not use M15, a memory sharing command is issued to the sequence controller 18 (step 53). These commands are held in the register 21.
The sequence controller 18 generates a command signal for switching the switching circuit 33 in accordance with the command content regarding the memory held in the command register 21. That is, in the case of the memory independent use instruction, the control signal from the memory control circuit 32 is R
The memory control circuit 32 controls the writing and reading of the signal data RAM 6 when it is supplied to the AM 6 and performs the sound field control process or the sound field control process and the graphic equalizer process in parallel as described above.
On the other hand, in the case of the memory sharing command, the control signal is supplied from the memory control circuit 31 to the RAMs 5 and 6, and in the case of the graphic equalizer processing which does not use the external RAM or the processing of only the filter processing, the writing and writing of the signal data RAMs 5 and 6 are performed. The reading is controlled by the memory control circuit 31.
Therefore, the memory control circuit 31 specifies the address of the RAM 6 in addition to specifying the write and read addresses of the RAM 5. For example, if the write address exceeds the upper limit address of RAM 5 when writing to RAM 5, RAM
Therefore, the writing is shifted to the writing by the address designation of No. 6.

Next, the operation when the mute key of the keyboard 25 is operated will be described. Microcomputer 24
When the mute key is operated, it judges whether or not it is in the mute state as shown in FIG. 6 (step 6).
1). This is determined from the contents of the mute flag F _M. If not in the mute state, F _M = 0, so a mute command is generated (step 62) and 1 is set in the mute flag F _M (step 63). Since the mute command is held in the command register 21, the sequence controller 18 turns off the mute switch circuit 30. On the other hand, in the case of the mute state, F _M = 1 so that the mute release command is generated (step 64) and the mute flag F _M is reset to 0 (step 65). The mute release command is command register 2 instead of the mute command.
Since it is held at 1, the sequence controller 18 turns on the mute switch circuit 30.

Therefore, when the mute key is operated, the mute switch circuit 30 is turned off, and when the mute key is operated again, the mute switch circuit 30 is turned on. While the mute switch circuit 30 is off, the sequence controller 18 continues the instruction generating operation according to the program.

As described above, in the audio signal data processing device of the present invention, the transfer of the audio signal data among the input means, the output means, the first and second data memories, and the arithmetic means is performed on the first data bus. , The transfer of the audio signal data for creating the delay data between the second data memory and the delay memory is performed by the second data bus, so that the data transfer of different data can be performed by the first and second data buses independent of each other. The delay processing operation by the delay memory and the coefficient multiplication operation by the arithmetic means can be performed in parallel. Therefore, it is possible to perform the sound field control with sufficient accuracy without using a high-speed digital processing speed by using an expensive element and to have a function such as a graphic equalizer.

[Brief description of drawings]

1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram partially showing the device of FIG. 1, FIG.
5 and 6 are flow charts showing the operation of the microcomputer in the apparatus of FIG. 1, and FIG. 4 is a view showing the order of each processing operation. Description of symbols of main parts 2 ... DSP 4, 14 ... Data bus 5, 6 ... Signal data RAM 7, 9 ... Buffer memory 8 ... Multiplier 10 ... Coefficient data RAM 11 ... ALU 12 ... Accumulator 17 ... Delay time data RAM 18 ... Sequence controller

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuo Watanabe 465 Osato-cho, Kofu-shi, Yamanashi Pioneer Video Co., Ltd. Semiconductor factory (56) References JP 63-64096 (JP, A) JP 64-64 72615 (JP, A) JP-A-2-132497 (JP, A)

Claims (1)

[Claims] 1. Input means for sequentially supplying audio signal data, a first data memory, and first data memory control for writing audio signal data to the first data memory and reading from the first data memory. Means, a second data memory, a second data memory control means for writing audio signal data to the second data memory and reading the audio signal data from the second data memory, and the first and second data memories. Arithmetic means for multiplying the audio signal data written in at least one of them by a predetermined coefficient, output means for outputting audio signal data according to the arithmetic result of the arithmetic means, the input means, the output means, First data for transferring audio signal data between the first and second data memories and the arithmetic means A delay memory, a delay memory, delay memory control means for controlling writing and reading to and from the delay memory so as to delay the audio signal data read from the second data memory by a predetermined time, and the second data memory. And a second data bus for transferring audio signal data between the delay memories.