JPH0779161A - A/d converter - Google Patents

Abstract

PURPOSE:To reduce the number of exclusive OR gates and to decrease the number of components, power consumption and a chip area by comparing a high level voltage in a noninverting output voltage and an inverting output voltage with a reference voltage and latching the higher voltage. CONSTITUTION:Since Va, CVb are inputted to inputs D1, D2 of a latched comparator LC, an output of a wired OR circuit 9a comprising transistors (TRs) Q2, Q3 indicates equivalently a V-shaped waveform. On the other hand, an output voltage Vx of a reference voltage generating circuit 8 is inputted to a base of the TR Q1 of the latched comparator LC, that is, an input DB as a reference voltage. Thus, the output Q of the latched comparator LC goes to an H level in the case of Vrb<Vin<Vra and goes to an L level in other cases. In this case, since the latched comparator LC itself makes exclusive logical operation, it is possible to eliminate the need for other exclusive OR gates.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog / digital converter for converting an analog signal into a digital signal, and more particularly to an improvement of a parallel type structure.

[0002]

2. Description of the Related Art A block diagram of a conventional parallel type analog-digital converter is shown in FIG. 11 (three-bit example). In the figure, reference numeral 1 is a reference resistor section in which reference resistors are arranged in series, and 2 is a pre-amplifier consisting of a plurality of pre-amplifiers PA1 to PA7.
An amplifier row 3, a latched comparator row composed of the same number of latched comparators LC1 to LC7 as the pre-amplifiers PA1 to PA, an exclusive OR gate row composed of a plurality of exclusive OR gates EX1 to EX, and a reference numeral 5 An analog input unit to which an analog input voltage Vin to be converted is introduced, 6 is D
An encoder consisting of three bit lines of 0, D1 and D2,
Reference numeral 7 is a dotting transistor for driving the bit line. An analog input voltage Vin is commonly input to one input terminal of each of the preamplifiers PA1 to PA7,
A reference voltage generated by being divided by each reference resistor of the reference resistance unit 1 is input to the other input terminal. Thus, conventionally, each of the preamplifiers PA1 to PA7
The same number of latched comparators LC1 to LC7 receive the output of the above. Then, an exclusive OR between the outputs of the latched comparators adjacent to each other is calculated through the exclusive OR gate row 4, and the encoder is driven through the dotting transistor based on the output to perform coding. (A 3-bit Gray code is generated in this conventional example).

[0003]

However, as shown in FIG.
In the conventional analog-digital converter shown in FIG. 1, the same number of latched comparators LC1 as the pre-amplifiers PA1 to PA7 are provided.
~ 7 and exclusive OR gates EX1 to EX7 are required, the number of latched comparators and the number of exclusive OR gates increase significantly as the resolution of the analog-to-digital converter increases. There was a drawback that the number and power consumption became huge.

The present invention has been made in view of the above problems, and an object thereof is to provide a non-inverted output voltage of one pre-amplifier among a plurality of pre-amplifiers and another pre-amplifier by a latched comparator. By reducing the number of latched comparators and exclusive OR gates required by comparing the voltage on the higher potential side of the inverted output voltage of the amplifier with a predetermined voltage and latching it, The goal is to significantly reduce the number, power consumption, and chip area.

[0005]

In order to achieve the above-mentioned object, the means of the invention as claimed in claim 1, 2 or 3 is such that one input section receives a common analog signal and the other input section successively receives. A plurality of pre-amplifiers configured to receive a reference voltage signal set with a predetermined voltage difference and generate complementary non-inverted voltage signals and inverted voltage signals;
An analog-to-digital converter including a plurality of latched comparators that receive the output of an amplifier and a coding means that performs coding based on the digital output of the latched comparators.

In addition to the basic structure described above, the means of the present invention is provided with a reference voltage generating circuit for generating a reference voltage signal corresponding to the balanced point of the complementary output voltages of the preamplifier. . Then, at least one group of the latched comparators is provided with a non-inverted voltage signal from one preamplifier of the plurality of preamplifiers and an inverted voltage signal from another preamplifier and the above reference. It has three input sections to which a reference voltage signal from the voltage generation circuit is inputted, and is configured to compare and latch the high-potential-side voltage of the non-inverted output voltage and the inverted output voltage with the reference voltage. It was done.

According to a second aspect of the present invention, in addition to the basic configuration described above, a non-inverted voltage signal from one preamplifier among the plurality of preamplifiers and another preamplifier from another preamplifier are used. Of the pre-amplifier and an OR circuit that has two input sections for receiving the inverted output voltage of the above-mentioned, and generates an output voltage corresponding to the higher potential side voltage of the non-inverted output voltage and the inverted output voltage. And a reference voltage generating circuit for generating a reference voltage signal corresponding to the balanced point of the dynamic output voltage. The latched comparator has two input sections to which the output signal of the OR circuit and the output signal of the reference voltage generating circuit are input, and compares the output voltage of the OR circuit with the reference voltage. It is configured to latch.

According to a third aspect of the present invention, in addition to the basic configuration described above, a non-inverted voltage signal from one preamplifier among the plurality of preamplifiers and another preamplifier from another preamplifier are used. Of the non-inverted output voltage and the inverted output voltage, and an OR circuit for generating an output voltage corresponding to a voltage on the higher potential side of the non-inverted output voltage and the pre-amplifier. And a pair of input sections to which the complementary voltage (non-inverted output voltage) of the non-inverted output voltage generated by the above and the complementary voltage (non-inverted output voltage) of the inverted output voltage generated by the other pre-amplifier are input. Then, an AND circuit that generates an output voltage according to the voltage on the lower potential side of the two input voltages is provided. The latched comparator is the OR
The output voltage of the circuit and the output voltage of the AND circuit are compared and latched.

According to the invention of claim 4, in the invention of claim 1, 2 or 3, the non-inverted output voltage and the inverted output voltage of each of the preamplifiers are switched between logics of digital output signals. The complementary output voltages intersect at an input voltage corresponding to
The output of the latched comparator is directly coded.

[0010]

With the above construction, in the invention of claim 1, the output of the three-input latched comparator becomes the H level when the input voltage is between the input voltages at the equilibrium points of the two predetermined complementary output voltages, and the input is When the voltage is in the other region, a signal that becomes L level is obtained. That is, the latched comparator itself performs an exclusive OR operation, and an analog signal can be converted into a digital signal without an exclusive OR gate. Therefore, the exclusive OR gate is not required, and the number of elements and power consumption can be significantly reduced.

According to the second aspect of the present invention, the OR circuit outputs the OR logic of the non-inverted output voltage of one pre-amplifier and the inverted output voltage of the other pre-amplifier. Therefore, the same effect as that of the first aspect can be obtained, and highly reliable conversion is possible even when operated at high speed.

In the invention of claim 3, the output of the OR circuit is V
Since the waveform becomes a V shape and the output of the AND circuit becomes a Λ waveform, the pair of inputs of the latched comparator become completely complementary signals, and the differential gain at the intersection of both waveforms is 2
Double. Therefore, the same effect as that of the first aspect can be obtained, and highly reliable and highly accurate conversion can be performed.

According to a fourth aspect of the present invention, in the above-mentioned first, second or third aspect of the invention, the input of the latched comparator is taken from the complementary output voltage corresponding to the transition of the logic of the digital output. -It is possible to directly code with the output of the comparator. Therefore, the number of elements such as the exclusive OR gate and the latched comparator and the power consumption can be significantly reduced.

[0014]

EXAMPLES Examples of the present invention will be described below.

(Embodiment 1) First, Embodiment 1 according to the invention of claim 1 will be described with reference to FIGS.

FIG. 1 shows a basic configuration of a pre-amplifier and a latched comparator in an analog-digital converter according to a first embodiment. Reference numeral 1 is a reference resistor arranged in series and different reference voltages Vra and Vrb (Vra). > Vrb), a reference resistor section configured to generate a preamplifier PA (a) and a preamplifier row including a plurality of preamplifiers PA (b), and LC has three inputs D1. , D
2, a latched comparator 5 having DB, and 5 are signal input sections to which the analog input signal Vin is introduced.

Each of the above preamplifiers PA (a), PA
One input section of (b) is connected to the signal input section 5, and the common analog input signal Vin is input. Also,
The other input portion of each preamplifier PA (a), PA (b) is connected to a predetermined portion of the reference resistance portion 1 and receives the reference voltages Vra, Vrb, respectively. Also,
In one preamplifier PA (a), the non-inverted output voltage V
a and the inverted output voltage CVa are
In (b), the non-inverted output voltage Vb and the inverted output voltage CV
b is generated.

A wired OR circuit 9a is provided in the latched comparator LC. The wired circuit 9a is composed of two transistors Q2 and Q3 connected in parallel between the emitter and collector, the base of the transistor Q3 being the non-inverting output terminal of the one preamplifier PA (a). The base of the transistor Q2 is connected to the inverting output side terminal of the other preamplifier PA (b). That is, each of the above
The inverted output voltage CVb of one of the preamplifiers PA (b) of the amplifiers PA (a) and PA (b) is the transistor Q2.
It becomes the input D2 to the base of the other preamplifier PA
The non-inverted output voltage Va of (a) serves as the input D1 to the base of the transistor Q3.

Further, each preamplifier PA (a), PA
A reference voltage generating circuit 8 for generating a reference Vx corresponding to the output voltage at the balanced point of the complementary output in (b) is provided, and a transistor whose output is the input DB to the base is provided. Q1 is provided.
The latched comparator LC has inputs D1 and D
It is configured to compare and latch the higher voltage of the two and the voltage of the input DB. That is, the latched comparator LC has three input parts, and each input D1, D
It is configured as a 3-input latched comparator that compares and latches the voltage on the high potential side of D1 and D2 of 2 and DB with the input voltage DB.

FIG. 2A shows the analog input signal Vin.
Preamplifiers PA (a) and P for changes in (horizontal axis)
The characteristics of the output voltage of A (b) are shown respectively. Non-inverting output voltages Va, V of the pre-amplifiers PA (a) and PA (b)
b increases as the analog input voltage Vin increases,
The inverted output voltages CVa and CVb are the analog input voltage Vin.
Falls with the rise of. Also, the pre-amp PA
(A) Complementary output voltage (non-inverted and inverted output voltage) V
a and CVa, and the complementary output voltages Vb and CVb of the preamplifier PA (b) are reference voltages Vra and Vr, respectively.
It intersects at the input point of b, and the output voltage at this intersection corresponds to the above-mentioned reference voltage Vx.

With the above configuration, since Va and CVb are input to the inputs D1 and D2 of the latched comparator LC, respectively, the output of the wired OR circuit 9a formed by the transistors Q2 and Q3 is equivalent. 2 has a V-shaped waveform as shown by V (OR) in FIG. On the other hand, the output voltage Vx of the reference voltage generation circuit 8 is input as a reference voltage to the base of the transistor Q1 of the latched comparator LC, that is, the input DB. Therefore, the output Q of the latched comparator LC is H level when Vrb <Vin <Vra, and L level otherwise.

Therefore, by using the configuration of the pre-amplifier array 2 and the latched comparator LC described above, an analog-digital converter corresponding to the conventional analog-digital converter (see FIG. 11), that is, a gray code digital signal. When a 3-bit analog-to-digital converter that outputs is output is as shown in FIG. That is, FIG.
As is clear from comparison with the conventional example shown in FIG. 1, in this embodiment, since the latched comparators LC1 to LC7 themselves perform an exclusive OR operation, it is possible to delete all the exclusive OR gates. Becomes As a result, the number of elements, power consumption, and chip area can be significantly reduced.

(Second Embodiment) Next, a second embodiment according to the invention of claim 2 will be described with reference to FIG.

FIG. 4 shows the basic structure of the pre-amplifier and the latched comparator in the analog-digital converter in the second embodiment. The pre-amplifiers PA (a), P (a), P
On the output side of A (b), emitter followers made of NPN transistors are provided, respectively. That is,
The inverting output CVa of the pre-amplifier PA (a) is a transistor Q3, the non-inverting output Va is a transistor Q4, the inverting output CVb of the pre-amplifier PA (b) is a transistor Q5, and the non-inverting output Vb is a transistor Q6. An emitter follower is provided for each. The latched comparator LC is a normal latched comparator having a pair of input parts D and DB and comparing and latching two input voltages. Further, the emitters of the transistors Q4 and Q5 of the emitter follower are coupled by the wiring means CN1, and the input D of the latched comparator LC is obtained.
It is connected to the. The transistors Q4 and Q5, the constant current source connected to the emitters of the transistors, and the wiring means CN1 constitute an OR circuit 9b according to the invention of claim 2.

That is, the latched comparator LC is connected from the emitters of such two transistors Q4 and Q5.
The signal input to the input D of FIG. 2 is the same as that of the emitter output of the transistors Q2 and Q3 in the first embodiment.
It becomes a V-shape as shown in (b) (however, the absolute voltage level is lowered by the base-emitter voltage Vbe of the bipolar transistor).

In the second embodiment, the preamplifier PA
(A), PA (b) is provided with a reference voltage generating circuit 8 for generating a voltage (Vx-Vbe) lower than the output voltage Vx at the balanced point of complementary outputs by the base-emitter voltage, and the reference voltage generating circuit 8 is provided. The output voltage of the generation circuit 8, that is, the reference voltage (Vx-Vbe) is input as the input DB.
Therefore, the output Q of the latched comparator LC is V
H level when rb <Vin <Vra, L otherwise
This is a level, and the same effect as that of the first embodiment (the invention of claim 1) can be obtained. In addition, in the second embodiment, the OR logic is always taken by the provided OR circuit 9b.
Highly reliable conversion is possible even when operating at high speed.

(Third Embodiment) Next, a third embodiment according to the invention of claim 3 will be described with reference to FIGS.

FIG. 5 shows the basic structure of the pre-amplifier and the latched comparator in the analog-digital converter in the third embodiment.
As in the case of the second embodiment, the NPN is output to the output of A (b).
Each transistor has an emitter follower. That is, the inverting output CVa of the pre-amplifier PA (a) is a transistor Q3, the non-inverting output Va is a transistor Q4, the inverting output CVb of the pre-amplifier PA (b) is a transistor Q5, and the non-inverting output Vb is a transistor. An emitter follower of Q6 is provided. And the latched comparator LC is
It is a normal latched comparator which has a pair of inputs D and DB and compares and latches two input voltages. Also,
The emitters of the transistors Q4 and Q5 of the emitter follower are coupled by the wiring means CN2 and input to the emitter follower of the PNP transistor Q7, and the output of the emitter follower is connected to the input D of the latched comparator LC. The transistors Q4, Q5,
The OR circuit 9b according to the invention of claim 3 is constituted by the constant current power source and the wiring means CN2 connected to the emitters of the transistors Q4 and Q5.

Further, the AND circuit 10 according to the invention of claim 3 is constituted by the PNP transistors Q8 and Q9 which are emitter-coupled and the constant current source which is connected to the emitters of the respective transistors Q8 and Q9. The AND circuit 10
Pair of input parts (base of each transistor Q8, Q9)
Is connected to the emitters of transistors Q3 and Q6,
Its output is connected to the input DB of the latched comparator. The output of the above-mentioned OR circuit 9b is as shown in FIG.
As indicated by the solid line V (OR) in (b), a V-shaped waveform is clamped on the high potential side of the voltages Va and CVb. On the other hand, the output of the above-mentioned AND circuit 10 has a Λ-shaped waveform clamped on the low voltage side of the voltages of CVa and Vb, as shown by the broken line V (AND) in FIG. 6B. Also, the above 2
The two waveforms V (OR) and V (AND) are input voltage Vin.
Intersect at the reference voltages Vra and Vrb. Therefore, the output Q of the latched comparator LC is Vrb <
When Vin <Vra, it becomes H level, and when it is other than that, it becomes L level, and the same effect as that of the second embodiment (the invention of claim 2) can be obtained. In addition, in the present invention, two signals V (OR) and V (AN input to the latched comparator LC are input.
Since D) is completely complementary, the intensity of the output voltage is doubled as compared with the above embodiment due to the differential gain of the two input signals, and therefore the reliability is high even when operating at high speed. In addition, highly accurate conversion is possible.

(Fourth Embodiment) Next, a fourth embodiment according to the present invention will be described with reference to FIGS. 7 and 8.

FIG. 7 shows an analog circuit according to the invention of claim 1.
This is an example in which a digital converter is configured and a 3-bit Gray code is generated. In FIG. 7, the non-inverting output of the preamplifier PA1 and the inverting output of PA3 are connected to the inputs D1 and D2 of the first latched comparator LC1, and the output of the first latched comparator LC1 is the dotting transistor DT1. Drive encoder line D0 via. Similarly, the non-inverting output of the preamplifier PA5 and the inverting output of PA7 are connected to the inputs D1 and D2 of the fourth latched comparator LC4,
The output of the fourth latched comparator LC4 drives the encoder line D0 via the dotting transistor DT4. That is, in the encoder line D0, the input voltage Vin is Vr7 <Vin <
When Vr5 and Vr3 <Vin <Vr1, it becomes H level. Also, the input D of the second latched comparator LC2
The non-inverting output of the pre-amplifier PA2 and the inverting output of the pre-amplifier PA6 are connected to 1 and D2, respectively, and the output of the second latched comparator LC2 is supplied to the encoder line D via the dotting transistor DT2.
It is designed to drive one. That is, in the encoder line D1, the input voltage Vin is Vr6 <Vin <V
It becomes H level at r2. On the other hand, the pre-amplifier PA is connected to the inputs D and DB of the third latched comparator LC3.
4 is connected to the third latched comparator L
The output of C3 is adapted to drive the encoder line D2 via the dotting transistor DT3. That is, the encoder line D2 receives the input voltage Vi
It goes high when n is Vr4 <Vin.

With the above configuration, a digital signal as shown in FIG. 8 is generated in the encoder. That is, with respect to the change of the input voltage Vin, when Vin <Vr7 is (0,0,0), when Vr7 <Vin <Vr6 is (0,0,1), when Vr6 <Vin <Vr5 ( 0,1,1), (0,1,0) when Vr5 <Vin <Vr4, (1,1,0) when Vr4 <Vin <Vr3, and (1,1 when Vr3 <Vin <Vr2. 1, 1), (1, 0, 1) when Vr2 <Vin <Vr1, and (1, 0, when Vr1 <Vin
0), and a 3-bit Gray code will be generated.

Therefore, in the fourth embodiment, in addition to the effect of omitting the exclusive OR gate similar to the above-mentioned respective embodiments, the number of latched comparators is changed from the conventional seven (the same number as the number of pre-amplifiers). The effect that it can be reduced to four can be obtained.

Although the fourth embodiment has shown the configuration for generating a 3-bit gray code, the present invention is not limited to this embodiment, and an n-bit gray code can be easily generated. it can. In that case, (2 ⁿ −
1) The required number of latched comparators is 2 ^n-1 . Moreover, since it is not necessary to take an exclusive OR between the outputs of the latched comparators, all (2 ⁿ -1) exclusive OR gates can be deleted. Therefore,
It is possible to significantly reduce the number of elements, power consumption, and chip area.

It should be noted that the present invention can similarly generate codes other than the Gray code, such as binary code.

The coding of the fourth embodiment can also be applied to the inventions of claims 2 and 3. 9 and 10 show examples in which the invention of claim 4 is applied to the inventions of claims 2 and 3, respectively, and in each case, in addition to the effects of the inventions of claims 2 and 3, The number of latched comparators can be reduced.

[0037]

As described above, according to the invention of claim 1, a plurality of pre-processors for receiving a common analog signal and a reference voltage and generating complementary non-inverted voltage signals and inverted voltage signals. As an analog-digital converter equipped with an amplifier, a plurality of latched comparators and a coding means, while generating a reference voltage corresponding to the balanced point of the complementary output voltage of the pre-amplifier through a reference voltage generation circuit, The latched comparator is a three-input latched comparator, and the high-potential side voltage and the reference voltage of the non-inverted output voltage generated by one of the pre-amplifiers and the inverted output voltage generated by the other pre-amplifier are used. Since it is configured to compare and latch, the output of the latched comparator has the input voltage between the input voltages at the equilibrium point of the two complementary output voltages. The exclusive OR output can be set to the H level and to the L level when it is in the other area. Therefore, the number of elements and power consumption can be significantly reduced by omitting the exclusive OR gate. it can.

According to the second aspect of the invention, a plurality of pre-amplifiers for receiving a common analog signal and a reference voltage and generating complementary non-inverted voltage signals and inverted voltage signals, a plurality of latched transistors. As an analog-to-digital converter including a comparator and a coding means, a reference voltage corresponding to a balanced point of complementary output voltages of a pre-amplifier is generated through a reference voltage generation circuit, while an OR circuit always generates a non-inverted output voltage. And output the OR logic of the inverted output voltage,
Since the latched comparator compares and latches the output voltage of the OR circuit with the reference voltage, it is possible to obtain the same effect as in claim 1 and to improve the reliability in high speed operation. it can.

According to the invention of claim 3, in addition to the invention of claim 2, the complementary voltage of the non-inverting output voltage of one pre-amplifier and the complementary voltage of the inverting output voltage of another pre-amplifier are provided. An AND circuit that receives and outputs an output voltage corresponding to the voltage on the lower potential side of each complementary voltage is arranged, and the output voltage of the OR circuit is compared with the output voltage of the AND circuit by the latched comparator and latched. Since the configuration is adopted, the output of the OR circuit having a V-shaped waveform and the AND having a Λ-shaped waveform
Due to the differential gain with the output of the circuit, the output signal strength is doubled. Therefore, in addition to the same effect as the invention of claim 2,
The conversion accuracy can be improved.

According to the invention of claim 4, the above-mentioned claim 1,
In the invention of 2 or 3, since the input of the latched comparator is taken from the complementary output voltage corresponding to the transition of the logic of the digital output, and the coding of the output of the latched comparator can be directly performed, it is exclusive. Not only the logical OR gate but also the number of latched comparators can be significantly reduced, and thus the number of elements and power consumption can be significantly reduced.

[Brief description of drawings]

FIG. 1 is an electrical wiring diagram showing a basic configuration of a pre-amplifier and a latched comparator of an analog / digital converter according to a first embodiment.

FIG. 2 is a diagram showing a complementary output voltage characteristic of a preamplifier and an input voltage characteristic to a latched comparator in the first embodiment.

FIG. 3 is an electrical wiring diagram of the 3-bit analog-digital converter in the first embodiment.

FIG. 4 is an electrical wiring diagram showing a basic configuration of a pre-amplifier and a latched comparator of an analog / digital converter according to a second embodiment.

FIG. 5 is an electrical wiring diagram showing a basic configuration of a pre-amplifier and a latched comparator of an analog / digital converter according to a third embodiment.

FIG. 6 is a diagram showing complementary output voltage characteristics of a preamplifier and output voltage characteristics of an OR circuit and an AND circuit according to a third embodiment.

FIG. 7 is an electrical wiring diagram of a 3-bit analog-digital converter that performs direct coding in the fourth embodiment to which the invention of claim 1 is applied.

FIG. 8 is a diagram showing a waveform of a digital signal of an encoder in the fourth embodiment.

FIG. 9 is an electrical wiring diagram of a 3-bit analog-digital converter that performs direct coding in a fourth embodiment to which the invention of claim 2 is applied.

FIG. 10 is an electrical wiring diagram of a 3-bit analog-digital converter that performs direct coding in the fourth embodiment to which the invention of claim 3 is applied.

FIG. 11 is an electrical wiring diagram of a conventional 3-bit analog-digital converter.

[Explanation of symbols]

 1 Reference Resistor Section 2 Pre-Amplifier Array 3 Latched Comparator Array 4 Exclusive OR Gate Array 5 Analog Input Signal Input Section 6 Encoder Section 7 Dotting Transistor 8 Reference Voltage Generation Circuit 9a Wired OR Circuit 9b OR Circuit 10 AND Circuit LC latched comparator PA preamplifier Q1 to Q9 transistor CN wiring means

Claims (4)

[Claims] 1. A complementary non-inverted voltage signal and an inverted voltage signal, wherein one input portion receives a common analog signal and the other input portion sequentially receives a reference voltage signal set with a predetermined voltage difference. A plurality of pre-configured to generate
An analog-digital converter comprising: an amplifier; a plurality of latched comparators that receive the output of the pre-amplifier; and coding means that performs coding based on the digital output of the latched comparator. A reference voltage generating circuit for generating a reference voltage signal corresponding to the balanced point of the complementary output voltage of the amplifier is provided, and at least one group of the latched comparators includes at least one of the plurality of pre-amplifiers. A non-inverted voltage signal from the pre-amplifier, an inverted voltage signal from another pre-amplifier, and a reference voltage signal from the reference voltage generation circuit.
An analog-to-digital converter, which is configured to compare and latch a high-potential-side voltage of the non-inverted output voltage and the inverted output voltage with the reference voltage. 2. A complementary non-inverted voltage signal and an inverted voltage signal, wherein one input portion receives a common analog signal and the other input portion sequentially receives a reference voltage signal set with a predetermined voltage difference. A plurality of pre-configured to generate
An analog-digital converter comprising: an amplifier; a plurality of latched comparators for receiving outputs of the pre-amplifier; and coding means for performing coding based on a digital output of the latched comparator, Of the preamplifiers, the noninverting voltage signal from one of the preamplifiers and the inverting output voltage from the other preamplifier are input, An OR circuit for generating an output voltage according to the voltage on the higher potential side, and a reference voltage generating circuit for generating a reference voltage signal corresponding to the equilibrium point of the complementary output voltages of the pre-amplifier. The comparator receives the output signal of the OR circuit and the output signal of the reference voltage generation circuit 2
An analog-to-digital converter having two input sections and configured to compare and latch the output voltage of the OR circuit and the reference voltage. 3. A complementary non-inverted voltage signal and an inverted voltage signal, wherein one input portion receives a common analog signal, and the other input portion sequentially receives a reference voltage signal set with a predetermined voltage difference. A plurality of pre-configured to generate
An analog-digital converter comprising: an amplifier; a plurality of latched comparators for receiving outputs of the pre-amplifier; and coding means for performing coding based on a digital output of the latched comparator, Of the preamplifiers, the noninverting voltage signal from one of the preamplifiers and the inverting output voltage from the other preamplifier are input, An OR circuit that generates an output voltage according to the voltage on the higher potential side, a complementary voltage (inverted output voltage) of the non-inverted output voltage generated by the one pre-amplifier and the other pre-amplifier. A complementary voltage of the inverted output voltage (non-inverted output voltage) is input, and an output voltage corresponding to the voltage on the low potential side of the two input voltages is generated A A D circuit, the a latched comparator, the output voltage and that the analog-digital converter, characterized in that by comparing the output voltage of the AND circuit is configured to latch the OR circuit. 4. The analog-to-digital converter according to claim 1, 2 or 3, wherein the non-inverting output voltage and the inverting output voltage of each of the pre-amplifiers are input voltages corresponding to the logic switching of the digital output signal. The analog-to-digital converter is characterized in that it is taken from complementary output voltages crossing at, and the coding means is configured to be directly coded at the output of the latched comparator.