JP2696905B2 - Input circuit of parallel type AD converter - Google Patents

Description

The present invention relates to an AD for converting an analog signal into a digital signal.
More specifically, the present invention relates to a circuit for reducing the input capacitance of a parallel type AD converter which is a high-speed AD converter.

[Summary of the Invention]

The parallel AD converter according to the present invention further comprises a circuit means for supplying an input analog signal via an amplifier having a voltage gain of 1 to the collector of one input transistor of the comparator to which the input analog signal is supplied, Since a voltage fluctuation equal to the voltage fluctuation of the base electrode to which the analog signal is supplied is applied to the collector electrode, the influence of the junction capacitance between the base and the collector is reduced. Therefore, an analog signal can be converted into a digital signal at a high sample rate.

[Conventional technology]

 FIGS. 3 to 5 show a conventional parallel type AD converter.

The circuit side of the parallel type AD converter shown in FIG. 5 converts the input signal _VIN into a 4-bit digital signal.

In this figure, an input signal e _IN is input to one input terminal of comparators COMP _{1 to} COMP ₁₆ connected in parallel.
The other input terminal of the comparator COMP ₁ ~COMP _16, although each reference voltage V _rof is input, the comparators COMP ₁ ~COMP ₁₆
Is a resistor R which is connected in _series with the reference input voltage V _rof.
Is generated by partial pressure.

16 output of the comparator COMP ₁ ~COMP ₁₆ ( _"1" is a level or "0" level.) Is converted into a binary code by a logic circuit L, the digital signal D ₁ to D ₄ is obtained in 4bit Can be

In some cases, the outputs of the comparators COMP _{1 to} COMP ₁₆ are input to an encoder, and then converted into a binary signal by the logic circuit L.

In such a parallel type AD converter, the input terminal
Since one input terminal of many comparators connected in parallel is connected to e _IN , even though the input capacitance of each of the comparators is small, the input capacitance seen from the input terminal e _IN to which the input signal is applied Is increased 16 times with a 4-bit AD converter and 256 times with an 8-bit AD converter, and therefore has a problem when converting an analog signal to a digital signal at high speed.

 This will be described with reference to FIGS. 3 and 4.

FIG. 3 and FIG. 4 show only the circuit of the input part of the comparator in the parallel type AD converter.

The circuit shown in FIG. 3 is an example of a circuit in which an emitter follower is used as an input circuit portion, and an input signal e _IN is input to the bases of the transistors T _{11 to} T _n1 .
Transistor T ₁₁ through T _n1 forms a emitter follower, the emitter output is supplied to the bases of the comparator COMP ₁ serves as one input of ～COMP _n transistors T ₁₂ through T _n2.

Reference voltages V _{rof1 to} V applied to the other input side of the comparator
_rofn is, each emitter-follower transistor T ₁₄ ~T
is applied to _n4 based, the emitter output is supplied to the base of the transistor T ₁₃ through T _n3 constituting the other input of the comparator.

In the circuit of FIG. 3, the input capacitance as viewed from the input terminal e _IN is obtained and examined. Emitter follower transistors T _{11 to} T
_Let the capacitance between the base and collector of _n1 be C _jc .

When the converter to obtain a binary code of N bits, the number of comparators is the 2 _N pieces required. Also, since the mirror effect does not occur in the emitter follower transistor, the input terminal
The capacitance C _IN viewed from e _IN is: C _IN = 2 ^N · C _jc (1)

Also, Figure 4 is an emitter follower transistor T ₁₁ through T _n1 and T ₁₄ through T _n4 of FIG. 3 are shown the input circuit of the comparator is omitted.

In the circuit of FIG. 4, the input capacitance as viewed from the input terminal
When C _IN is obtained, in an N-bit AD converter, C _IN = 2 ^N (1 + G) G _jc + C ′ (2) where G is the gain of the transistors T _{11 to} T _n1 .

In FIG. 4, since the capacitance C _jc between the base and the collector becomes (1 + G) due to the Miller effect, the expression is as shown in Expression (2).

Incidentally, C 'is the transistor T ₁₁ through T _n1 and transistor
T is a total specific capacity to come visible in a volume such as between ₁₂ base-emitter capacitance of the through T _n2 and collector sub constant current source circuit.

[Problems to be solved by the invention]

As described above, in the conventional parallel type AD converter, the input capacity for the input analog signal increases exponentially as the number N of converted bits increases, and it is difficult to increase the speed. Also, in order to achieve high speed in a conventional circuit, a drive circuit which can obtain a large output with low impedance is required, and there is a problem that power loss increases.

The present invention has been made in view of such a point, and an object of the present invention is to provide an AD converter circuit that can reduce input capacitance with a simple configuration and that can operate at high speed.

[Means for solving the problem]

According to the present invention, an apparent input capacitance seen from an input terminal is reduced by adding circuit means for changing a collector of a transistor in an input circuit portion in the same manner as a change in an input signal.

[Action]

If the potentials of the base and collector of the transistor in the input circuit part change in the same way, the capacitance C _jc between the base and collector will apparently not function for the input analog signal, and the effect of the capacitance C _jc may be eliminated. it can.

〔Example〕

FIG. 1 shows a first embodiment of an input circuit portion of a parallel type AD converter according to the present invention.

In Figure 1, the transistor T ₁₂ through T _n2 comparators COMP
_{1 to} COMP _n constitute a portion to which input signals are applied, and the transistors T _{13 to} T _n3 are provided with reference voltages V _{rcf1 to} V _{rcf1 to} V of comparators COMP _{1 to} COMP _n.
It constitutes the part to which _rofn is added.

Transistor T ₁₁ through T _n1 is a emitter follower circuit, the input signal supplied to the input terminal IN to the respective bases is applied. Transistor T ₁₄ through T _n4 also an emitter follower circuit, the reference voltage to the respective bases
V _{rof1 to} V _rofn are applied.

Actually, the outputs of the comparators COMP ₁ and COMP ₂ are input to the logic circuit via the output transistors T ₅ and T ₆ as shown by the dashed line.

The collector of the transistor T ₁₁ through T _n1 of the analog input side is connected to the emitter of the transistor T _01, the transistor T ₀₁ is operated as a buffer amplifier voltage gain becomes 1 as will be described later.

The transistors _T02 and _T03 constitute an amplifier having a voltage gain of 1. That is, since the resistor R is connected between the emitters of both transistors and the collector of the transistor _T02 is connected to make the resistance values of both resistors equal, the gain of this differential amplifier is one.

Since the input circuit of the AD converter of the present invention is configured as described above, the input signal e _IN supplied to the input terminal _IN is applied to the comparators COMP _{1 to} COMP _n via the transistors T _{11 to} T _n1 and the transistors T will be compared with a reference voltage supplied through the ₁₄ through T _n4.

Also, the input signal e _IN is simultaneously applied to the transistor T of the differential amplifier.
Also joins the base of ₀₃ . The collector of the transistor T ₀₂ is the output of the differential amplifier, with the input signal e _IN is outputted in the same phase, because the amplitude gain becomes R / R = 1,
The input signal e _IN is supplied to the base of the transistor _T01 as it is.

Therefore, the input signal e _IN is output to the emitter of the transistor T ₀₁ , so that one of the input transistors T ₁₁
The base and collector of ~ T _n1 will be swung in the same direction by the input signal e _IN .

That is, since the input signal e _IN which is supplied to the base of the transistor T ₁₁ through T _n1 will be supplied to the collector of the same transistor, even if there is capacity between the base and collector, in this capacity No current corresponding to the input signal e _IN flows, and apparently this capacitance is
Can be ignored for _IN .

Therefore, the input capacitance as viewed from the input terminal IN wiring capacitance and stray capacitance (because of the emitter-follower, the base-emitter capacitance is negligible) can be seen as, these of total capacity in the capacitor C _jc of the base-collector Since it is extremely small in comparison, the input capacitance seen from the input terminal IN can be made quite small by the circuit means of the transistors T ₀₁ , T ₀₂ and T ₀₃ .

FIG. 2 shows a part of an input circuit of a parallel type AD converter without an emitter follower circuit as a second embodiment of the present invention.

In Figure 2, the base of the transistor T ₁₁ through T _n1 and transistor T ₁₂ through T _n2 and constitute a plurality of comparators COMP ₁ ~COMP _n, the input of one comparator transistor T ₁₁ through T _n1 The input signal e _IN supplied to the input terminal IN is applied to
Reference voltages V _{rof1 to} V _rofn are applied to the bases of the other input transistors T _{12 to} T _n2 of the comparator, respectively.

Circuit means such that the voltage gain becomes 1 in the case of this embodiment is constituted by a differential amplifier of the transistors T ₀₁ and T _02, which are connected between the emitters of both transistors of the resistor R and the transistor T ₀₂ By making the resistance value equal to the resistance value of the resistor R connected to the collector, the gain of the differential amplifier becomes 1.

Then, the output of the transistor T ₀₂ is supplied to the base of the transistor T ₁₃ through T _n3 that is inserted into the collector of each transistor constituting the comparator.

Also in the case of this embodiment, the input signal e _IN supplied to the input terminal IN is applied to all the bases of the transistors T _{11 to} T _{n1 and} the reference voltage applied to the other transistors T _{12 to} T _n2. However, the input signal e _IN is also applied to the base of the transistor _T01 . Transistor T _01, since the gain of the differential amplifier comprised of transistors T ₀₂ is a 1, the collector of T ₀₂ the input signal e _IN is output as it is, this output signal to the base of the transistor T ₁₃ through T _n3 Supplied.

Since the transistor T ₁₃ through T _n3 operates as a buffer, one of the collector of the input transistor T ₁₁ through T _n1 of the comparator will be swung by the input signal e _IN.

Thus, the base-collector voltage of the transistor T ₁₁ through T _n1 becomes possible to vary at the same level by the input signal e _IN, the base-collector capacitance of the transistor T ₁₁ through T _n1 is the current due to the input signal e _IN It stops flowing. This means that the base-collector capacitance is apparently the input signal e _IN
Input terminal IN
, The input capacitance becomes very small.

Note that since the transistor T ₁₄ through T _n4 is operating well balanced comparator COMP ₁ ~COMP _n, not necessarily required to be one which takes into the collector of the transistor T ₁₂ through T _n2 reference voltage side .

The amplification means having a gain of 1 may use another circuit type.

〔The invention's effect〕

As described above, according to the present invention, amplifying means having a gain of 1 is added to a plurality of comparators constituting an AD converter, and one input of the comparator to which an input signal is applied is provided. Since the collector of the transistor is made to swing by the input signal, the input capacitance seen from the input terminal can be made very small, enabling high-speed operation of a parallel type AD converter that converts especially with high bits. It is effective.

[Brief description of the drawings]

1 is a circuit diagram of a first embodiment of the present invention, FIG. 2 is a circuit diagram of a second embodiment of the present invention, FIGS. 3 and 4 are diagrams showing a conventional input circuit portion, and FIG. FIG. 1 is a schematic diagram of a conventional parallel AD converter. In the _{figure, T 11 ~T n1, T 12} ~T n2, T 13 ~T n3, T 14 ~T n4, and T ₀₁
~ T ₀₃ is a transistor, COMP ₁ ~ COMP _n is a comparator, V _rof1 ~
V _rofn is a reference voltage.

Claims (1)

(57) [Claims] An input analog signal is provided with 2 ^N comparators in parallel, an input analog signal is applied to one input of each of the comparators, and a different reference voltage is sequentially applied to the other input. In the input circuit of the parallel type AD converter, in which an N-bit digital signal is obtained from the output of the comparator, the input analog signal supplied to the input terminal is converted into one of the input transistors constituting the comparator. Circuit means for applying the input analog signal to the respective collectors of the one input transistor via an amplifier having a gain of 1, and applying the input analog signal to the base and the collector of the one input transistor. An input circuit for a parallel type AD converter, wherein input circuits are configured to apply input analog signals having the same amplitude.