JPH01272232A - Input circuit for parallel ad converter - Google Patents

Abstract

PURPOSE:To apparently reduce an input capacity by adding a circuit means which changes collectors of transistors TRs in an input circuit part in accordance with the change of an input signal. CONSTITUTION:An input signal eIN supplied to an input terminal IN is not only supplied to comparators COMP1-COMPn through TRs T11-Tn1 but also compared with the reference voltage supplied through TRs T14-Tn4. The input signal eIN is applied to the base of a TR T03 of a differential amplifier also. Since the input signal eIN is outputted to the collector of a TR T02 of the output of the differential amplifier with the same phase and the amplitude gain is one, the input signal eIN is supplied to the base of a TR T01 as it is. Consequently, since the input signal eIN is outputted to the emitter of the TR T01, bases and collectors of input TRs T11-Tn1 of comparators are shaked in the same direction by the input signal eIN. Thus, a current corresponding to the input signal eIN does not flow to the input capacity, and this input capacity can be apparently ignored for the input signal eIN.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an AD converter that converts an analog signal into a digital signal.
The present invention relates to a converter, and more specifically, to a circuit that reduces the input capacitance of a parallel AD converter, which is a high-speed AD converter.

[Summary of the invention]

The parallel AD converter of the present invention adds circuit means for supplying an input analog signal via an amplifier with a voltage gain of 1 to the collector of one input transistor of the comparator to which the input analog signal is supplied, Since a voltage fluctuation equal to the voltage fluctuation of the base electrode to which an input analog signal is supplied is applied to the collector electrode, the influence of junction capacitance between the base and collector is reduced. Therefore, it becomes possible to convert analog signals to digital signals at a high sample rate.

[Conventional technology]

Conventional parallel AD converters are shown in FIGS. 3 to 5.

The circuit side of the parallel AD converter shown in FIG. 5 converts the input signal VIN into a 4 b i ,t digital signal.

In this figure, the input signal elN is input to one input terminal of 16 comparators GOMP, -COM P lb connected in parallel. Comparator GOMPI~COM P lb
The reference voltage V ret is input to the other input terminal of each comparator COMPI −COM P +
The reference voltage b is generated by dividing the reference input voltage Vref by resistors R connected in series.

The 16 outputs of the comparators COMF, ~COMP+6 (“l
"level or "0" level) is converted into a binary code by a logic circuit and output as a 4-bit digital signal D1~
D4 is obtained.

Note that the outputs of the comparators GOM P 1-G OM P lb may be input to an encoder and then converted into a binary signal by a logic circuit.

In such a parallel AD converter, one input terminal of many comparators connected in a cage is connected to the input terminal eis, so even if the input capacitance of each comparator is small, the input signal is The input capacitance seen from the applied input terminal SIN is 16 times larger for a 4-bit AD converter and 256 times larger for an 8-bit AD converter, so it takes much longer to convert an analog signal to a digital signal at high speed. I have a contact person.

This will be explained using FIGS. 3 and 4.

FIGS. 3 and 4 show only the input portion of the comparator circuit in the parallel AD converter.

The circuit shown in FIG. 3 shows an example of a circuit in which an emitter follower is used as an input circuit part, and an input signal elN is input to the bases of transistors Tit to Tnl, respectively. The transistors Tll to T n I form an emitter follower, whose emitter output is connected to the comparator COM
It is supplied to the bases of transistors T12 to Tn2, which are one input-side of PI to COM Pn, respectively.

Reference voltage V r e applied to the other input side of the comparator
f I to Vrefn are applied to the bases of emitter follower transistors T la '' T ns, respectively, and their emitter outputs are supplied to the bases of transistors T13 to Tn3 forming the other input side of the comparator.

In the circuit shown in FIG. 3, the input capacitance seen from the input terminal elH is determined and viewed. Emitter follower transistor T l
Let the base-collector capacitance of l''Tnl be CjC.

In the case of a converter that obtains an N-bit binary code, 2N comparators are required. Also, since the mirror effect does not occur in the emitter follower transistor, the capacitance CIN seen from the input terminal eIN is CIN=2''
Self Cj c −・
−・・・(1).

Further, FIG. 4 shows the input circuit side of the comparator with the emitter follower transistors Tll to Tnl and T14 to Tn4 of FIG. 3 omitted.

In the circuit shown in Figure 4, the input capacitance C seen from the input terminal
When calculating IN, for an N-bit AD converter, C+N=2No(1+G)Cjc ・・・・・・(2
) However, G is the gain of the transistor T++-Tn+.

In FIG. 4, the capacitance C3c between the base and the collector becomes (1+G) due to the Miller effect, so that an equation like equation (2) is obtained.

Note that the effects of the pace emitter capacitance and stray capacitance are small, so they are omitted.

[Problem that the invention seeks to solve]

As described above, in the conventional parallel fiAD dual inverter, the input capacity for the input analog signal increases exponentially as the number of conversion bits N increases, making it difficult to increase the speed. Furthermore, in order to achieve higher speeds with conventional circuits, a drive circuit that can obtain a large output with low impedance is required, which poses the problem of increased power loss.

The present invention was devised in view of these points.
A simple configuration reduces input capacity and increases speed.
The purpose is to provide a D converter circuit.

[Means for solving problems]

In the present invention, the collector of the transistor in the input circuit portion is
The apparent input capacitance seen from the input terminal is reduced by adding circuit means that changes the input signal in the same way as the input signal changes.

[Effect]

If the potentials of the base and collector of the transistors in the input circuit change in the same way, the capacitances C and e between the base and collector will apparently no longer function for the input analog signal, and the influence of the capacitances C and e will disappear. (I can do great things.

〔Example〕

FIG. 1 shows a first embodiment of an input circuit portion of a parallel AD converter according to the present invention.

In FIG. 1, transistors TI2 to T02. constitutes a part to which the input signal of the comparator COM P l'' COM P n is applied, and the transistors T I 3 to Tn3 form the reference voltage V of the comparator G OM P l'' COM P n
It constitutes a part to which refl to Vrefn are added.

The transistors Tll to Tnl are emitter follower circuits, and the input signals supplied to the input terminal IN are applied to their respective bases. Transistor T1
4 to T and 14 are also emitter follower circuits, and reference voltages Vrefl to Vrefn are applied to their respective bases.

Note that, in practice, the output of each comparator GOMP+ -GOMP2 is connected to the output transistor T5. It will be input to the logic circuit via T6.

Transistor T l l ” T n on the analog input side
The collector of 1 is connected to the emitter of transistor TO+, and transistor TO+ is operated as a buffer of an amplifier with a voltage gain of 1, as will be described later.

Transistors TO2 and Ta2 constitute an amplifier with a voltage gain of 1. That is, a resistor R is connected between the emitters of both transistors, and a resistor R is connected to the collector of the transistor TO2.
Since the resistance values of both resistors are made equal, the gain of this differential amplifier is 1.

Since the input circuit of the AD converter of the present invention is configured as described above, the input signal elN supplied to the input terminal IN is
is connected to the comparator C via transistors Tll to Tnl.
It is added to OMPI to COM P n and is compared with a reference voltage supplied via transistors T14 to T'n4.

Furthermore, the input signal elN is simultaneously applied to the base of the transistor TO3 of the differential amplifier. The human input signal e+N is outputted in the same phase to the collector of the transistor TO2 which is the output of the differential amplifier, and its amplitude has a gain R/R=
1, so the input signal eljl is supplied as is to the base of the transistor TOI.

Therefore, the input signal el is applied to the emitter of the transistor Tol.
N is output, so the base and collector of one of the input transistors Tll to Tnl of the comparator is connected to the input signal SI.
With N, it will be swung in the same direction.

In other words, the input signal e[H supplied to the base of the transistor T I I '' T n l is also supplied to the collector of the same transistor, so even if there is a capacitance between the base and collector, this No current corresponding to the input signal elH flows through the capacitor, and this capacitance can apparently be ignored with respect to the input signal elN.

Therefore, the input capacitance seen from the input terminal IN can be considered to be only the stray capacitance and the base-emitter capacitance, and since these total capacitances are extremely small compared to the base-collector capacitance Cjc, the input capacitance seen from the input terminal IN Capacity is transistor TOI.

Significantly smaller values can be achieved by means of the Te31 Ta2 circuit.

FIG. 2 shows the input circuit portion of a parallel AD converter without an emitter follower circuit as a second embodiment of the present invention.

In FIG. 2, a plurality of comparators COMP are formed by transistors Tll to Tnl and transistors TI2 to Tn2.
1 to COM Pn, the input signal elN supplied to the input terminal IN is applied to the base of one input transistor Tll to Tnl of the comparator, and the input signal elN supplied to the input terminal IN is applied to the base of one input transistor Tll to Tnl of the comparator; (7) Each base has a reference voltage V r e f r ” V r
e f n is applied.

In this embodiment as well, the four-circuit means is composed of a differential amplifier made up of transistors T o 1 and Te2 so that the voltage gain is 1, and a resistor R connected between the emitters of both transistors and the collector of the transistor TO2 is used. The gain of the differential amplifier is 1 by making the resistance value equal to that of the resistor R connected to the differential amplifier.

The output of the transistor TO2 is supplied to the bases of the transistors T I 3 to Tn3 and T14 to Tni inserted into the collectors of the respective transistors constituting the comparator.

In this embodiment as well, the input signal elN supplied to the input terminal IN is transmitted through the transistors Tll to T n 1 (7) t
The input signal eIN is applied to the bases of all transistors and is compared with the reference voltage applied to the other transistors TI2 to Tn2.
Also applied to the base of the OI. Since the gain of the differential amplifier consisting of the transistor TOI and the transistor TO2 is set to 1, the input signal elN is output as is to the h-rector of Te2, and this output signal is output to the transistor T13.
~Tn3 and T1-~"r, , are supplied to the bases of each of them.

The transistors TI2 to Tn3 operate as buffers, and one of the input transistors Tll to Tn of the comparator
The collector of l will be swung by the input signal eIN.

Therefore, the base-collector voltages of transistors Tll to Tn1 (7) will fluctuate at the same level depending on the input signal eIN, and no current will flow through the base-collector capacitance of transistors Tll to Tnl due to the input signal e1M. . This is the same as apparently ignoring the base-collector capacitance with respect to the human input signal elN, so the input capacitance seen from the input terminal IN becomes very small.

Note that Y transistors T14 to Tn4 are comparators GOMP.
In order to operate 1 to COM P n in a well-balanced manner,
This is a useless transistor that causes the collectors of the transistors T12 to Tn2 on the reference voltage side to be swung by the input signal elN, and is not necessarily necessary.

Note that other circuit types may be used as the amplifying means with a gain of 1.

〔Effect of the invention〕

As described above, according to the present invention, an amplification means having a gain of 1 is added to a plurality of comparators constituting an AD converter, and one input of the comparator to which an input signal is applied is Since the collector of the transistor is made to swing by the input signal, the input capacitance seen from the input terminal can be made extremely small, which enables high-speed operation of parallel AD converters, especially those that convert at high bits. It is effective.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, FIG. 2 is a circuit diagram of a second embodiment of the present invention, FIGS. 3 and 4 are diagrams showing conventional input circuit parts, and FIG. 5 1 is a schematic diagram of a conventional parallel AD converter. In the figure, Tll"'Tnl, T'12NT'n2,
Te5NTn3゜T (a ~ T n 41 and TO
I~TO3 are transistors, COM F1~COM
P n is a comparator, V r e f l ”' V r
e f n is a reference voltage.

Claims (1)

[Claims] 2^N comparators are arranged in parallel with respect to the input analog signal, and the input analog signal is applied to one input of each of the comparators, and different reference voltages are sequentially applied to the other input, respectively. In an input circuit of a parallel AD converter configured to obtain an N-bit digital signal from a comparator output, an input analog signal supplied to an input terminal is applied to each base of one input transistor constituting the comparator. and circuit means for applying the input analog signal to the collector of each of the one input transistors via an amplifier with a gain of 1, and applying an input analog signal of the same amplitude to the base and collector of each of the one input transistors. An input circuit for a parallel AD converter, characterized in that it is configured to apply a signal.